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IB/hns: Fix for Checkpatch.pl comment style errors

Browse source 
This patch correct the comment style errors caught by
checkpatch.pl script

Signed-off-by: Salil Mehta  <salil.mehta@huawei.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
Salil 2016-11-23 19:41:09 +00:00 • committed by Doug Ledford
parent 8254746978
commit e84e40be8e
6 changed files with 66 additions and 66 deletions
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8
drivers/infiniband/hw/hns/hns_roce_cmd.c
View file

@ -216,10 +216,10 @@ static int __hns_roce_cmd_mbox_wait(struct hns_roce_dev *hr_dev, u64 in_param,
goto out; goto out;
/* /*
* It is timeout when wait_for_completion_timeout return 0 * It is timeout when wait_for_completion_timeout return 0
* The return value is the time limit set in advance * The return value is the time limit set in advance
* how many seconds showing * how many seconds showing
*/ */
if (!wait_for_completion_timeout(&context->done, if (!wait_for_completion_timeout(&context->done,
msecs_to_jiffies(timeout))) { msecs_to_jiffies(timeout))) {
dev_err(dev, "[cmd]wait_for_completion_timeout timeout\n"); dev_err(dev, "[cmd]wait_for_completion_timeout timeout\n");

28
drivers/infiniband/hw/hns/hns_roce_device.h
View file

@ -201,9 +201,9 @@ struct hns_roce_bitmap {
/* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */ /* Order = 0: bitmap is biggest, order = max bitmap is least (only a bit) */
/* Every bit repesent to a partner free/used status in bitmap */ /* Every bit repesent to a partner free/used status in bitmap */
/* /*
* Initial, bits of other bitmap are all 0 except that a bit of max_order is 1 * Initial, bits of other bitmap are all 0 except that a bit of max_order is 1
* Bit = 1 represent to idle and available; bit = 0: not available * Bit = 1 represent to idle and available; bit = 0: not available
*/ */
struct hns_roce_buddy { struct hns_roce_buddy {
/* Members point to every order level bitmap */ /* Members point to every order level bitmap */
unsigned long **bits; unsigned long **bits;
@ -365,25 +365,25 @@ struct hns_roce_cmdq {
struct mutex hcr_mutex; struct mutex hcr_mutex;
struct semaphore poll_sem; struct semaphore poll_sem;
/* /*
* Event mode: cmd register mutex protection, * Event mode: cmd register mutex protection,
* ensure to not exceed max_cmds and user use limit region * ensure to not exceed max_cmds and user use limit region
*/ */
struct semaphore event_sem; struct semaphore event_sem;
int max_cmds; int max_cmds;
spinlock_t context_lock; spinlock_t context_lock;
int free_head; int free_head;
struct hns_roce_cmd_context *context; struct hns_roce_cmd_context *context;
/* /*
* Result of get integer part * Result of get integer part
* which max_comds compute according a power of 2 * which max_comds compute according a power of 2
*/ */
u16 token_mask; u16 token_mask;
/* /*
* Process whether use event mode, init default non-zero * Process whether use event mode, init default non-zero
* After the event queue of cmd event ready, * After the event queue of cmd event ready,
* can switch into event mode * can switch into event mode
* close device, switch into poll mode(non event mode) * close device, switch into poll mode(non event mode)
*/ */
u8 use_events; u8 use_events;
u8 toggle; u8 toggle;
}; };

6
drivers/infiniband/hw/hns/hns_roce_eq.c
View file

@ -371,9 +371,9 @@ static int hns_roce_aeq_ovf_int(struct hns_roce_dev *hr_dev,
int i = 0; int i = 0;
/** /**
* AEQ overflow ECC mult bit err CEQ overflow alarm * AEQ overflow ECC mult bit err CEQ overflow alarm
* must clear interrupt, mask irq, clear irq, cancel mask operation * must clear interrupt, mask irq, clear irq, cancel mask operation
*/ */
aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG); aeshift_val = roce_read(hr_dev, ROCEE_CAEP_AEQC_AEQE_SHIFT_REG);
if (roce_get_bit(aeshift_val, if (roce_get_bit(aeshift_val,

6
drivers/infiniband/hw/hns/hns_roce_hem.c
View file

@ -80,9 +80,9 @@ struct hns_roce_hem *hns_roce_alloc_hem(struct hns_roce_dev *hr_dev, int npages,
--order; --order;
/* /*
* Alloc memory one time. If failed, don't alloc small block * Alloc memory one time. If failed, don't alloc small block
* memory, directly return fail. * memory, directly return fail.
*/ */
mem = &chunk->mem[chunk->npages]; mem = &chunk->mem[chunk->npages];
buf = dma_alloc_coherent(&hr_dev->pdev->dev, PAGE_SIZE << order, buf = dma_alloc_coherent(&hr_dev->pdev->dev, PAGE_SIZE << order,
&sg_dma_address(mem), gfp_mask); &sg_dma_address(mem), gfp_mask);

56
drivers/infiniband/hw/hns/hns_roce_hw_v1.c
View file

@ -1352,9 +1352,9 @@ static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
} }
/* /*
* Now backwards through the CQ, removing CQ entries * Now backwards through the CQ, removing CQ entries
* that match our QP by overwriting them with next entries. * that match our QP by overwriting them with next entries.
*/ */
while ((int) --prod_index - (int) hr_cq->cons_index >= 0) { while ((int) --prod_index - (int) hr_cq->cons_index >= 0) {
cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe); cqe = get_cqe(hr_cq, prod_index & hr_cq->ib_cq.cqe);
if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M, if ((roce_get_field(cqe->cqe_byte_16, CQE_BYTE_16_LOCAL_QPN_M,
@ -1376,9 +1376,9 @@ static void __hns_roce_v1_cq_clean(struct hns_roce_cq *hr_cq, u32 qpn,
if (nfreed) { if (nfreed) {
hr_cq->cons_index += nfreed; hr_cq->cons_index += nfreed;
/* /*
* Make sure update of buffer contents is done before * Make sure update of buffer contents is done before
* updating consumer index. * updating consumer index.
*/ */
wmb(); wmb();
hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index); hns_roce_v1_cq_set_ci(hr_cq, hr_cq->cons_index);
@ -1473,7 +1473,7 @@ void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev,
roce_set_bit(cq_context->cqc_byte_32, roce_set_bit(cq_context->cqc_byte_32,
CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S, CQ_CQNTEXT_CQC_BYTE_32_TYPE_OF_COMPLETION_NOTIFICATION_S,
0); 0);
/*The initial value of cq's ci is 0 */ /* The initial value of cq's ci is 0 */
roce_set_field(cq_context->cqc_byte_32, roce_set_field(cq_context->cqc_byte_32,
CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M, CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M,
CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0); CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0);
@ -1490,9 +1490,9 @@ int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
notification_flag = (flags & IB_CQ_SOLICITED_MASK) == notification_flag = (flags & IB_CQ_SOLICITED_MASK) ==
IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL; IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL;
/* /*
* flags = 0; Notification Flag = 1, next * flags = 0; Notification Flag = 1, next
* flags = 1; Notification Flag = 0, solocited * flags = 1; Notification Flag = 0, solocited
*/ */
doorbell[0] = hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1); doorbell[0] = hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1);
roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1); roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1);
roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M, roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M,
@ -1647,10 +1647,10 @@ static int hns_roce_v1_poll_one(struct hns_roce_cq *hr_cq,
wq = &(*cur_qp)->sq; wq = &(*cur_qp)->sq;
if ((*cur_qp)->sq_signal_bits) { if ((*cur_qp)->sq_signal_bits) {
/* /*
* If sg_signal_bit is 1, * If sg_signal_bit is 1,
* firstly tail pointer updated to wqe * firstly tail pointer updated to wqe
* which current cqe correspond to * which current cqe correspond to
*/ */
wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4, wqe_ctr = (u16)roce_get_field(cqe->cqe_byte_4,
CQE_BYTE_4_WQE_INDEX_M, CQE_BYTE_4_WQE_INDEX_M,
CQE_BYTE_4_WQE_INDEX_S); CQE_BYTE_4_WQE_INDEX_S);
@ -2072,11 +2072,11 @@ static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
} }
/* /*
*Reset to init * Reset to init
* Mandatory param: * Mandatory param:
* IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS * IB_QP_STATE | IB_QP_PKEY_INDEX | IB_QP_PORT | IB_QP_ACCESS_FLAGS
* Optional param: NA * Optional param: NA
*/ */
if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
roce_set_field(context->qpc_bytes_4, roce_set_field(context->qpc_bytes_4,
QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M, QP_CONTEXT_QPC_BYTES_4_TRANSPORT_SERVICE_TYPE_M,
@ -2584,9 +2584,9 @@ static int hns_roce_v1_m_qp(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
} }
/* /*
* Use rst2init to instead of init2init with drv, * Use rst2init to instead of init2init with drv,
* need to hw to flash RQ HEAD by DB again * need to hw to flash RQ HEAD by DB again
*/ */
if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) { if (cur_state == IB_QPS_INIT && new_state == IB_QPS_INIT) {
/* Memory barrier */ /* Memory barrier */
wmb(); wmb();
@ -2921,9 +2921,9 @@ static void hns_roce_v1_destroy_qp_common(struct hns_roce_dev *hr_dev,
if (hr_qp->ibqp.qp_type == IB_QPT_RC) { if (hr_qp->ibqp.qp_type == IB_QPT_RC) {
if (hr_qp->state != IB_QPS_RESET) { if (hr_qp->state != IB_QPS_RESET) {
/* /*
* Set qp to ERR, * Set qp to ERR,
* waiting for hw complete processing all dbs * waiting for hw complete processing all dbs
*/ */
if (hns_roce_v1_qp_modify(hr_dev, NULL, if (hns_roce_v1_qp_modify(hr_dev, NULL,
to_hns_roce_state( to_hns_roce_state(
(enum ib_qp_state)hr_qp->state), (enum ib_qp_state)hr_qp->state),
@ -2936,9 +2936,9 @@ static void hns_roce_v1_destroy_qp_common(struct hns_roce_dev *hr_dev,
sdbisusepr_val = roce_read(hr_dev, sdbisusepr_val = roce_read(hr_dev,
ROCEE_SDB_ISSUE_PTR_REG); ROCEE_SDB_ISSUE_PTR_REG);
/* /*
* Query db process status, * Query db process status,
* until hw process completely * until hw process completely
*/ */
end = msecs_to_jiffies( end = msecs_to_jiffies(
HNS_ROCE_QP_DESTROY_TIMEOUT_MSECS) + jiffies; HNS_ROCE_QP_DESTROY_TIMEOUT_MSECS) + jiffies;
do { do {

28
drivers/infiniband/hw/hns/hns_roce_main.c
View file

@ -148,8 +148,8 @@ static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
break; break;
case NETDEV_DOWN: case NETDEV_DOWN:
/* /*
* In v1 engine, only support all ports closed together. * In v1 engine, only support all ports closed together.
*/ */
break; break;
default: default:
dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event)); dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
@ -773,10 +773,10 @@ err_unmap_mtt:
} }
/** /**
* hns_roce_setup_hca - setup host channel adapter * hns_roce_setup_hca - setup host channel adapter
* @hr_dev: pointer to hns roce device * @hr_dev: pointer to hns roce device
* Return : int * Return : int
*/ */
static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev) static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
{ {
int ret; int ret;
@ -841,11 +841,11 @@ err_uar_table_free:
} }
/** /**
* hns_roce_probe - RoCE driver entrance * hns_roce_probe - RoCE driver entrance
* @pdev: pointer to platform device * @pdev: pointer to platform device
* Return : int * Return : int
* *
*/ */
static int hns_roce_probe(struct platform_device *pdev) static int hns_roce_probe(struct platform_device *pdev)
{ {
int ret; int ret;
@ -958,9 +958,9 @@ error_failed_get_cfg:
} }
/** /**
* hns_roce_remove - remove RoCE device * hns_roce_remove - remove RoCE device
* @pdev: pointer to platform device * @pdev: pointer to platform device
*/ */
static int hns_roce_remove(struct platform_device *pdev) static int hns_roce_remove(struct platform_device *pdev)
{ {
struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev); struct hns_roce_dev *hr_dev = platform_get_drvdata(pdev);