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spi/mxs: Make the SPI block clock speed configurable via DT

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Add "clock-frequency" property, which allows configuring the SPI block's
base speed.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This commit is contained in:
Marek Vasut 2012-08-22 22:38:35 +02:00 • committed by Mark Brown
parent f13639dc60
commit e64d07a2da
2 changed files with 19 additions and 6 deletions
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4
Documentation/devicetree/bindings/spi/mxs-spi.txt
View file

@ -6,6 +6,10 @@ Required properties:
- interrupts: Should contain SSP interrupts (error irq first, dma irq second) - interrupts: Should contain SSP interrupts (error irq first, dma irq second)
- fsl,ssp-dma-channel: APBX DMA channel for the SSP - fsl,ssp-dma-channel: APBX DMA channel for the SSP
Optional properties:
- clock-frequency : Input clock frequency to the SPI block in Hz.
Default is 160000000 Hz.
Example: Example:
ssp0: ssp@80010000 { ssp0: ssp@80010000 {

21
drivers/spi/spi-mxs.c
View file

@ -520,10 +520,17 @@ static int __devinit mxs_spi_probe(struct platform_device *pdev)
struct pinctrl *pinctrl; struct pinctrl *pinctrl;
struct clk *clk; struct clk *clk;
void __iomem *base; void __iomem *base;
int devid, dma_channel; int devid, dma_channel, clk_freq;
int ret = 0, irq_err, irq_dma; int ret = 0, irq_err, irq_dma;
dma_cap_mask_t mask; dma_cap_mask_t mask;
/*
* Default clock speed for the SPI core. 160MHz seems to
* work reasonably well with most SPI flashes, so use this
* as a default. Override with "clock-frequency" DT prop.
*/
const int clk_freq_default = 160000000;
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
irq_err = platform_get_irq(pdev, 0); irq_err = platform_get_irq(pdev, 0);
irq_dma = platform_get_irq(pdev, 1); irq_dma = platform_get_irq(pdev, 1);
@ -555,12 +562,18 @@ static int __devinit mxs_spi_probe(struct platform_device *pdev)
"Failed to get DMA channel\n"); "Failed to get DMA channel\n");
return -EINVAL; return -EINVAL;
} }
ret = of_property_read_u32(np, "clock-frequency",
&clk_freq);
if (ret)
clk_freq = clk_freq_default;
} else { } else {
dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
if (!dmares) if (!dmares)
return -EINVAL; return -EINVAL;
devid = pdev->id_entry->driver_data; devid = pdev->id_entry->driver_data;
dma_channel = dmares->start; dma_channel = dmares->start;
clk_freq = clk_freq_default;
} }
master = spi_alloc_master(&pdev->dev, sizeof(*spi)); master = spi_alloc_master(&pdev->dev, sizeof(*spi));
@ -598,12 +611,8 @@ static int __devinit mxs_spi_probe(struct platform_device *pdev)
goto out_master_free; goto out_master_free;
} }
/*
* Crank up the clock to 120MHz, this will be further divided onto a
* proper speed.
*/
clk_prepare_enable(ssp->clk); clk_prepare_enable(ssp->clk);
clk_set_rate(ssp->clk, 120 * 1000 * 1000); clk_set_rate(ssp->clk, clk_freq);
ssp->clk_rate = clk_get_rate(ssp->clk) / 1000; ssp->clk_rate = clk_get_rate(ssp->clk) / 1000;
stmp_reset_block(ssp->base); stmp_reset_block(ssp->base);