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platform/chrome: cros_ec_lpc: add a "quirks" system

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Some devices ship a ChromeOS EC in a non-standard configuration. Quirks
allow cros_ec_lpc to account for these non-standard configurations.

It only supports one quirk right now:
- CROS_EC_LPC_QUIRK_REMAP_MEMORY: use a different port I/O base for
  MMIO to the EC's memory region

Signed-off-by: Dustin L. Howett <dustin@howett.net>
Reviewed-by: Thomas Weißschuh <linux@weissschuh.net>
Tested-by: Thomas Weißschuh <linux@weissschuh.net>
Tested-by: Mario Limonciello <superm1@gmail.com>
Link: https://lore.kernel.org/r/20240403004713.130365-4-dustin@howett.net
Signed-off-by: Tzung-Bi Shih <tzungbi@kernel.org>
This commit is contained in:
Dustin L. Howett 2024-04-02 19:47:12 -05:00 • committed by Tzung-Bi Shih
parent c0e6ba2d0b
commit e4dbf9d65e
1 changed files with 31 additions and 0 deletions
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31
drivers/platform/chrome/cros_ec_lpc.c
View file

@ -34,6 +34,24 @@
/* True if ACPI device is present */ /* True if ACPI device is present */
static bool cros_ec_lpc_acpi_device_found; static bool cros_ec_lpc_acpi_device_found;
/*
* Indicates that lpc_driver_data.quirk_mmio_memory_base should
* be used as the base port for EC mapped memory.
*/
#define CROS_EC_LPC_QUIRK_REMAP_MEMORY BIT(0)
/**
* struct lpc_driver_data - driver data attached to a DMI device ID to indicate
* hardware quirks.
* @quirks: a bitfield composed of quirks from CROS_EC_LPC_QUIRK_*
* @quirk_mmio_memory_base: The first I/O port addressing EC mapped memory (used
* when quirk ...REMAP_MEMORY is set.)
*/
struct lpc_driver_data {
u32 quirks;
u16 quirk_mmio_memory_base;
};
/** /**
* struct cros_ec_lpc - LPC device-specific data * struct cros_ec_lpc - LPC device-specific data
* @mmio_memory_base: The first I/O port addressing EC mapped memory. * @mmio_memory_base: The first I/O port addressing EC mapped memory.
@ -363,8 +381,10 @@ static int cros_ec_lpc_probe(struct platform_device *pdev)
acpi_status status; acpi_status status;
struct cros_ec_device *ec_dev; struct cros_ec_device *ec_dev;
struct cros_ec_lpc *ec_lpc; struct cros_ec_lpc *ec_lpc;
struct lpc_driver_data *driver_data;
u8 buf[2] = {}; u8 buf[2] = {};
int irq, ret; int irq, ret;
u32 quirks;
ec_lpc = devm_kzalloc(dev, sizeof(*ec_lpc), GFP_KERNEL); ec_lpc = devm_kzalloc(dev, sizeof(*ec_lpc), GFP_KERNEL);
if (!ec_lpc) if (!ec_lpc)
@ -372,6 +392,17 @@ static int cros_ec_lpc_probe(struct platform_device *pdev)
ec_lpc->mmio_memory_base = EC_LPC_ADDR_MEMMAP; ec_lpc->mmio_memory_base = EC_LPC_ADDR_MEMMAP;
driver_data = platform_get_drvdata(pdev);
if (driver_data) {
quirks = driver_data->quirks;
if (quirks)
dev_info(dev, "loaded with quirks %8.08x\n", quirks);
if (quirks & CROS_EC_LPC_QUIRK_REMAP_MEMORY)
ec_lpc->mmio_memory_base = driver_data->quirk_mmio_memory_base;
}
/* /*
* The Framework Laptop (and possibly other non-ChromeOS devices) * The Framework Laptop (and possibly other non-ChromeOS devices)
* only exposes the eight I/O ports that are required for the Microchip EC. * only exposes the eight I/O ports that are required for the Microchip EC.