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drm/amdgpu: Show warning message if IH ring overflow
If IH primary ring and KFD ih fifo overflows, we may miss CP, SDMA interrupts and cause application soft hang. Show warning message with ring name if overflow happens. Add function to get ih ring name to avoid duplicating it. To keep warning message consistent between GPU generations, change all *_ih.c except ASICs older than Vega which has only one ih ring. Signed-off-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
de844846f7
commit
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6 changed files with 15 additions and 11 deletions
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@ -298,3 +298,9 @@ uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,
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dw2 = le32_to_cpu(ih->ring[ring_index + 2]);
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return dw1 | ((u64)(dw2 & 0xffff) << 32);
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}
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const char *amdgpu_ih_ring_name(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
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{
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return ih == &adev->irq.ih ? "ih" : ih == &adev->irq.ih_soft ? "sw ih" :
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ih == &adev->irq.ih1 ? "ih1" : ih == &adev->irq.ih2 ? "ih2" : "unknown";
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}
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@ -110,4 +110,5 @@ void amdgpu_ih_decode_iv_helper(struct amdgpu_device *adev,
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struct amdgpu_iv_entry *entry);
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uint64_t amdgpu_ih_decode_iv_ts_helper(struct amdgpu_ih_ring *ih, u32 rptr,
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signed int offset);
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const char *amdgpu_ih_ring_name(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
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#endif
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@ -434,9 +434,8 @@ static u32 navi10_ih_get_wptr(struct amdgpu_device *adev,
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* this should allow us to catch up.
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*/
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tmp = (wptr + 32) & ih->ptr_mask;
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dev_warn(adev->dev, "IH ring buffer overflow "
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"(0x%08X, 0x%08X, 0x%08X)\n",
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wptr, ih->rptr, tmp);
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dev_warn(adev->dev, "%s ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
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amdgpu_ih_ring_name(adev, ih), wptr, ih->rptr, tmp);
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ih->rptr = tmp;
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tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
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@ -364,9 +364,8 @@ static u32 vega10_ih_get_wptr(struct amdgpu_device *adev,
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* this should allow us to catchup.
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*/
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tmp = (wptr + 32) & ih->ptr_mask;
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dev_warn(adev->dev, "IH ring buffer overflow "
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"(0x%08X, 0x%08X, 0x%08X)\n",
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wptr, ih->rptr, tmp);
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dev_warn_ratelimited(adev->dev, "%s ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
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amdgpu_ih_ring_name(adev, ih), wptr, ih->rptr, tmp);
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ih->rptr = tmp;
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tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
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@ -444,9 +444,8 @@ static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
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* this should allow us to catchup.
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*/
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tmp = (wptr + 32) & ih->ptr_mask;
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dev_warn(adev->dev, "IH ring buffer overflow "
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"(0x%08X, 0x%08X, 0x%08X)\n",
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wptr, ih->rptr, tmp);
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dev_warn_ratelimited(adev->dev, "%s ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
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amdgpu_ih_ring_name(adev, ih), wptr, ih->rptr, tmp);
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ih->rptr = tmp;
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tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
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@ -108,8 +108,8 @@ void kfd_interrupt_exit(struct kfd_node *node)
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bool enqueue_ih_ring_entry(struct kfd_node *node, const void *ih_ring_entry)
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{
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if (kfifo_is_full(&node->ih_fifo)) {
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dev_dbg_ratelimited(node->adev->dev,
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"Interrupt ring overflow, dropping interrupt\n");
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dev_warn_ratelimited(node->adev->dev, "KFD node %d ih_fifo overflow\n",
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node->node_id);
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return false;
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}
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