arm64: dts: imx8-apalis: Add PCIe and SATA support

The needed drivers to support PCIe and SATA for i.MX 8QM have been
added.
Configure them for the Apalis iMX8 SoM.

The pciea and pcieb blocks each get a single PCIe lane, pciea is
available on the carrier boards while pcieb is connected to the
on module Wi-Fi/BT module.
The SATA lane is available on the carrier boards.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Max Krummenacher 2025-04-16 17:13:41 +02:00 committed by Shawn Guo
parent e05fae71e6
commit e2cfc140ae
5 changed files with 74 additions and 36 deletions

View file

@ -104,7 +104,10 @@
status = "okay";
};
/* TODO: Apalis PCIE1 */
/* Apalis PCIE1 */
&pciea {
status = "okay";
};
/* TODO: Apalis BKL1_PWM */
@ -121,7 +124,10 @@
status = "okay";
};
/* TODO: Apalis SATA1 */
/* Apalis SATA1 */
&sata {
status = "okay";
};
/* Apalis SPDIF1 */
&spdif0 {

View file

@ -191,7 +191,10 @@
status = "okay";
};
/* TODO: Apalis PCIE1 */
/* Apalis PCIE1 */
&pciea {
status = "okay";
};
/* TODO: Apalis BKL1_PWM */
@ -208,7 +211,10 @@
status = "okay";
};
/* TODO: Apalis SATA1 */
/* Apalis SATA1 */
&sata {
status = "okay";
};
/* Apalis SPDIF1 */
&spdif0 {

View file

@ -240,7 +240,10 @@
status = "okay";
};
/* TODO: Apalis PCIE1 */
/* Apalis PCIE1 */
&pciea {
status = "okay";
};
/* TODO: Apalis BKL1_PWM */
@ -257,7 +260,10 @@
status = "okay";
};
/* TODO: Apalis SATA1 */
/* Apalis SATA1 */
&sata {
status = "okay";
};
/* Apalis SPDIF1 */
&spdif0 {

View file

@ -339,6 +339,25 @@
pinctrl-0 = <&pinctrl_flexcan3>;
};
&hsio_phy {
fsl,hsio-cfg = "pciea-pcieb-sata";
fsl,refclk-pad-mode = "input";
status = "okay";
};
&hsio_refa_clk {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_sata_refclk>;
enable-gpios = <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>;
};
&hsio_refb_clk {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_wifi_refclk>;
clocks = <&hsio_refa_clk>;
enable-gpios = <&lsio_gpio2 11 GPIO_ACTIVE_HIGH>;
};
/* TODO: Apalis HDMI1 */
&gpu_alert0 {
@ -514,7 +533,10 @@
"MXM3_112",
"MXM3_118",
"MXM3_114",
"MXM3_116";
"MXM3_116",
"",
"",
"MXM3_26";
};
&lsio_gpio1 {
@ -586,15 +608,6 @@
"MXM3_183",
"MXM3_185",
"MXM3_187";
pcie-wifi-hog {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_wifi_refclk>;
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
line-name = "PCIE_WIFI_CLK";
output-high;
};
};
&lsio_gpio3 {
@ -660,16 +673,6 @@
"MXM3_291",
"MXM3_289",
"MXM3_287";
/* Enable pcie root / sata ref clock unconditionally */
pcie-sata-hog {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_sata_refclk>;
gpio-hog;
gpios = <11 GPIO_ACTIVE_HIGH>;
line-name = "PCIE_SATA_CLK";
output-high;
};
};
&lsio_gpio5 {
@ -771,9 +774,30 @@
status = "okay";
};
/* TODO: Apalis PCIE1 */
/* Apalis PCIE1 */
&pciea {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_moci>;
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
reset-gpio = <&lsio_gpio0 30 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie_switch>;
};
/* TODO: On-module Wi-Fi */
/* On-module Wi-Fi */
&pcieb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcieb>, <&pinctrl_wifi>;
phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>;
phy-names = "pcie-phy";
reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
&phyx2_lpcg {
clocks = <&hsio_refa_clk>, <&hsio_refb_clk>,
<&hsio_refa_clk>, <&hsio_per_clk>;
};
/* TODO: Apalis BKL1_PWM */
@ -806,8 +830,6 @@
<722534400>, <45158400>, <11289600>, <49152000>;
};
/* TODO: Apalis SATA1 */
/* Apalis SPDIF1 */
&spdif0 {
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,

View file

@ -22,6 +22,10 @@
phy-mode = "rgmii-rxid";
};
&hsio_refa_clk {
enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_HIGH>;
};
/* TODO: Apalis HDMI1 */
/* Apalis I2C2 (DDC) */
@ -188,12 +192,6 @@
"MXM3_291",
"MXM3_289",
"MXM3_287";
/* Enable pcie root / sata ref clock unconditionally */
pcie-sata-hog {
gpios = <27 GPIO_ACTIVE_HIGH>;
};
};
&lsio_gpio5 {