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ASoC: cs48l32: Add driver for Cirrus Logic CS48L32 audio DSP
Add a codec driver for the Cirrus Logic CS48L32 audio DSP. The CS48L32 is a low-power audio DSP with microphone inputs for "Always on Voice" (i.e. voice trigger) and voice command processing. It has a programmable Halo Core DSP and a variety of power-efficient fixed-function audio processors, with configurable digital mixing and routing. There are two I2S/TDM audio serial ports. Four analogue inputs are available through IN1. These feed into a 2-channel ADC through an analogue mux. There is an ALSA control for each IN1 ADC channel to select which analogue input to use. A dedicated digital mic (DMIC) PDM input is available on IN2. Two PDM outputs can feed DMIC inputs on another codec or a host DMIC/PDM input. An on-board regulator provides a power supply or bias voltage to attached microphones. Three switchable MICBIAS outputs are fed from this allowing only the microphone in use to be powered-up. There are DAPM widgets for these outputs: MICBIAS1A, MICBIAS1B and MICBIAS1C. The machine driver must create a DAPM route from the required MICBIAS1x widget to the INn input widgets to make the MICBIAS switch on when the audio input is powered-up. For example if the microphone feeding CS48L32 pin IN1LN_1 is powered from MICBIAS1A, the machine driver must create the path: (sink) IN1LN_1 <----- (source) MICBIAS1A Co-developed-by: Stuart Henderson <stuarth@opensource.cirrus.com> Signed-off-by: Stuart Henderson <stuarth@opensource.cirrus.com> Co-developed-by: Qi Zhou <qi.zhou@cirrus.com> Signed-off-by: Qi Zhou <qi.zhou@cirrus.com> Co-developed-by: Piotr Stankiewicz <piotrs@opensource.cirrus.com> Signed-off-by: Piotr Stankiewicz <piotrs@opensource.cirrus.com> Signed-off-by: Richard Fitzgerald <rf@opensource.cirrus.com> Link: https://patch.msgid.link/20250415115016.505777-3-rf@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Richard Fitzgerald
Mark Brown
parent
ac03495d73
commit
e2bcbf99d0
7 changed files with 5605 additions and 0 deletions
47
include/sound/cs48l32.h
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include/sound/cs48l32.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Register definitions for Cirrus Logic CS48L32
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*
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* Copyright (C) 2017-2018, 2020, 2022, 2025 Cirrus Logic, Inc. and
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* Cirrus Logic International Semiconductor Ltd.
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*/
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#ifndef CS48L32_H
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#define CS48L32_H
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/* pll_id for snd_soc_component_set_pll() */
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#define CS48L32_FLL1_REFCLK 1
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/* source for snd_soc_component_set_pll() */
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#define CS48L32_FLL_SRC_NONE -1
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#define CS48L32_FLL_SRC_MCLK1 0
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#define CS48L32_FLL_SRC_PDMCLK 5
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#define CS48L32_FLL_SRC_ASP1_BCLK 8
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#define CS48L32_FLL_SRC_ASP2_BCLK 9
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#define CS48L32_FLL_SRC_ASP1_FSYNC 12
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#define CS48L32_FLL_SRC_ASP2_FSYNC 13
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/* clk_id for snd_soc_component_set_sysclk() and snd_soc_dai_set_sysclk() */
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#define CS48L32_CLK_SYSCLK_1 1
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#define CS48L32_CLK_SYSCLK_2 2
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#define CS48L32_CLK_SYSCLK_3 3
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#define CS48L32_CLK_SYSCLK_4 4
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#define CS48L32_CLK_DSPCLK 7
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#define CS48L32_CLK_PDM_FLLCLK 13
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/* source for snd_soc_component_set_sysclk() */
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#define CS48L32_CLK_SRC_MCLK1 0x0
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#define CS48L32_CLK_SRC_FLL1 0x4
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#define CS48L32_CLK_SRC_ASP1_BCLK 0x8
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#define CS48L32_CLK_SRC_ASP2_BCLK 0x9
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struct cs48l32 {
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struct regmap *regmap;
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struct device *dev;
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struct gpio_desc *reset_gpio;
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struct clk *mclk1;
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struct regulator_bulk_data core_supplies[2];
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struct regulator *vdd_d;
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int irq;
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};
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#endif
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530
include/sound/cs48l32_registers.h
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include/sound/cs48l32_registers.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Register definitions for Cirrus Logic CS48L32
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*
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* Copyright (C) 2017-2018, 2020, 2022, 2025 Cirrus Logic, Inc. and
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* Cirrus Logic International Semiconductor Ltd.
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*/
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#ifndef CS48L32_REGISTERS_H
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#define CS48L32_REGISTERS_H
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/* Register Addresses. */
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#define CS48L32_DEVID 0x0
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#define CS48L32_REVID 0x4
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#define CS48L32_OTPID 0x10
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#define CS48L32_SFT_RESET 0x20
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#define CS48L32_CTRL_IF_DEBUG3 0xA8
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#define CS48L32_MCU_CTRL1 0x804
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#define CS48L32_GPIO1_CTRL1 0xc08
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#define CS48L32_GPIO3_CTRL1 0xc10
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#define CS48L32_GPIO7_CTRL1 0xc20
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#define CS48L32_GPIO16_CTRL1 0xc44
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#define CS48L32_OUTPUT_SYS_CLK 0x1020
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#define CS48L32_AUXPDM_CTRL 0x1044
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#define CS48L32_AUXPDM_CTRL2 0x105c
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#define CS48L32_CLOCK32K 0x1400
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#define CS48L32_SYSTEM_CLOCK1 0x1404
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#define CS48L32_SYSTEM_CLOCK2 0x1408
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#define CS48L32_SAMPLE_RATE1 0x1420
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#define CS48L32_SAMPLE_RATE2 0x1424
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#define CS48L32_SAMPLE_RATE3 0x1428
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#define CS48L32_SAMPLE_RATE4 0x142c
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#define CS48L32_DSP_CLOCK1 0x1510
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#define CS48L32_FLL1_CONTROL1 0x1c00
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#define CS48L32_FLL1_CONTROL5 0x1c10
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#define CS48L32_FLL1_CONTROL6 0x1c14
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#define CS48L32_FLL1_GPIO_CLOCK 0x1ca0
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#define CS48L32_CHARGE_PUMP1 0x2000
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#define CS48L32_LDO2_CTRL1 0x2408
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#define CS48L32_MICBIAS_CTRL1 0x2410
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#define CS48L32_MICBIAS_CTRL5 0x2418
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#define CS48L32_IRQ1_CTRL_AOD 0x2710
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#define CS48L32_AOD_PAD_CTRL 0x2718
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#define CS48L32_INPUT_CONTROL 0x4000
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#define CS48L32_INPUT_STATUS 0x4004
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#define CS48L32_INPUT_RATE_CONTROL 0x4008
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#define CS48L32_INPUT_CONTROL2 0x400c
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#define CS48L32_INPUT_CONTROL3 0x4014
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#define CS48L32_INPUT1_CONTROL1 0x4020
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#define CS48L32_IN1L_CONTROL1 0x4024
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#define CS48L32_IN1L_CONTROL2 0x4028
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#define CS48L32_IN1R_CONTROL1 0x4044
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#define CS48L32_IN1R_CONTROL2 0x4048
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#define CS48L32_INPUT2_CONTROL1 0x4060
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#define CS48L32_IN2L_CONTROL1 0x4064
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#define CS48L32_IN2L_CONTROL2 0x4068
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#define CS48L32_IN2R_CONTROL1 0x4084
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#define CS48L32_IN2R_CONTROL2 0x4088
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#define CS48L32_INPUT_HPF_CONTROL 0x4244
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#define CS48L32_INPUT_VOL_CONTROL 0x4248
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#define CS48L32_AUXPDM_CONTROL1 0x4300
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#define CS48L32_AUXPDM_CONTROL2 0x4304
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#define CS48L32_AUXPDM1_CONTROL1 0x4308
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#define CS48L32_AUXPDM2_CONTROL1 0x4310
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#define CS48L32_ADC1L_ANA_CONTROL1 0x4688
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#define CS48L32_ADC1R_ANA_CONTROL1 0x468c
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#define CS48L32_ASP1_ENABLES1 0x6000
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#define CS48L32_ASP1_CONTROL3 0x600C
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#define CS48L32_ASP1_DATA_CONTROL5 0x6040
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#define CS48L32_ASP2_ENABLES1 0x6080
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#define CS48L32_ASP2_CONTROL3 0x608C
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#define CS48L32_ASP2_DATA_CONTROL5 0x60c0
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#define CS48L32_ASP1TX1_INPUT1 0x8200
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#define CS48L32_ASP1TX2_INPUT1 0x8210
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#define CS48L32_ASP1TX3_INPUT1 0x8220
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#define CS48L32_ASP1TX4_INPUT1 0x8230
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#define CS48L32_ASP1TX5_INPUT1 0x8240
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#define CS48L32_ASP1TX6_INPUT1 0x8250
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#define CS48L32_ASP1TX7_INPUT1 0x8260
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#define CS48L32_ASP1TX8_INPUT1 0x8270
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#define CS48L32_ASP1TX8_INPUT4 0x827c
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#define CS48L32_ASP2TX1_INPUT1 0x8300
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#define CS48L32_ASP2TX2_INPUT1 0x8310
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#define CS48L32_ASP2TX3_INPUT1 0x8320
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#define CS48L32_ASP2TX4_INPUT1 0x8330
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#define CS48L32_ASP2TX4_INPUT4 0x833c
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#define CS48L32_ISRC1INT1_INPUT1 0x8980
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#define CS48L32_ISRC1INT2_INPUT1 0x8990
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#define CS48L32_ISRC1INT3_INPUT1 0x89a0
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#define CS48L32_ISRC1INT4_INPUT1 0x89b0
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#define CS48L32_ISRC1DEC1_INPUT1 0x89c0
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#define CS48L32_ISRC1DEC2_INPUT1 0x89d0
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#define CS48L32_ISRC1DEC3_INPUT1 0x89e0
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#define CS48L32_ISRC1DEC4_INPUT1 0x89f0
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#define CS48L32_ISRC2INT1_INPUT1 0x8a00
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#define CS48L32_ISRC2INT2_INPUT1 0x8a10
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#define CS48L32_ISRC2DEC1_INPUT1 0x8a40
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#define CS48L32_ISRC2DEC2_INPUT1 0x8a50
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#define CS48L32_ISRC3INT1_INPUT1 0x8a80
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#define CS48L32_ISRC3INT2_INPUT1 0x8a90
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#define CS48L32_ISRC3DEC1_INPUT1 0x8ac0
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#define CS48L32_ISRC3DEC2_INPUT1 0x8ad0
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#define CS48L32_EQ1_INPUT1 0x8b80
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#define CS48L32_EQ2_INPUT1 0x8b90
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#define CS48L32_EQ3_INPUT1 0x8ba0
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#define CS48L32_EQ4_INPUT1 0x8bb0
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#define CS48L32_EQ4_INPUT4 0x8bbc
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#define CS48L32_DRC1L_INPUT1 0x8c00
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#define CS48L32_DRC1R_INPUT1 0x8c10
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#define CS48L32_DRC1R_INPUT4 0x8c1c
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#define CS48L32_DRC2L_INPUT1 0x8c20
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#define CS48L32_DRC2R_INPUT1 0x8c30
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#define CS48L32_DRC2R_INPUT4 0x8c3c
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#define CS48L32_LHPF1_INPUT1 0x8c80
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#define CS48L32_LHPF1_INPUT4 0x8c8c
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#define CS48L32_LHPF2_INPUT1 0x8c90
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#define CS48L32_LHPF2_INPUT4 0x8c9c
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#define CS48L32_LHPF3_INPUT1 0x8ca0
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#define CS48L32_LHPF3_INPUT4 0x8cac
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#define CS48L32_LHPF4_INPUT1 0x8cb0
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#define CS48L32_LHPF4_INPUT4 0x8cbc
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#define CS48L32_DSP1RX1_INPUT1 0x9000
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#define CS48L32_DSP1RX2_INPUT1 0x9010
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#define CS48L32_DSP1RX3_INPUT1 0x9020
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#define CS48L32_DSP1RX4_INPUT1 0x9030
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#define CS48L32_DSP1RX5_INPUT1 0x9040
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#define CS48L32_DSP1RX6_INPUT1 0x9050
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#define CS48L32_DSP1RX7_INPUT1 0x9060
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#define CS48L32_DSP1RX8_INPUT1 0x9070
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#define CS48L32_DSP1RX8_INPUT4 0x907c
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#define CS48L32_ISRC1_CONTROL1 0xa400
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#define CS48L32_ISRC1_CONTROL2 0xa404
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#define CS48L32_ISRC2_CONTROL1 0xa510
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#define CS48L32_ISRC2_CONTROL2 0xa514
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#define CS48L32_ISRC3_CONTROL1 0xa620
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#define CS48L32_ISRC3_CONTROL2 0xa624
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#define CS48L32_FX_SAMPLE_RATE 0xa800
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#define CS48L32_EQ_CONTROL1 0xa808
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#define CS48L32_EQ_CONTROL2 0xa80c
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#define CS48L32_EQ1_GAIN1 0xa810
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#define CS48L32_EQ1_GAIN2 0xa814
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#define CS48L32_EQ1_BAND1_COEFF1 0xa818
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#define CS48L32_EQ1_BAND1_COEFF2 0xa81c
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#define CS48L32_EQ1_BAND1_PG 0xa820
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#define CS48L32_EQ1_BAND2_COEFF1 0xa824
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#define CS48L32_EQ1_BAND2_COEFF2 0xa828
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#define CS48L32_EQ1_BAND2_PG 0xa82c
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#define CS48L32_EQ1_BAND3_COEFF1 0xa830
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#define CS48L32_EQ1_BAND3_COEFF2 0xa834
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#define CS48L32_EQ1_BAND3_PG 0xa838
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#define CS48L32_EQ1_BAND4_COEFF1 0xa83c
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#define CS48L32_EQ1_BAND4_COEFF2 0xa840
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#define CS48L32_EQ1_BAND4_PG 0xa844
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#define CS48L32_EQ1_BAND5_COEFF1 0xa848
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#define CS48L32_EQ1_BAND5_PG 0xa850
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#define CS48L32_EQ2_GAIN1 0xa854
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#define CS48L32_EQ2_GAIN2 0xa858
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#define CS48L32_EQ2_BAND1_COEFF1 0xa85c
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#define CS48L32_EQ2_BAND1_COEFF2 0xa860
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#define CS48L32_EQ2_BAND1_PG 0xa864
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#define CS48L32_EQ2_BAND2_COEFF1 0xa868
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#define CS48L32_EQ2_BAND2_COEFF2 0xa86c
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#define CS48L32_EQ2_BAND2_PG 0xa870
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#define CS48L32_EQ2_BAND3_COEFF1 0xa874
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#define CS48L32_EQ2_BAND3_COEFF2 0xa878
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#define CS48L32_EQ2_BAND3_PG 0xa87c
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#define CS48L32_EQ2_BAND4_COEFF1 0xa880
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#define CS48L32_EQ2_BAND4_COEFF2 0xa884
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#define CS48L32_EQ2_BAND4_PG 0xa888
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#define CS48L32_EQ2_BAND5_COEFF1 0xa88c
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#define CS48L32_EQ2_BAND5_PG 0xa894
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#define CS48L32_EQ3_GAIN1 0xa898
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#define CS48L32_EQ3_GAIN2 0xa89c
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#define CS48L32_EQ3_BAND1_COEFF1 0xa8a0
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#define CS48L32_EQ3_BAND1_COEFF2 0xa8a4
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#define CS48L32_EQ3_BAND1_PG 0xa8a8
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#define CS48L32_EQ3_BAND2_COEFF1 0xa8ac
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#define CS48L32_EQ3_BAND2_COEFF2 0xa8b0
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#define CS48L32_EQ3_BAND2_PG 0xa8b4
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#define CS48L32_EQ3_BAND3_COEFF1 0xa8b8
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#define CS48L32_EQ3_BAND3_COEFF2 0xa8bc
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#define CS48L32_EQ3_BAND3_PG 0xa8c0
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#define CS48L32_EQ3_BAND4_COEFF1 0xa8c4
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#define CS48L32_EQ3_BAND4_COEFF2 0xa8c8
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#define CS48L32_EQ3_BAND4_PG 0xa8cc
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#define CS48L32_EQ3_BAND5_COEFF1 0xa8d0
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#define CS48L32_EQ3_BAND5_PG 0xa8d8
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#define CS48L32_EQ4_GAIN1 0xa8dc
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#define CS48L32_EQ4_GAIN2 0xa8e0
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#define CS48L32_EQ4_BAND1_COEFF1 0xa8e4
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#define CS48L32_EQ4_BAND1_COEFF2 0xa8e8
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#define CS48L32_EQ4_BAND1_PG 0xa8ec
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#define CS48L32_EQ4_BAND2_COEFF1 0xa8f0
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#define CS48L32_EQ4_BAND2_COEFF2 0xa8f4
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#define CS48L32_EQ4_BAND2_PG 0xa8f8
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#define CS48L32_EQ4_BAND3_COEFF1 0xa8fc
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#define CS48L32_EQ4_BAND3_COEFF2 0xa900
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#define CS48L32_EQ4_BAND3_PG 0xa904
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#define CS48L32_EQ4_BAND4_COEFF1 0xa908
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#define CS48L32_EQ4_BAND4_COEFF2 0xa90c
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#define CS48L32_EQ4_BAND4_PG 0xa910
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#define CS48L32_EQ4_BAND5_COEFF1 0xa914
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#define CS48L32_EQ4_BAND5_PG 0xa91c
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#define CS48L32_LHPF_CONTROL1 0xaa30
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#define CS48L32_LHPF_CONTROL2 0xaa34
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#define CS48L32_LHPF1_COEFF 0xaa38
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#define CS48L32_LHPF2_COEFF 0xaa3c
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#define CS48L32_LHPF3_COEFF 0xaa40
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#define CS48L32_LHPF4_COEFF 0xaa44
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#define CS48L32_DRC1_CONTROL1 0xab00
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#define CS48L32_DRC1_CONTROL4 0xab0c
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#define CS48L32_DRC2_CONTROL1 0xab14
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#define CS48L32_DRC2_CONTROL4 0xab20
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#define CS48L32_TONE_GENERATOR1 0xb000
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#define CS48L32_TONE_GENERATOR2 0xb004
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#define CS48L32_COMFORT_NOISE_GENERATOR 0xb400
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#define CS48L32_US_CONTROL 0xb800
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#define CS48L32_US1_CONTROL 0xb804
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#define CS48L32_US1_DET_CONTROL 0xb808
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#define CS48L32_US2_CONTROL 0xb814
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#define CS48L32_US2_DET_CONTROL 0xb818
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#define CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 0x1700c
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#define CS48L32_DSP1_XM_SRAM_IBUS_SETUP_1 0x17010
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#define CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24 0x1706c
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#define CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 0x17070
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#define CS48L32_DSP1_YM_SRAM_IBUS_SETUP_1 0x17074
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#define CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8 0x17090
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#define CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 0x17094
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#define CS48L32_DSP1_PM_SRAM_IBUS_SETUP_1 0x17098
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#define CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7 0x170b0
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#define CS48L32_IRQ1_STATUS 0x18004
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#define CS48L32_IRQ1_EINT_1 0x18010
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#define CS48L32_IRQ1_EINT_2 0x18014
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#define CS48L32_IRQ1_EINT_7 0x18028
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#define CS48L32_IRQ1_EINT_9 0x18030
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#define CS48L32_IRQ1_EINT_11 0x18038
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#define CS48L32_IRQ1_STS_1 0x18090
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#define CS48L32_IRQ1_STS_6 0x180a4
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#define CS48L32_IRQ1_STS_11 0x180b8
|
||||
#define CS48L32_IRQ1_MASK_1 0x18110
|
||||
#define CS48L32_IRQ1_MASK_2 0x18114
|
||||
#define CS48L32_IRQ1_MASK_7 0x18128
|
||||
#define CS48L32_IRQ1_MASK_9 0x18130
|
||||
#define CS48L32_IRQ1_MASK_11 0x18138
|
||||
#define CS48L32_DSP1_XMEM_PACKED_0 0x2000000
|
||||
#define CS48L32_DSP1_XMEM_PACKED_LAST 0x208fff0
|
||||
#define CS48L32_DSP1_SYS_INFO_ID 0x25e0000
|
||||
#define CS48L32_DSP1_AHBM_WINDOW_DEBUG_1 0x25e2044
|
||||
#define CS48L32_DSP1_XMEM_UNPACKED24_0 0x2800000
|
||||
#define CS48L32_DSP1_XMEM_UNPACKED24_LAST 0x28bfff4
|
||||
#define CS48L32_DSP1_CLOCK_FREQ 0x2b80000
|
||||
#define CS48L32_DSP1_SAMPLE_RATE_TX8 0x2b802b8
|
||||
#define CS48L32_DSP1_SCRATCH1 0x2b805c0
|
||||
#define CS48L32_DSP1_SCRATCH4 0x2b805d8
|
||||
#define CS48L32_DSP1_CCM_CORE_CONTROL 0x2bc1000
|
||||
#define CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1 0x2bc5a00
|
||||
#define CS48L32_DSP1_YMEM_PACKED_0 0x2c00000
|
||||
#define CS48L32_DSP1_YMEM_PACKED_LAST 0x2c2fff0
|
||||
#define CS48L32_DSP1_YMEM_UNPACKED24_0 0x3400000
|
||||
#define CS48L32_DSP1_YMEM_UNPACKED24_LAST 0x343fff4
|
||||
#define CS48L32_DSP1_PMEM_0 0x3800000
|
||||
#define CS48L32_DSP1_PMEM_LAST 0x3845fe8
|
||||
|
||||
/* (0x0) DEVID */
|
||||
#define CS48L32_DEVID_MASK 0x00ffffff
|
||||
#define CS48L32_DEVID_SHIFT 0
|
||||
|
||||
/* (0x4) REVID */
|
||||
#define CS48L32_AREVID_MASK 0x000000f0
|
||||
#define CS48L32_AREVID_SHIFT 4
|
||||
#define CS48L32_MTLREVID_MASK 0x0000000f
|
||||
#define CS48L32_MTLREVID_SHIFT 0
|
||||
|
||||
/* (0x10) OTPID */
|
||||
#define CS48L32_OTPID_MASK 0x0000000f
|
||||
|
||||
/* (0x0804) MCU_CTRL1 */
|
||||
#define CS48L32_MCU_STS_MASK 0x0000ff00
|
||||
#define CS48L32_MCU_STS_SHIFT 8
|
||||
|
||||
/* (0xc08) GPIO1_CTRL1 */
|
||||
#define CS48L32_GPIOX_CTRL1_FN_MASK 0x000003ff
|
||||
|
||||
/* (0x1020) OUTPUT_SYS_CLK */
|
||||
#define CS48L32_OPCLK_EN_SHIFT 15
|
||||
#define CS48L32_OPCLK_DIV_MASK 0x000000f8
|
||||
#define CS48L32_OPCLK_DIV_SHIFT 3
|
||||
#define CS48L32_OPCLK_SEL_MASK 0x00000007
|
||||
|
||||
/* (0x105c) AUXPDM_CTRL2 */
|
||||
#define CS48L32_AUXPDMDAT2_SRC_SHIFT 4
|
||||
#define CS48L32_AUXPDMDAT1_SRC_SHIFT 0
|
||||
|
||||
/* (0x1400) CLOCK32K */
|
||||
#define CS48L32_CLK_32K_EN_MASK 0x00000040
|
||||
#define CS48L32_CLK_32K_SRC_MASK 0x00000003
|
||||
|
||||
/* (0x1404) SYSTEM_CLOCK1 */
|
||||
#define CS48L32_SYSCLK_FRAC_MASK 0x00008000
|
||||
#define CS48L32_SYSCLK_FREQ_MASK 0x00000700
|
||||
#define CS48L32_SYSCLK_FREQ_SHIFT 8
|
||||
#define CS48L32_SYSCLK_EN_SHIFT 6
|
||||
#define CS48L32_SYSCLK_SRC_MASK 0x0000001f
|
||||
#define CS48L32_SYSCLK_SRC_SHIFT 0
|
||||
|
||||
/* (0x1408) SYSTEM_CLOCK2 */
|
||||
#define CS48L32_SYSCLK_FREQ_STS_MASK 0x00000700
|
||||
#define CS48L32_SYSCLK_FREQ_STS_SHIFT 8
|
||||
|
||||
/* (0x1420) SAMPLE_RATE1 */
|
||||
#define CS48L32_SAMPLE_RATE_1_MASK 0x0000001f
|
||||
#define CS48L32_SAMPLE_RATE_1_SHIFT 0
|
||||
|
||||
/* (0x1510) DSP_CLOCK1 */
|
||||
#define CS48L32_DSP_CLK_FREQ_MASK 0xffff0000
|
||||
#define CS48L32_DSP_CLK_FREQ_SHIFT 16
|
||||
|
||||
/* (0x1c00) FLL_CONTROL1 */
|
||||
#define CS48L32_FLL_CTRL_UPD_MASK 0x00000004
|
||||
#define CS48L32_FLL_HOLD_MASK 0x00000002
|
||||
#define CS48L32_FLL_EN_MASK 0x00000001
|
||||
|
||||
/* (0x1c04) FLL_CONTROL2 */
|
||||
#define CS48L32_FLL_LOCKDET_THR_MASK 0xf0000000
|
||||
#define CS48L32_FLL_LOCKDET_THR_SHIFT 28
|
||||
#define CS48L32_FLL_LOCKDET_MASK 0x08000000
|
||||
#define CS48L32_FLL_PHASEDET_MASK 0x00400000
|
||||
#define CS48L32_FLL_PHASEDET_SHIFT 22
|
||||
#define CS48L32_FLL_REFCLK_DIV_MASK 0x00030000
|
||||
#define CS48L32_FLL_REFCLK_DIV_SHIFT 16
|
||||
#define CS48L32_FLL_REFCLK_SRC_MASK 0x0000f000
|
||||
#define CS48L32_FLL_REFCLK_SRC_SHIFT 12
|
||||
#define CS48L32_FLL_N_MASK 0x000003ff
|
||||
#define CS48L32_FLL_N_SHIFT 0
|
||||
|
||||
/* (0x1c08) FLL_CONTROL3 */
|
||||
#define CS48L32_FLL_LAMBDA_MASK 0xffff0000
|
||||
#define CS48L32_FLL_LAMBDA_SHIFT 16
|
||||
#define CS48L32_FLL_THETA_MASK 0x0000ffff
|
||||
#define CS48L32_FLL_THETA_SHIFT 0
|
||||
|
||||
/* (0x1c0c) FLL_CONTROL4 */
|
||||
#define CS48L32_FLL_FD_GAIN_COARSE_SHIFT 16
|
||||
#define CS48L32_FLL_HP_MASK 0x00003000
|
||||
#define CS48L32_FLL_HP_SHIFT 12
|
||||
#define CS48L32_FLL_FB_DIV_MASK 0x000003ff
|
||||
#define CS48L32_FLL_FB_DIV_SHIFT 0
|
||||
|
||||
/* (0x1c10) FLL_CONTROL5 */
|
||||
#define CS48L32_FLL_FRC_INTEG_UPD_MASK 0x00008000
|
||||
|
||||
/* (0x2000) CHARGE_PUMP1 */
|
||||
#define CS48L32_CP2_BYPASS_SHIFT 1
|
||||
#define CS48L32_CP2_EN_SHIFT 0
|
||||
|
||||
/* (0x2408) LDO2_CTRL1 */
|
||||
#define CS48L32_LDO2_VSEL_MASK 0x000007e0
|
||||
#define CS48L32_LDO2_VSEL_SHIFT 5
|
||||
|
||||
/* (0x2410) MICBIAS_CTRL1 */
|
||||
#define CS48L32_MICB1_LVL_MASK 0x000001e0
|
||||
#define CS48L32_MICB1_LVL_SHIFT 5
|
||||
#define CS48L32_MICB1_EN_SHIFT 0
|
||||
|
||||
/* (0x2418) MICBIAS_CTRL5 */
|
||||
#define CS48L32_MICB1C_EN_SHIFT 8
|
||||
#define CS48L32_MICB1B_EN_SHIFT 4
|
||||
#define CS48L32_MICB1A_EN_SHIFT 0
|
||||
|
||||
/* (0x2710) IRQ1_CTRL_AOD */
|
||||
#define CS48L32_IRQ_POL_MASK 0x00000400
|
||||
|
||||
/* (0x4000) INPUT_CONTROL */
|
||||
#define CS48L32_IN2L_EN_SHIFT 3
|
||||
#define CS48L32_IN2R_EN_SHIFT 2
|
||||
#define CS48L32_IN1L_EN_SHIFT 1
|
||||
#define CS48L32_IN1R_EN_SHIFT 0
|
||||
|
||||
/* (0x400c) INPUT_CONTROL2 */
|
||||
#define CS48L32_PDM_FLLCLK_SRC_MASK 0x0000000f
|
||||
#define CS48L32_PDM_FLLCLK_SRC_SHIFT 0
|
||||
|
||||
/* (0x4014) INPUT_CONTROL3 */
|
||||
#define CS48L32_IN_VU 0x20000000
|
||||
#define CS48L32_IN_VU_MASK 0x20000000
|
||||
#define CS48L32_IN_VU_SHIFT 29
|
||||
#define CS48L32_IN_VU_WIDTH 1
|
||||
|
||||
/* (0x4020) INPUT1_CONTROL1 */
|
||||
#define CS48L32_IN1_OSR_SHIFT 16
|
||||
#define CS48L32_IN1_PDM_SUP_MASK 0x00000300
|
||||
#define CS48L32_IN1_PDM_SUP_SHIFT 8
|
||||
#define CS48L32_IN1_MODE_SHIFT 0
|
||||
|
||||
/*
|
||||
* (0x4024) IN1L_CONTROL1
|
||||
* (0x4044) IN1R_CONTROL1
|
||||
*/
|
||||
#define CS48L32_INx_SRC_MASK 0x30000000
|
||||
#define CS48L32_INx_SRC_SHIFT 28
|
||||
#define CS48L32_INx_RATE_MASK 0x0000f800
|
||||
#define CS48L32_INx_RATE_SHIFT 11
|
||||
#define CS48L32_INx_HPF_SHIFT 2
|
||||
#define CS48L32_INx_LP_MODE_SHIFT 0
|
||||
|
||||
/*
|
||||
* (0x4028) IN1L_CONTROL2
|
||||
* (0x4048) IN1R_CONTROL2
|
||||
*/
|
||||
#define CS48L32_INx_MUTE_MASK 0x10000000
|
||||
#define CS48L32_INx_VOL_SHIFT 16
|
||||
#define CS48L32_INx_PGA_VOL_SHIFT 1
|
||||
|
||||
/* (0x4244) INPUT_HPF_CONTROL */
|
||||
#define CS48L32_IN_HPF_CUT_SHIFT 0
|
||||
|
||||
/* (0x4248) INPUT_VOL_CONTROL */
|
||||
#define CS48L32_IN_VD_RAMP_SHIFT 4
|
||||
#define CS48L32_IN_VI_RAMP_SHIFT 0
|
||||
|
||||
/* (0x4308) AUXPDM1_CONTROL1 */
|
||||
#define CS48L32_AUXPDM1_FREQ_SHIFT 16
|
||||
#define CS48L32_AUXPDM1_SRC_MASK 0x00000f00
|
||||
#define CS48L32_AUXPDM1_SRC_SHIFT 8
|
||||
|
||||
/* (0x4688) ADC1L_ANA_CONTROL1 */
|
||||
/* (0x468c) ADC1R_ANA_CONTROL1 */
|
||||
#define CS48L32_ADC1x_INT_ENA_FRC_MASK 0x00000002
|
||||
|
||||
/* (0x6004) ASPn_CONTROL1 */
|
||||
#define CS48L32_ASP_RATE_MASK 0x00001f00
|
||||
#define CS48L32_ASP_RATE_SHIFT 8
|
||||
#define CS48L32_ASP_BCLK_FREQ_MASK 0x0000003f
|
||||
|
||||
/* (0x6008) ASPn_CONTROL2 */
|
||||
#define CS48L32_ASP_RX_WIDTH_MASK 0xff000000
|
||||
#define CS48L32_ASP_RX_WIDTH_SHIFT 24
|
||||
#define CS48L32_ASP_TX_WIDTH_MASK 0x00ff0000
|
||||
#define CS48L32_ASP_TX_WIDTH_SHIFT 16
|
||||
#define CS48L32_ASP_FMT_MASK 0x00000700
|
||||
#define CS48L32_ASP_FMT_SHIFT 8
|
||||
#define CS48L32_ASP_BCLK_INV_MASK 0x00000040
|
||||
#define CS48L32_ASP_BCLK_MSTR_MASK 0x00000010
|
||||
#define CS48L32_ASP_FSYNC_INV_MASK 0x00000004
|
||||
#define CS48L32_ASP_FSYNC_MSTR_MASK 0x00000001
|
||||
|
||||
/* (0x6010) ASPn_CONTROL3 */
|
||||
#define CS48L32_ASP_DOUT_HIZ_MASK 0x00000003
|
||||
|
||||
/* (0x6030) ASPn_DATA_CONTROL1 */
|
||||
#define CS48L32_ASP_TX_WL_MASK 0x0000003f
|
||||
|
||||
/* (0x6040) ASPn_DATA_CONTROL5 */
|
||||
#define CS48L32_ASP_RX_WL_MASK 0x0000003f
|
||||
|
||||
/* (0x82xx - 0x90xx) *_INPUT[1-4] */
|
||||
#define CS48L32_MIXER_VOL_MASK 0x00FE0000
|
||||
#define CS48L32_MIXER_VOL_SHIFT 17
|
||||
#define CS48L32_MIXER_VOL_WIDTH 7
|
||||
#define CS48L32_MIXER_SRC_MASK 0x000001ff
|
||||
#define CS48L32_MIXER_SRC_SHIFT 0
|
||||
#define CS48L32_MIXER_SRC_WIDTH 9
|
||||
|
||||
/* (0xa400) ISRC1_CONTROL1 */
|
||||
#define CS48L32_ISRC1_FSL_MASK 0xf8000000
|
||||
#define CS48L32_ISRC1_FSL_SHIFT 27
|
||||
#define CS48L32_ISRC1_FSH_MASK 0x0000f800
|
||||
#define CS48L32_ISRC1_FSH_SHIFT 11
|
||||
|
||||
/* (0xa404) ISRC1_CONTROL2 */
|
||||
#define CS48L32_ISRC1_INT4_EN_SHIFT 11
|
||||
#define CS48L32_ISRC1_INT3_EN_SHIFT 10
|
||||
#define CS48L32_ISRC1_INT2_EN_SHIFT 9
|
||||
#define CS48L32_ISRC1_INT1_EN_SHIFT 8
|
||||
#define CS48L32_ISRC1_DEC4_EN_SHIFT 3
|
||||
#define CS48L32_ISRC1_DEC3_EN_SHIFT 2
|
||||
#define CS48L32_ISRC1_DEC2_EN_SHIFT 1
|
||||
#define CS48L32_ISRC1_DEC1_EN_SHIFT 0
|
||||
|
||||
/* (0xa800) FX_SAMPLE_RATE */
|
||||
#define CS48L32_FX_RATE_MASK 0x0000f800
|
||||
#define CS48L32_FX_RATE_SHIFT 11
|
||||
|
||||
/* (0xab00) DRC1_CONTROL1 */
|
||||
#define CS48L32_DRC1L_EN_SHIFT 1
|
||||
#define CS48L32_DRC1R_EN_SHIFT 0
|
||||
|
||||
/* (0xb400) Comfort_Noise_Generator */
|
||||
#define CS48L32_NOISE_GEN_RATE_MASK 0x0000f800
|
||||
#define CS48L32_NOISE_GEN_RATE_SHIFT 11
|
||||
#define CS48L32_NOISE_GEN_EN_SHIFT 5
|
||||
#define CS48L32_NOISE_GEN_GAIN_SHIFT 0
|
||||
|
||||
/* (0xb800) US_CONTROL */
|
||||
#define CS48L32_US1_DET_EN_SHIFT 8
|
||||
|
||||
/* (0xb804) US1_CONTROL */
|
||||
#define CS48L32_US1_RATE_MASK 0xf8000000
|
||||
#define CS48L32_US1_RATE_SHIFT 27
|
||||
#define CS48L32_US1_GAIN_SHIFT 12
|
||||
#define CS48L32_US1_SRC_MASK 0x00000f00
|
||||
#define CS48L32_US1_SRC_SHIFT 8
|
||||
#define CS48L32_US1_FREQ_MASK 0x00000070
|
||||
#define CS48L32_US1_FREQ_SHIFT 4
|
||||
|
||||
/* (0xb808) US1_DET_CONTROL */
|
||||
#define CS48L32_US1_DET_DCY_SHIFT 28
|
||||
#define CS48L32_US1_DET_HOLD_SHIFT 24
|
||||
#define CS48L32_US1_DET_NUM_SHIFT 20
|
||||
#define CS48L32_US1_DET_THR_SHIFT 16
|
||||
#define CS48L32_US1_DET_LPF_CUT_SHIFT 5
|
||||
#define CS48L32_US1_DET_LPF_SHIFT 4
|
||||
|
||||
/* (0x18004) IRQ1_STATUS */
|
||||
#define CS48L32_IRQ1_STS_MASK 0x00000001
|
||||
|
||||
/* (0x18014) IRQ1_EINT_2 */
|
||||
#define CS48L32_BOOT_DONE_EINT1_MASK 0x00000008
|
||||
|
||||
/* (0x18028) IRQ1_EINT_7 */
|
||||
#define CS48L32_DSP1_MPU_ERR_EINT1_MASK 0x00200000
|
||||
#define CS48L32_DSP1_WDT_EXPIRE_EINT1_MASK 0x00100000
|
||||
|
||||
/* (0x18030) IRQ1_EINT_9 */
|
||||
#define CS48L32_DSP1_IRQ0_EINT1_MASK 0x00000001
|
||||
|
||||
/* (0x180a4) IRQ1_STS_6 */
|
||||
#define CS48L32_FLL1_LOCK_STS1_MASK 0x00000001
|
||||
|
||||
#endif
|
||||
|
|
@ -103,6 +103,7 @@ config SND_SOC_ALL_CODECS
|
|||
imply SND_SOC_CS47L85
|
||||
imply SND_SOC_CS47L90
|
||||
imply SND_SOC_CS47L92
|
||||
imply SND_SOC_CS48L32
|
||||
imply SND_SOC_CS53L30
|
||||
imply SND_SOC_CS530X_I2C
|
||||
imply SND_SOC_CX20442
|
||||
|
|
@ -403,6 +404,7 @@ config SND_SOC_WM_ADSP
|
|||
default y if SND_SOC_CS35L45_SPI=y
|
||||
default y if SND_SOC_CS35L45_I2C=y
|
||||
default y if SND_SOC_CS35L56=y
|
||||
default y if SND_SOC_CS48L32=y
|
||||
default m if SND_SOC_MADERA=m
|
||||
default m if SND_SOC_CS47L24=m
|
||||
default m if SND_SOC_WM5102=m
|
||||
|
|
@ -413,6 +415,7 @@ config SND_SOC_WM_ADSP
|
|||
default m if SND_SOC_CS35L45_SPI=m
|
||||
default m if SND_SOC_CS35L45_I2C=m
|
||||
default m if SND_SOC_CS35L56=m
|
||||
default m if SND_SOC_CS48L32=m
|
||||
|
||||
config SND_SOC_AB8500_CODEC
|
||||
tristate
|
||||
|
|
@ -1049,6 +1052,13 @@ config SND_SOC_CS47L92
|
|||
tristate
|
||||
depends on MFD_CS47L92
|
||||
|
||||
config SND_SOC_CS48L32
|
||||
tristate "Cirrus Logic CS48L32 audio DSP"
|
||||
depends on SPI_MASTER
|
||||
select REGMAP_SPI
|
||||
help
|
||||
Build the codec driver for the Cirrus Logic CS48L32 audio DSP.
|
||||
|
||||
# Cirrus Logic Quad-Channel ADC
|
||||
config SND_SOC_CS53L30
|
||||
tristate "Cirrus Logic CS53L30 CODEC"
|
||||
|
|
|
|||
|
|
@ -111,6 +111,7 @@ snd-soc-cs47l35-y := cs47l35.o
|
|||
snd-soc-cs47l85-y := cs47l85.o
|
||||
snd-soc-cs47l90-y := cs47l90.o
|
||||
snd-soc-cs47l92-y := cs47l92.o
|
||||
snd-soc-cs48l32-y := cs48l32.o cs48l32-tables.o
|
||||
snd-soc-cs53l30-y := cs53l30.o
|
||||
snd-soc-cs530x-y := cs530x.o
|
||||
snd-soc-cs530x-i2c-y := cs530x-i2c.o
|
||||
|
|
@ -529,6 +530,7 @@ obj-$(CONFIG_SND_SOC_CS47L35) += snd-soc-cs47l35.o
|
|||
obj-$(CONFIG_SND_SOC_CS47L85) += snd-soc-cs47l85.o
|
||||
obj-$(CONFIG_SND_SOC_CS47L90) += snd-soc-cs47l90.o
|
||||
obj-$(CONFIG_SND_SOC_CS47L92) += snd-soc-cs47l92.o
|
||||
obj-$(CONFIG_SND_SOC_CS48L32) += snd-soc-cs48l32.o
|
||||
obj-$(CONFIG_SND_SOC_CS53L30) += snd-soc-cs53l30.o
|
||||
obj-$(CONFIG_SND_SOC_CS530X) += snd-soc-cs530x.o
|
||||
obj-$(CONFIG_SND_SOC_CS530X_I2C) += snd-soc-cs530x-i2c.o
|
||||
|
|
|
|||
540
sound/soc/codecs/cs48l32-tables.c
Normal file
540
sound/soc/codecs/cs48l32-tables.c
Normal file
|
|
@ -0,0 +1,540 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// Regmap tables and other data for Cirrus Logic CS48L32 audio DSP.
|
||||
//
|
||||
// Copyright (C) 2018, 2020, 2022, 2025 Cirrus Logic, Inc. and
|
||||
// Cirrus Logic International Semiconductor Ltd.
|
||||
|
||||
#include <linux/array_size.h>
|
||||
#include <linux/build_bug.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/linear_range.h>
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/regulator/consumer.h>
|
||||
#include <sound/cs48l32.h>
|
||||
#include <sound/cs48l32_registers.h>
|
||||
|
||||
#include "cs48l32.h"
|
||||
|
||||
static const struct reg_sequence cs48l32_reva_patch[] = {
|
||||
{ 0x00001044, 0x0005000f },
|
||||
{ 0x00001c34, 0x000037e8 },
|
||||
{ 0x000046d8, 0x00000fe0 },
|
||||
};
|
||||
|
||||
int cs48l32_apply_patch(struct cs48l32 *cs48l32)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = regmap_register_patch(cs48l32->regmap, cs48l32_reva_patch,
|
||||
ARRAY_SIZE(cs48l32_reva_patch));
|
||||
if (ret < 0)
|
||||
return dev_err_probe(cs48l32->dev, ret, "Failed to apply patch\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct reg_default cs48l32_reg_default[] = {
|
||||
{ 0x00000c08, 0xe1000001 }, /* GPIO1_CTRL1 */
|
||||
{ 0x00000c0c, 0xe1000001 }, /* GPIO2_CTRL1 */
|
||||
{ 0x00000c10, 0xe1000001 }, /* GPIO3_CTRL1 */
|
||||
{ 0x00000c14, 0xe1000001 }, /* GPIO4_CTRL1 */
|
||||
{ 0x00000c18, 0xe1000001 }, /* GPIO5_CTRL1 */
|
||||
{ 0x00000c1c, 0xe1000001 }, /* GPIO6_CTRL1 */
|
||||
{ 0x00000c20, 0xe1000001 }, /* GPIO7_CTRL1 */
|
||||
{ 0x00000c24, 0xe1000001 }, /* GPIO8_CTRL1 */
|
||||
{ 0x00000c28, 0xe1000001 }, /* GPIO9_CTRL1 */
|
||||
{ 0x00000c2c, 0xe1000001 }, /* GPIO10_CTRL1 */
|
||||
{ 0x00000c30, 0xe1000001 }, /* GPIO11_CTRL1 */
|
||||
{ 0x00000c34, 0xe1000001 }, /* GPIO12_CTRL1 */
|
||||
{ 0x00000c38, 0xe1000001 }, /* GPIO13_CTRL1 */
|
||||
{ 0x00000c3c, 0xe1000001 }, /* GPIO14_CTRL1 */
|
||||
{ 0x00000c40, 0xe1000001 }, /* GPIO15_CTRL1 */
|
||||
{ 0x00000c44, 0xe1000001 }, /* GPIO16_CTRL1 */
|
||||
{ 0x00001020, 0x00000000 }, /* OUTPUT_SYS_CLK */
|
||||
{ 0x00001044, 0x0005000f }, /* AUXPDM_CTRL */
|
||||
{ 0x0000105c, 0x00000000 }, /* AUXPDM_CTRL2 */
|
||||
{ 0x00001400, 0x00000002 }, /* CLOCK32K */
|
||||
{ 0x00001404, 0x00000404 }, /* SYSTEM_CLOCK1 */
|
||||
{ 0x00001420, 0x00000003 }, /* SAMPLE_RATE1 */
|
||||
{ 0x00001424, 0x00000003 }, /* SAMPLE_RATE2 */
|
||||
{ 0x00001428, 0x00000003 }, /* SAMPLE_RATE3 */
|
||||
{ 0x0000142c, 0x00000003 }, /* SAMPLE_RATE4 */
|
||||
{ 0x00001c00, 0x00000002 }, /* FLL1_CONTROL1 */
|
||||
{ 0x00001c04, 0x88203004 }, /* FLL1_CONTROL2 */
|
||||
{ 0x00001c08, 0x00000000 }, /* FLL1_CONTROL3 */
|
||||
{ 0x00001c0c, 0x21f05001 }, /* FLL1_CONTROL4 */
|
||||
{ 0x00001ca0, 0x00000c04 }, /* FLL1_GPIO_CLOCK */
|
||||
{ 0x00002000, 0x00000006 }, /* CHARGE_PUMP1 */
|
||||
{ 0x00002408, 0x000003e4 }, /* LDO2_CTRL1 */
|
||||
{ 0x00002410, 0x000000e6 }, /* MICBIAS_CTRL1 */
|
||||
{ 0x00002418, 0x00000222 }, /* MICBIAS_CTRL5 */
|
||||
{ 0x00002710, 0x00004600 }, /* IRQ1_CTRL_AOD */
|
||||
{ 0x00004000, 0x00000000 }, /* INPUT_CONTROL */
|
||||
{ 0x00004008, 0x00000400 }, /* INPUT_RATE_CONTROL */
|
||||
{ 0x0000400c, 0x00000000 }, /* INPUT_CONTROL2 */
|
||||
{ 0x00004020, 0x00050020 }, /* INPUT1_CONTROL1 */
|
||||
{ 0x00004024, 0x00000000 }, /* IN1L_CONTROL1 */
|
||||
{ 0x00004028, 0x10800080 }, /* IN1L_CONTROL2 */
|
||||
{ 0x00004044, 0x00000000 }, /* IN1R_CONTROL1 */
|
||||
{ 0x00004048, 0x10800080 }, /* IN1R_CONTROL2 */
|
||||
{ 0x00004060, 0x00050020 }, /* INPUT2_CONTROL1 */
|
||||
{ 0x00004064, 0x00000000 }, /* IN2L_CONTROL1 */
|
||||
{ 0x00004068, 0x10800000 }, /* IN2L_CONTROL2 */
|
||||
{ 0x00004084, 0x00000000 }, /* IN2R_CONTROL1 */
|
||||
{ 0x00004088, 0x10800000 }, /* IN2R_CONTROL2 */
|
||||
{ 0x00004244, 0x00000002 }, /* INPUT_HPF_CONTROL */
|
||||
{ 0x00004248, 0x00000022 }, /* INPUT_VOL_CONTROL */
|
||||
{ 0x00004300, 0x00000000 }, /* AUXPDM_CONTROL1 */
|
||||
{ 0x00004304, 0x00000000 }, /* AUXPDM_CONTROL2 */
|
||||
{ 0x00004308, 0x00010008 }, /* AUXPDM1_CONTROL1 */
|
||||
{ 0x00004310, 0x00010008 }, /* AUXPDM2_CONTROL1 */
|
||||
{ 0x00004688, 0x00000000 }, /* ADC1L_ANA_CONTROL1 */
|
||||
{ 0x0000468c, 0x00000000 }, /* ADC1R_ANA_CONTROL1 */
|
||||
{ 0x00006000, 0x00000000 }, /* ASP1_ENABLES1 */
|
||||
{ 0x00006004, 0x00000028 }, /* ASP1_CONTROL1 */
|
||||
{ 0x00006008, 0x18180200 }, /* ASP1_CONTROL2 */
|
||||
{ 0x0000600c, 0x00000002 }, /* ASP1_CONTROL3 */
|
||||
{ 0x00006010, 0x03020100 }, /* ASP1_FRAME_CONTROL1 */
|
||||
{ 0x00006014, 0x07060504 }, /* ASP1_FRAME_CONTROL2 */
|
||||
{ 0x00006020, 0x03020100 }, /* ASP1_FRAME_CONTROL5 */
|
||||
{ 0x00006024, 0x07060504 }, /* ASP1_FRAME_CONTROL6 */
|
||||
{ 0x00006030, 0x00000020 }, /* ASP1_DATA_CONTROL1 */
|
||||
{ 0x00006040, 0x00000020 }, /* ASP1_DATA_CONTROL5 */
|
||||
{ 0x00006080, 0x00000000 }, /* ASP2_ENABLES1 */
|
||||
{ 0x00006084, 0x00000028 }, /* ASP2_CONTROL1 */
|
||||
{ 0x00006088, 0x18180200 }, /* ASP2_CONTROL2 */
|
||||
{ 0x0000608c, 0x00000002 }, /* ASP2_CONTROL3 */
|
||||
{ 0x00006090, 0x03020100 }, /* ASP2_FRAME_CONTROL1 */
|
||||
{ 0x000060a0, 0x03020100 }, /* ASP2_FRAME_CONTROL5 */
|
||||
{ 0x000060b0, 0x00000020 }, /* ASP2_DATA_CONTROL1 */
|
||||
{ 0x000060c0, 0x00000020 }, /* ASP2_DATA_CONTROL5 */
|
||||
{ 0x00008200, 0x00800000 }, /* ASP1TX1_INPUT1 */
|
||||
{ 0x00008204, 0x00800000 }, /* ASP1TX1_INPUT2 */
|
||||
{ 0x00008208, 0x00800000 }, /* ASP1TX1_INPUT3 */
|
||||
{ 0x0000820c, 0x00800000 }, /* ASP1TX1_INPUT4 */
|
||||
{ 0x00008210, 0x00800000 }, /* ASP1TX2_INPUT1 */
|
||||
{ 0x00008214, 0x00800000 }, /* ASP1TX2_INPUT2 */
|
||||
{ 0x00008218, 0x00800000 }, /* ASP1TX2_INPUT3 */
|
||||
{ 0x0000821c, 0x00800000 }, /* ASP1TX2_INPUT4 */
|
||||
{ 0x00008220, 0x00800000 }, /* ASP1TX3_INPUT1 */
|
||||
{ 0x00008224, 0x00800000 }, /* ASP1TX3_INPUT2 */
|
||||
{ 0x00008228, 0x00800000 }, /* ASP1TX3_INPUT3 */
|
||||
{ 0x0000822c, 0x00800000 }, /* ASP1TX3_INPUT4 */
|
||||
{ 0x00008230, 0x00800000 }, /* ASP1TX4_INPUT1 */
|
||||
{ 0x00008234, 0x00800000 }, /* ASP1TX4_INPUT2 */
|
||||
{ 0x00008238, 0x00800000 }, /* ASP1TX4_INPUT3 */
|
||||
{ 0x0000823c, 0x00800000 }, /* ASP1TX4_INPUT4 */
|
||||
{ 0x00008240, 0x00800000 }, /* ASP1TX5_INPUT1 */
|
||||
{ 0x00008244, 0x00800000 }, /* ASP1TX5_INPUT2 */
|
||||
{ 0x00008248, 0x00800000 }, /* ASP1TX5_INPUT3 */
|
||||
{ 0x0000824c, 0x00800000 }, /* ASP1TX5_INPUT4 */
|
||||
{ 0x00008250, 0x00800000 }, /* ASP1TX6_INPUT1 */
|
||||
{ 0x00008254, 0x00800000 }, /* ASP1TX6_INPUT2 */
|
||||
{ 0x00008258, 0x00800000 }, /* ASP1TX6_INPUT3 */
|
||||
{ 0x0000825c, 0x00800000 }, /* ASP1TX6_INPUT4 */
|
||||
{ 0x00008260, 0x00800000 }, /* ASP1TX7_INPUT1 */
|
||||
{ 0x00008264, 0x00800000 }, /* ASP1TX7_INPUT2 */
|
||||
{ 0x00008268, 0x00800000 }, /* ASP1TX7_INPUT3 */
|
||||
{ 0x0000826c, 0x00800000 }, /* ASP1TX7_INPUT4 */
|
||||
{ 0x00008270, 0x00800000 }, /* ASP1TX8_INPUT1 */
|
||||
{ 0x00008274, 0x00800000 }, /* ASP1TX8_INPUT2 */
|
||||
{ 0x00008278, 0x00800000 }, /* ASP1TX8_INPUT3 */
|
||||
{ 0x0000827c, 0x00800000 }, /* ASP1TX8_INPUT4 */
|
||||
{ 0x00008300, 0x00800000 }, /* ASP2TX1_INPUT1 */
|
||||
{ 0x00008304, 0x00800000 }, /* ASP2TX1_INPUT2 */
|
||||
{ 0x00008308, 0x00800000 }, /* ASP2TX1_INPUT3 */
|
||||
{ 0x0000830c, 0x00800000 }, /* ASP2TX1_INPUT4 */
|
||||
{ 0x00008310, 0x00800000 }, /* ASP2TX2_INPUT1 */
|
||||
{ 0x00008314, 0x00800000 }, /* ASP2TX2_INPUT2 */
|
||||
{ 0x00008318, 0x00800000 }, /* ASP2TX2_INPUT3 */
|
||||
{ 0x0000831c, 0x00800000 }, /* ASP2TX2_INPUT4 */
|
||||
{ 0x00008320, 0x00800000 }, /* ASP2TX3_INPUT1 */
|
||||
{ 0x00008324, 0x00800000 }, /* ASP2TX3_INPUT2 */
|
||||
{ 0x00008328, 0x00800000 }, /* ASP2TX3_INPUT3 */
|
||||
{ 0x0000832c, 0x00800000 }, /* ASP2TX3_INPUT4 */
|
||||
{ 0x00008330, 0x00800000 }, /* ASP2TX4_INPUT1 */
|
||||
{ 0x00008334, 0x00800000 }, /* ASP2TX4_INPUT2 */
|
||||
{ 0x00008338, 0x00800000 }, /* ASP2TX4_INPUT3 */
|
||||
{ 0x0000833c, 0x00800000 }, /* ASP2TX4_INPUT4 */
|
||||
{ 0x00008980, 0x00000000 }, /* ISRC1INT1_INPUT1 */
|
||||
{ 0x00008990, 0x00000000 }, /* ISRC1INT2_INPUT1 */
|
||||
{ 0x000089a0, 0x00000000 }, /* ISRC1INT3_INPUT1 */
|
||||
{ 0x000089b0, 0x00000000 }, /* ISRC1INT4_INPUT1 */
|
||||
{ 0x000089c0, 0x00000000 }, /* ISRC1DEC1_INPUT1 */
|
||||
{ 0x000089d0, 0x00000000 }, /* ISRC1DEC2_INPUT1 */
|
||||
{ 0x000089e0, 0x00000000 }, /* ISRC1DEC3_INPUT1 */
|
||||
{ 0x000089f0, 0x00000000 }, /* ISRC1DEC4_INPUT1 */
|
||||
{ 0x00008a00, 0x00000000 }, /* ISRC2INT1_INPUT1 */
|
||||
{ 0x00008a10, 0x00000000 }, /* ISRC2INT2_INPUT1 */
|
||||
{ 0x00008a40, 0x00000000 }, /* ISRC2DEC1_INPUT1 */
|
||||
{ 0x00008a50, 0x00000000 }, /* ISRC2DEC2_INPUT1 */
|
||||
{ 0x00008a80, 0x00000000 }, /* ISRC3INT1_INPUT1 */
|
||||
{ 0x00008a90, 0x00000000 }, /* ISRC3INT2_INPUT1 */
|
||||
{ 0x00008ac0, 0x00000000 }, /* ISRC3DEC1_INPUT1 */
|
||||
{ 0x00008ad0, 0x00000000 }, /* ISRC3DEC2_INPUT1 */
|
||||
{ 0x00008b80, 0x00800000 }, /* EQ1_INPUT1 */
|
||||
{ 0x00008b84, 0x00800000 }, /* EQ1_INPUT2 */
|
||||
{ 0x00008b88, 0x00800000 }, /* EQ1_INPUT3 */
|
||||
{ 0x00008b8c, 0x00800000 }, /* EQ1_INPUT4 */
|
||||
{ 0x00008b90, 0x00800000 }, /* EQ2_INPUT1 */
|
||||
{ 0x00008b94, 0x00800000 }, /* EQ2_INPUT2 */
|
||||
{ 0x00008b98, 0x00800000 }, /* EQ2_INPUT3 */
|
||||
{ 0x00008b9c, 0x00800000 }, /* EQ2_INPUT4 */
|
||||
{ 0x00008ba0, 0x00800000 }, /* EQ3_INPUT1 */
|
||||
{ 0x00008ba4, 0x00800000 }, /* EQ3_INPUT2 */
|
||||
{ 0x00008ba8, 0x00800000 }, /* EQ3_INPUT3 */
|
||||
{ 0x00008bac, 0x00800000 }, /* EQ3_INPUT4 */
|
||||
{ 0x00008bb0, 0x00800000 }, /* EQ4_INPUT1 */
|
||||
{ 0x00008bb4, 0x00800000 }, /* EQ4_INPUT2 */
|
||||
{ 0x00008bb8, 0x00800000 }, /* EQ4_INPUT3 */
|
||||
{ 0x00008bbc, 0x00800000 }, /* EQ4_INPUT4 */
|
||||
{ 0x00008c00, 0x00800000 }, /* DRC1L_INPUT1 */
|
||||
{ 0x00008c04, 0x00800000 }, /* DRC1L_INPUT2 */
|
||||
{ 0x00008c08, 0x00800000 }, /* DRC1L_INPUT3 */
|
||||
{ 0x00008c0c, 0x00800000 }, /* DRC1L_INPUT4 */
|
||||
{ 0x00008c10, 0x00800000 }, /* DRC1R_INPUT1 */
|
||||
{ 0x00008c14, 0x00800000 }, /* DRC1R_INPUT2 */
|
||||
{ 0x00008c18, 0x00800000 }, /* DRC1R_INPUT3 */
|
||||
{ 0x00008c1c, 0x00800000 }, /* DRC1R_INPUT4 */
|
||||
{ 0x00008c20, 0x00800000 }, /* DRC2L_INPUT1 */
|
||||
{ 0x00008c24, 0x00800000 }, /* DRC2L_INPUT2 */
|
||||
{ 0x00008c28, 0x00800000 }, /* DRC2L_INPUT3 */
|
||||
{ 0x00008c2c, 0x00800000 }, /* DRC2L_INPUT4 */
|
||||
{ 0x00008c30, 0x00800000 }, /* DRC2R_INPUT1 */
|
||||
{ 0x00008c34, 0x00800000 }, /* DRC2R_INPUT2 */
|
||||
{ 0x00008c38, 0x00800000 }, /* DRC2R_INPUT3 */
|
||||
{ 0x00008c3c, 0x00800000 }, /* DRC2R_INPUT4 */
|
||||
{ 0x00008c80, 0x00800000 }, /* LHPF1_INPUT1 */
|
||||
{ 0x00008c84, 0x00800000 }, /* LHPF1_INPUT2 */
|
||||
{ 0x00008c88, 0x00800000 }, /* LHPF1_INPUT3 */
|
||||
{ 0x00008c8c, 0x00800000 }, /* LHPF1_INPUT4 */
|
||||
{ 0x00008c90, 0x00800000 }, /* LHPF2_INPUT1 */
|
||||
{ 0x00008c94, 0x00800000 }, /* LHPF2_INPUT2 */
|
||||
{ 0x00008c98, 0x00800000 }, /* LHPF2_INPUT3 */
|
||||
{ 0x00008c9c, 0x00800000 }, /* LHPF2_INPUT4 */
|
||||
{ 0x00008ca0, 0x00800000 }, /* LHPF3_INPUT1 */
|
||||
{ 0x00008ca4, 0x00800000 }, /* LHPF3_INPUT2 */
|
||||
{ 0x00008ca8, 0x00800000 }, /* LHPF3_INPUT3 */
|
||||
{ 0x00008cac, 0x00800000 }, /* LHPF3_INPUT4 */
|
||||
{ 0x00008cb0, 0x00800000 }, /* LHPF4_INPUT1 */
|
||||
{ 0x00008cb4, 0x00800000 }, /* LHPF4_INPUT2 */
|
||||
{ 0x00008cb8, 0x00800000 }, /* LHPF4_INPUT3 */
|
||||
{ 0x00008cbc, 0x00800000 }, /* LHPF4_INPUT4 */
|
||||
{ 0x00009000, 0x00800000 }, /* DSP1RX1_INPUT1 */
|
||||
{ 0x00009004, 0x00800000 }, /* DSP1RX1_INPUT2 */
|
||||
{ 0x00009008, 0x00800000 }, /* DSP1RX1_INPUT3 */
|
||||
{ 0x0000900c, 0x00800000 }, /* DSP1RX1_INPUT4 */
|
||||
{ 0x00009010, 0x00800000 }, /* DSP1RX2_INPUT1 */
|
||||
{ 0x00009014, 0x00800000 }, /* DSP1RX2_INPUT2 */
|
||||
{ 0x00009018, 0x00800000 }, /* DSP1RX2_INPUT3 */
|
||||
{ 0x0000901c, 0x00800000 }, /* DSP1RX2_INPUT4 */
|
||||
{ 0x00009020, 0x00800000 }, /* DSP1RX3_INPUT1 */
|
||||
{ 0x00009024, 0x00800000 }, /* DSP1RX3_INPUT2 */
|
||||
{ 0x00009028, 0x00800000 }, /* DSP1RX3_INPUT3 */
|
||||
{ 0x0000902c, 0x00800000 }, /* DSP1RX3_INPUT4 */
|
||||
{ 0x00009030, 0x00800000 }, /* DSP1RX4_INPUT1 */
|
||||
{ 0x00009034, 0x00800000 }, /* DSP1RX4_INPUT2 */
|
||||
{ 0x00009038, 0x00800000 }, /* DSP1RX4_INPUT3 */
|
||||
{ 0x0000903c, 0x00800000 }, /* DSP1RX4_INPUT4 */
|
||||
{ 0x00009040, 0x00800000 }, /* DSP1RX5_INPUT1 */
|
||||
{ 0x00009044, 0x00800000 }, /* DSP1RX5_INPUT2 */
|
||||
{ 0x00009048, 0x00800000 }, /* DSP1RX5_INPUT3 */
|
||||
{ 0x0000904c, 0x00800000 }, /* DSP1RX5_INPUT4 */
|
||||
{ 0x00009050, 0x00800000 }, /* DSP1RX6_INPUT1 */
|
||||
{ 0x00009054, 0x00800000 }, /* DSP1RX6_INPUT2 */
|
||||
{ 0x00009058, 0x00800000 }, /* DSP1RX6_INPUT3 */
|
||||
{ 0x0000905c, 0x00800000 }, /* DSP1RX6_INPUT4 */
|
||||
{ 0x00009060, 0x00800000 }, /* DSP1RX7_INPUT1 */
|
||||
{ 0x00009064, 0x00800000 }, /* DSP1RX7_INPUT2 */
|
||||
{ 0x00009068, 0x00800000 }, /* DSP1RX7_INPUT3 */
|
||||
{ 0x0000906c, 0x00800000 }, /* DSP1RX7_INPUT4 */
|
||||
{ 0x00009070, 0x00800000 }, /* DSP1RX8_INPUT1 */
|
||||
{ 0x00009074, 0x00800000 }, /* DSP1RX8_INPUT2 */
|
||||
{ 0x00009078, 0x00800000 }, /* DSP1RX8_INPUT3 */
|
||||
{ 0x0000907c, 0x00800000 }, /* DSP1RX8_INPUT4 */
|
||||
{ 0x0000a400, 0x00000000 }, /* ISRC1_CONTROL1 */
|
||||
{ 0x0000a404, 0x00000000 }, /* ISRC1_CONTROL2 */
|
||||
{ 0x0000a510, 0x00000000 }, /* ISRC2_CONTROL1 */
|
||||
{ 0x0000a514, 0x00000000 }, /* ISRC2_CONTROL2 */
|
||||
{ 0x0000a620, 0x00000000 }, /* ISRC3_CONTROL1 */
|
||||
{ 0x0000a624, 0x00000000 }, /* ISRC3_CONTROL2 */
|
||||
{ 0x0000a800, 0x00000000 }, /* FX_SAMPLE_RATE */
|
||||
{ 0x0000a808, 0x00000000 }, /* EQ_CONTROL1 */
|
||||
{ 0x0000a80c, 0x00000000 }, /* EQ_CONTROL2 */
|
||||
{ 0x0000a810, 0x0c0c0c0c }, /* EQ1_GAIN1 */
|
||||
{ 0x0000a814, 0x0000000c }, /* EQ1_GAIN2 */
|
||||
{ 0x0000a818, 0x03fe0fc8 }, /* EQ1_BAND1_COEFF1 */
|
||||
{ 0x0000a81c, 0x00000b75 }, /* EQ1_BAND1_COEFF2 */
|
||||
{ 0x0000a820, 0x000000e0 }, /* EQ1_BAND1_PG */
|
||||
{ 0x0000a824, 0xf1361ec4 }, /* EQ1_BAND2_COEFF1 */
|
||||
{ 0x0000a828, 0x00000409 }, /* EQ1_BAND2_COEFF2 */
|
||||
{ 0x0000a82c, 0x000004cc }, /* EQ1_BAND2_PG */
|
||||
{ 0x0000a830, 0xf3371c9b }, /* EQ1_BAND3_COEFF1 */
|
||||
{ 0x0000a834, 0x0000040b }, /* EQ1_BAND3_COEFF2 */
|
||||
{ 0x0000a838, 0x00000cbb }, /* EQ1_BAND3_PG */
|
||||
{ 0x0000a83c, 0xf7d916f8 }, /* EQ1_BAND4_COEFF1 */
|
||||
{ 0x0000a840, 0x0000040a }, /* EQ1_BAND4_COEFF2 */
|
||||
{ 0x0000a844, 0x00001f14 }, /* EQ1_BAND4_PG */
|
||||
{ 0x0000a848, 0x0563058c }, /* EQ1_BAND5_COEFF1 */
|
||||
{ 0x0000a84c, 0x00000000 }, /* EQ1_BAND5_COEFF1 + 4 */
|
||||
{ 0x0000a850, 0x00004000 }, /* EQ1_BAND5_PG */
|
||||
{ 0x0000a854, 0x0c0c0c0c }, /* EQ2_GAIN1 */
|
||||
{ 0x0000a858, 0x0000000c }, /* EQ2_GAIN2 */
|
||||
{ 0x0000a85c, 0x03fe0fc8 }, /* EQ2_BAND1_COEFF1 */
|
||||
{ 0x0000a860, 0x00000b75 }, /* EQ2_BAND1_COEFF2 */
|
||||
{ 0x0000a864, 0x000000e0 }, /* EQ2_BAND1_PG */
|
||||
{ 0x0000a868, 0xf1361ec4 }, /* EQ2_BAND2_COEFF1 */
|
||||
{ 0x0000a86c, 0x00000409 }, /* EQ2_BAND2_COEFF2 */
|
||||
{ 0x0000a870, 0x000004cc }, /* EQ2_BAND2_PG */
|
||||
{ 0x0000a874, 0xf3371c9b }, /* EQ2_BAND3_COEFF1 */
|
||||
{ 0x0000a878, 0x0000040b }, /* EQ2_BAND3_COEFF2 */
|
||||
{ 0x0000a87c, 0x00000cbb }, /* EQ2_BAND3_PG */
|
||||
{ 0x0000a880, 0xf7d916f8 }, /* EQ2_BAND4_COEFF1 */
|
||||
{ 0x0000a884, 0x0000040a }, /* EQ2_BAND4_COEFF2 */
|
||||
{ 0x0000a888, 0x00001f14 }, /* EQ2_BAND4_PG */
|
||||
{ 0x0000a88c, 0x0563058c }, /* EQ2_BAND5_COEFF1 */
|
||||
{ 0x0000a890, 0x00000000 }, /* EQ2_BAND5_COEFF1 + 4 */
|
||||
{ 0x0000a894, 0x00004000 }, /* EQ2_BAND5_PG */
|
||||
{ 0x0000a898, 0x0c0c0c0c }, /* EQ3_GAIN1 */
|
||||
{ 0x0000a89c, 0x0000000c }, /* EQ3_GAIN2 */
|
||||
{ 0x0000a8a0, 0x03fe0fc8 }, /* EQ3_BAND1_COEFF1 */
|
||||
{ 0x0000a8a4, 0x00000b75 }, /* EQ3_BAND1_COEFF2 */
|
||||
{ 0x0000a8a8, 0x000000e0 }, /* EQ3_BAND1_PG */
|
||||
{ 0x0000a8ac, 0xf1361ec4 }, /* EQ3_BAND2_COEFF1 */
|
||||
{ 0x0000a8b0, 0x00000409 }, /* EQ3_BAND2_COEFF2 */
|
||||
{ 0x0000a8b4, 0x000004cc }, /* EQ3_BAND2_PG */
|
||||
{ 0x0000a8b8, 0xf3371c9b }, /* EQ3_BAND3_COEFF1 */
|
||||
{ 0x0000a8bc, 0x0000040b }, /* EQ3_BAND3_COEFF2 */
|
||||
{ 0x0000a8c0, 0x00000cbb }, /* EQ3_BAND3_PG */
|
||||
{ 0x0000a8c4, 0xf7d916f8 }, /* EQ3_BAND4_COEFF1 */
|
||||
{ 0x0000a8c8, 0x0000040a }, /* EQ3_BAND4_COEFF2 */
|
||||
{ 0x0000a8cc, 0x00001f14 }, /* EQ3_BAND4_PG */
|
||||
{ 0x0000a8d0, 0x0563058c }, /* EQ3_BAND5_COEFF1 */
|
||||
{ 0x0000a8d4, 0x00000000 }, /* EQ3_BAND5_COEFF1 + 4 */
|
||||
{ 0x0000a8d8, 0x00004000 }, /* EQ3_BAND5_PG */
|
||||
{ 0x0000a8dc, 0x0c0c0c0c }, /* EQ4_GAIN1 */
|
||||
{ 0x0000a8e0, 0x0000000c }, /* EQ4_GAIN2 */
|
||||
{ 0x0000a8e4, 0x03fe0fc8 }, /* EQ4_BAND1_COEFF1 */
|
||||
{ 0x0000a8e8, 0x00000b75 }, /* EQ4_BAND1_COEFF2 */
|
||||
{ 0x0000a8ec, 0x000000e0 }, /* EQ4_BAND1_PG */
|
||||
{ 0x0000a8f0, 0xf1361ec4 }, /* EQ4_BAND2_COEFF1 */
|
||||
{ 0x0000a8f4, 0x00000409 }, /* EQ4_BAND2_COEFF2 */
|
||||
{ 0x0000a8f8, 0x000004cc }, /* EQ4_BAND2_PG */
|
||||
{ 0x0000a8fc, 0xf3371c9b }, /* EQ4_BAND3_COEFF1 */
|
||||
{ 0x0000a900, 0x0000040b }, /* EQ4_BAND3_COEFF2 */
|
||||
{ 0x0000a904, 0x00000cbb }, /* EQ4_BAND3_PG */
|
||||
{ 0x0000a908, 0xf7d916f8 }, /* EQ4_BAND4_COEFF1 */
|
||||
{ 0x0000a90c, 0x0000040a }, /* EQ4_BAND4_COEFF2 */
|
||||
{ 0x0000a910, 0x00001f14 }, /* EQ4_BAND4_PG */
|
||||
{ 0x0000a914, 0x0563058c }, /* EQ4_BAND5_COEFF1 */
|
||||
{ 0x0000a918, 0x00000000 }, /* EQ4_BAND5_COEFF1 + 4 */
|
||||
{ 0x0000a91c, 0x00004000 }, /* EQ4_BAND5_PG */
|
||||
{ 0x0000aa30, 0x00000000 }, /* LHPF_CONTROL1 */
|
||||
{ 0x0000aa34, 0x00000000 }, /* LHPF_CONTROL2 */
|
||||
{ 0x0000aa38, 0x00000000 }, /* LHPF1_COEFF */
|
||||
{ 0x0000aa3c, 0x00000000 }, /* LHPF2_COEFF */
|
||||
{ 0x0000aa40, 0x00000000 }, /* LHPF3_COEFF */
|
||||
{ 0x0000aa44, 0x00000000 }, /* LHPF4_COEFF */
|
||||
{ 0x0000ab00, 0x00000000 }, /* DRC1_CONTROL1 */
|
||||
{ 0x0000ab04, 0x49130018 }, /* DRC1_CONTROL2 */
|
||||
{ 0x0000ab08, 0x00000018 }, /* DRC1_CONTROL3 */
|
||||
{ 0x0000ab0c, 0x00000000 }, /* DRC1_CONTROL4 */
|
||||
{ 0x0000ab14, 0x00000000 }, /* DRC2_CONTROL1 */
|
||||
{ 0x0000ab18, 0x49130018 }, /* DRC2_CONTROL2 */
|
||||
{ 0x0000ab1c, 0x00000018 }, /* DRC2_CONTROL3 */
|
||||
{ 0x0000ab20, 0x00000000 }, /* DRC2_CONTROL4 */
|
||||
{ 0x0000b000, 0x00000000 }, /* TONE_GENERATOR1 */
|
||||
{ 0x0000b004, 0x00100000 }, /* TONE_GENERATOR2 */
|
||||
{ 0x0000b400, 0x00000000 }, /* COMFORT_NOISE_GENERATOR */
|
||||
{ 0x0000b800, 0x00000000 }, /* US_CONTROL */
|
||||
{ 0x0000b804, 0x00002020 }, /* US1_CONTROL */
|
||||
{ 0x0000b808, 0x00000000 }, /* US1_DET_CONTROL */
|
||||
{ 0x0000b814, 0x00002020 }, /* US2_CONTROL */
|
||||
{ 0x0000b818, 0x00000000 }, /* US2_DET_CONTROL */
|
||||
{ 0x00018110, 0x00000700 }, /* IRQ1_MASK_1 */
|
||||
{ 0x00018114, 0x00000004 }, /* IRQ1_MASK_2 */
|
||||
{ 0x00018120, 0x03ff0000 }, /* IRQ1_MASK_5 */
|
||||
{ 0x00018124, 0x00000103 }, /* IRQ1_MASK_6 */
|
||||
{ 0x00018128, 0x003f0000 }, /* IRQ1_MASK_7 */
|
||||
{ 0x00018130, 0xff00000f }, /* IRQ1_MASK_9 */
|
||||
{ 0x00018138, 0xffff0000 }, /* IRQ1_MASK_11 */
|
||||
};
|
||||
|
||||
static bool cs48l32_readable_register(struct device *dev, unsigned int reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case CS48L32_DEVID:
|
||||
case CS48L32_REVID:
|
||||
case CS48L32_OTPID:
|
||||
case CS48L32_SFT_RESET:
|
||||
case CS48L32_CTRL_IF_DEBUG3:
|
||||
case CS48L32_MCU_CTRL1:
|
||||
case CS48L32_GPIO1_CTRL1 ... CS48L32_GPIO16_CTRL1:
|
||||
case CS48L32_OUTPUT_SYS_CLK:
|
||||
case CS48L32_AUXPDM_CTRL:
|
||||
case CS48L32_AUXPDM_CTRL2:
|
||||
case CS48L32_CLOCK32K:
|
||||
case CS48L32_SYSTEM_CLOCK1 ... CS48L32_SYSTEM_CLOCK2:
|
||||
case CS48L32_SAMPLE_RATE1 ... CS48L32_SAMPLE_RATE4:
|
||||
case CS48L32_FLL1_CONTROL1 ... CS48L32_FLL1_GPIO_CLOCK:
|
||||
case CS48L32_CHARGE_PUMP1:
|
||||
case CS48L32_LDO2_CTRL1:
|
||||
case CS48L32_MICBIAS_CTRL1:
|
||||
case CS48L32_MICBIAS_CTRL5:
|
||||
case CS48L32_IRQ1_CTRL_AOD:
|
||||
case CS48L32_INPUT_CONTROL:
|
||||
case CS48L32_INPUT_STATUS:
|
||||
case CS48L32_INPUT_RATE_CONTROL:
|
||||
case CS48L32_INPUT_CONTROL2:
|
||||
case CS48L32_INPUT_CONTROL3:
|
||||
case CS48L32_INPUT1_CONTROL1:
|
||||
case CS48L32_IN1L_CONTROL1 ... CS48L32_IN1L_CONTROL2:
|
||||
case CS48L32_IN1R_CONTROL1 ... CS48L32_IN1R_CONTROL2:
|
||||
case CS48L32_INPUT2_CONTROL1:
|
||||
case CS48L32_IN2L_CONTROL1 ... CS48L32_IN2L_CONTROL2:
|
||||
case CS48L32_IN2R_CONTROL1 ... CS48L32_IN2R_CONTROL2:
|
||||
case CS48L32_INPUT_HPF_CONTROL:
|
||||
case CS48L32_INPUT_VOL_CONTROL:
|
||||
case CS48L32_AUXPDM_CONTROL1:
|
||||
case CS48L32_AUXPDM_CONTROL2:
|
||||
case CS48L32_AUXPDM1_CONTROL1:
|
||||
case CS48L32_AUXPDM2_CONTROL1:
|
||||
case CS48L32_ADC1L_ANA_CONTROL1:
|
||||
case CS48L32_ADC1R_ANA_CONTROL1:
|
||||
case CS48L32_ASP1_ENABLES1 ... CS48L32_ASP1_DATA_CONTROL5:
|
||||
case CS48L32_ASP2_ENABLES1 ... CS48L32_ASP2_DATA_CONTROL5:
|
||||
case CS48L32_ASP1TX1_INPUT1 ... CS48L32_ASP1TX8_INPUT4:
|
||||
case CS48L32_ASP2TX1_INPUT1 ... CS48L32_ASP2TX4_INPUT4:
|
||||
case CS48L32_ISRC1INT1_INPUT1 ... CS48L32_ISRC1DEC4_INPUT1:
|
||||
case CS48L32_ISRC2INT1_INPUT1 ... CS48L32_ISRC2DEC2_INPUT1:
|
||||
case CS48L32_ISRC3INT1_INPUT1 ... CS48L32_ISRC3DEC2_INPUT1:
|
||||
case CS48L32_EQ1_INPUT1 ... CS48L32_EQ4_INPUT4:
|
||||
case CS48L32_DRC1L_INPUT1 ... CS48L32_DRC1R_INPUT4:
|
||||
case CS48L32_DRC2L_INPUT1 ... CS48L32_DRC2R_INPUT4:
|
||||
case CS48L32_LHPF1_INPUT1 ... CS48L32_LHPF1_INPUT4:
|
||||
case CS48L32_LHPF2_INPUT1 ... CS48L32_LHPF2_INPUT4:
|
||||
case CS48L32_LHPF3_INPUT1 ... CS48L32_LHPF3_INPUT4:
|
||||
case CS48L32_LHPF4_INPUT1 ... CS48L32_LHPF4_INPUT4:
|
||||
case CS48L32_DSP1RX1_INPUT1 ... CS48L32_DSP1RX8_INPUT4:
|
||||
case CS48L32_ISRC1_CONTROL1 ... CS48L32_ISRC1_CONTROL2:
|
||||
case CS48L32_ISRC2_CONTROL1 ... CS48L32_ISRC2_CONTROL2:
|
||||
case CS48L32_ISRC3_CONTROL1 ... CS48L32_ISRC3_CONTROL2:
|
||||
case CS48L32_FX_SAMPLE_RATE:
|
||||
case CS48L32_EQ_CONTROL1 ... CS48L32_EQ_CONTROL2:
|
||||
case CS48L32_EQ1_GAIN1 ... CS48L32_EQ1_BAND5_PG:
|
||||
case CS48L32_EQ2_GAIN1 ... CS48L32_EQ2_BAND5_PG:
|
||||
case CS48L32_EQ3_GAIN1 ... CS48L32_EQ3_BAND5_PG:
|
||||
case CS48L32_EQ4_GAIN1 ... CS48L32_EQ4_BAND5_PG:
|
||||
case CS48L32_LHPF_CONTROL1 ... CS48L32_LHPF_CONTROL2:
|
||||
case CS48L32_LHPF1_COEFF ... CS48L32_LHPF4_COEFF:
|
||||
case CS48L32_DRC1_CONTROL1 ... CS48L32_DRC1_CONTROL4:
|
||||
case CS48L32_DRC2_CONTROL1 ... CS48L32_DRC2_CONTROL4:
|
||||
case CS48L32_TONE_GENERATOR1 ... CS48L32_TONE_GENERATOR2:
|
||||
case CS48L32_COMFORT_NOISE_GENERATOR:
|
||||
case CS48L32_US_CONTROL:
|
||||
case CS48L32_US1_CONTROL:
|
||||
case CS48L32_US1_DET_CONTROL:
|
||||
case CS48L32_US2_CONTROL:
|
||||
case CS48L32_US2_DET_CONTROL:
|
||||
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24:
|
||||
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8:
|
||||
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7:
|
||||
case CS48L32_IRQ1_STATUS:
|
||||
case CS48L32_IRQ1_EINT_1 ... CS48L32_IRQ1_EINT_11:
|
||||
case CS48L32_IRQ1_STS_1 ... CS48L32_IRQ1_STS_11:
|
||||
case CS48L32_IRQ1_MASK_1 ... CS48L32_IRQ1_MASK_11:
|
||||
case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_LAST:
|
||||
case CS48L32_DSP1_SYS_INFO_ID ... CS48L32_DSP1_AHBM_WINDOW_DEBUG_1:
|
||||
case CS48L32_DSP1_XMEM_UNPACKED24_0 ... CS48L32_DSP1_XMEM_UNPACKED24_LAST:
|
||||
case CS48L32_DSP1_CLOCK_FREQ ... CS48L32_DSP1_SAMPLE_RATE_TX8:
|
||||
case CS48L32_DSP1_SCRATCH1 ... CS48L32_DSP1_SCRATCH4:
|
||||
case CS48L32_DSP1_CCM_CORE_CONTROL ... CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1:
|
||||
case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_LAST:
|
||||
case CS48L32_DSP1_YMEM_UNPACKED24_0 ... CS48L32_DSP1_YMEM_UNPACKED24_LAST:
|
||||
case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_LAST:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static bool cs48l32_volatile_register(struct device *dev, unsigned int reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case CS48L32_DEVID:
|
||||
case CS48L32_REVID:
|
||||
case CS48L32_OTPID:
|
||||
case CS48L32_SFT_RESET:
|
||||
case CS48L32_CTRL_IF_DEBUG3:
|
||||
case CS48L32_MCU_CTRL1:
|
||||
case CS48L32_SYSTEM_CLOCK2:
|
||||
case CS48L32_FLL1_CONTROL5:
|
||||
case CS48L32_FLL1_CONTROL6:
|
||||
case CS48L32_INPUT_STATUS:
|
||||
case CS48L32_INPUT_CONTROL3:
|
||||
case CS48L32_DSP1_XM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_XM_SRAM_IBUS_SETUP_24:
|
||||
case CS48L32_DSP1_YM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_YM_SRAM_IBUS_SETUP_8:
|
||||
case CS48L32_DSP1_PM_SRAM_IBUS_SETUP_0 ... CS48L32_DSP1_PM_SRAM_IBUS_SETUP_7:
|
||||
case CS48L32_IRQ1_STATUS:
|
||||
case CS48L32_IRQ1_EINT_1 ... CS48L32_IRQ1_EINT_11:
|
||||
case CS48L32_IRQ1_STS_1 ... CS48L32_IRQ1_STS_11:
|
||||
case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_LAST:
|
||||
case CS48L32_DSP1_SYS_INFO_ID ... CS48L32_DSP1_AHBM_WINDOW_DEBUG_1:
|
||||
case CS48L32_DSP1_XMEM_UNPACKED24_0 ... CS48L32_DSP1_XMEM_UNPACKED24_LAST:
|
||||
case CS48L32_DSP1_CLOCK_FREQ ... CS48L32_DSP1_SAMPLE_RATE_TX8:
|
||||
case CS48L32_DSP1_SCRATCH1 ... CS48L32_DSP1_SCRATCH4:
|
||||
case CS48L32_DSP1_CCM_CORE_CONTROL ... CS48L32_DSP1_STREAM_ARB_RESYNC_MSK1:
|
||||
case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_LAST:
|
||||
case CS48L32_DSP1_YMEM_UNPACKED24_0 ... CS48L32_DSP1_YMEM_UNPACKED24_LAST:
|
||||
case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_LAST:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* The bus bridge requires DSP packed memory registers to be accessed in
|
||||
* aligned block multiples.
|
||||
* Mark precious to prevent regmap debugfs causing an illegal bus transaction.
|
||||
*/
|
||||
static bool cs48l32_precious_register(struct device *dev, unsigned int reg)
|
||||
{
|
||||
switch (reg) {
|
||||
case CS48L32_DSP1_XMEM_PACKED_0 ... CS48L32_DSP1_XMEM_PACKED_LAST:
|
||||
case CS48L32_DSP1_YMEM_PACKED_0 ... CS48L32_DSP1_YMEM_PACKED_LAST:
|
||||
case CS48L32_DSP1_PMEM_0 ... CS48L32_DSP1_PMEM_LAST:
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct regmap_config cs48l32_regmap = {
|
||||
.name = "cs48l32",
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.pad_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_format_endian = REGMAP_ENDIAN_BIG,
|
||||
.val_format_endian = REGMAP_ENDIAN_BIG,
|
||||
|
||||
.max_register = CS48L32_DSP1_PMEM_LAST,
|
||||
.readable_reg = &cs48l32_readable_register,
|
||||
.volatile_reg = &cs48l32_volatile_register,
|
||||
.precious_reg = &cs48l32_precious_register,
|
||||
|
||||
.cache_type = REGCACHE_MAPLE,
|
||||
.reg_defaults = cs48l32_reg_default,
|
||||
.num_reg_defaults = ARRAY_SIZE(cs48l32_reg_default),
|
||||
};
|
||||
|
||||
int cs48l32_create_regmap(struct spi_device *spi, struct cs48l32 *cs48l32)
|
||||
{
|
||||
cs48l32->regmap = devm_regmap_init_spi(spi, &cs48l32_regmap);
|
||||
if (IS_ERR(cs48l32->regmap))
|
||||
return PTR_ERR(cs48l32->regmap);
|
||||
|
||||
return 0;
|
||||
}
|
||||
4073
sound/soc/codecs/cs48l32.c
Normal file
4073
sound/soc/codecs/cs48l32.c
Normal file
File diff suppressed because it is too large
Load diff
403
sound/soc/codecs/cs48l32.h
Normal file
403
sound/soc/codecs/cs48l32.h
Normal file
|
|
@ -0,0 +1,403 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Cirrus Logic CS48L32 audio DSP.
|
||||
*
|
||||
* Copyright (C) 2016-2018, 2020, 2022, 2025 Cirrus Logic, Inc. and
|
||||
* Cirrus Logic International Semiconductor Ltd.
|
||||
*/
|
||||
#ifndef SND_SOC_CS48L32_H
|
||||
#define SND_SOC_CS48L32_H
|
||||
|
||||
#include <linux/bits.h>
|
||||
#include <sound/soc.h>
|
||||
#include "wm_adsp.h"
|
||||
|
||||
#define CS48L32_SILICON_ID 0x48a32
|
||||
|
||||
#define CS48L32_32K_MCLK1 0
|
||||
|
||||
#define CS48L32_SFT_RESET_MAGIC 0x5a000000
|
||||
#define CS48L32_SOFT_RESET_US 2000
|
||||
#define CS48L32_HARD_RESET_MIN_US 1000
|
||||
|
||||
#define CS48L32_SEEN_BOOT_DONE BIT(0)
|
||||
#define CS48L32_BOOT_TIMEOUT_US 25000
|
||||
|
||||
#define CS48L32_ASP_ENABLES1 0x00
|
||||
#define CS48L32_ASP_CONTROL1 0x04
|
||||
#define CS48L32_ASP_CONTROL2 0x08
|
||||
#define CS48L32_ASP_CONTROL3 0x0c
|
||||
#define CS48L32_ASP_FRAME_CONTROL1 0x10
|
||||
#define CS48L32_ASP_FRAME_CONTROL2 0x14
|
||||
#define CS48L32_ASP_FRAME_CONTROL5 0x20
|
||||
#define CS48L32_ASP_FRAME_CONTROL6 0x24
|
||||
#define CS48L32_ASP_DATA_CONTROL1 0x30
|
||||
#define CS48L32_ASP_DATA_CONTROL5 0x40
|
||||
#define CS48L32_SYSCLK_RATE_6MHZ 0
|
||||
#define CS48L32_SYSCLK_RATE_12MHZ 1
|
||||
#define CS48L32_SYSCLK_RATE_24MHZ 2
|
||||
#define CS48L32_SYSCLK_RATE_49MHZ 3
|
||||
#define CS48L32_SYSCLK_RATE_98MHZ 4
|
||||
#define CS48L32_FLLHJ_INT_MAX_N 1023
|
||||
#define CS48L32_FLLHJ_INT_MIN_N 1
|
||||
#define CS48L32_FLLHJ_FRAC_MAX_N 255
|
||||
#define CS48L32_FLLHJ_FRAC_MIN_N 2
|
||||
#define CS48L32_FLLHJ_LP_INT_MODE_THRESH 100000
|
||||
#define CS48L32_FLLHJ_LOW_THRESH 192000
|
||||
#define CS48L32_FLLHJ_MID_THRESH 1152000
|
||||
#define CS48L32_FLLHJ_MAX_THRESH 13000000
|
||||
#define CS48L32_FLLHJ_LOW_GAINS 0x23f0
|
||||
#define CS48L32_FLLHJ_MID_GAINS 0x22f2
|
||||
#define CS48L32_FLLHJ_HIGH_GAINS 0x21f0
|
||||
#define CS48L32_FLL_MAX_FOUT 50000000
|
||||
#define CS48L32_FLL_MAX_REFDIV 8
|
||||
#define CS48L32_FLL_CONTROL1_OFFS 0x00
|
||||
#define CS48L32_FLL_CONTROL2_OFFS 0x04
|
||||
#define CS48L32_FLL_CONTROL3_OFFS 0x08
|
||||
#define CS48L32_FLL_CONTROL4_OFFS 0x0c
|
||||
#define CS48L32_FLL_CONTROL5_OFFS 0x10
|
||||
#define CS48L32_FLL_CONTROL6_OFFS 0x14
|
||||
#define CS48L32_FLL_DIGITAL_TEST2_OFFS 0x34
|
||||
#define CS48L32_FLL_GPIO_CLOCK_OFFS 0xa0
|
||||
#define CS48L32_DSP_CLOCK_FREQ_OFFS 0x00000
|
||||
#define CS48L32_ASP_FMT_DSP_MODE_A 0
|
||||
#define CS48L32_ASP_FMT_DSP_MODE_B 1
|
||||
#define CS48L32_ASP_FMT_I2S_MODE 2
|
||||
#define CS48L32_ASP_FMT_LEFT_JUSTIFIED_MODE 3
|
||||
#define CS48L32_HALO_SAMPLE_RATE_RX1 0x00080
|
||||
#define CS48L32_HALO_SAMPLE_RATE_TX1 0x00280
|
||||
#define CS48L32_HALO_DSP_RATE_MASK 0x1f
|
||||
|
||||
#define CS48L32_PDMCLK_SRC_IN1_PDMCLK 0x0
|
||||
#define CS48L32_PDMCLK_SRC_IN2_PDMCLK 0x1
|
||||
#define CS48L32_PDMCLK_SRC_IN3_PDMCLK 0x2
|
||||
#define CS48L32_PDMCLK_SRC_IN4_PDMCLK 0x3
|
||||
#define CS48L32_PDMCLK_SRC_AUXPDM1_CLK 0x8
|
||||
#define CS48L32_PDMCLK_SRC_AUXPDM2_CLK 0x9
|
||||
|
||||
#define CS48L32_MAX_DAI 6
|
||||
#define CS48L32_MAX_INPUT 4
|
||||
#define CS48L32_MAX_ANALOG_INPUT 2
|
||||
#define CS48L32_MAX_IN_MUX_WAYS 2
|
||||
#define CS48L32_MAX_ASP 2
|
||||
|
||||
#define CS48L32_EQ_BLOCK_SZ 60
|
||||
#define CS48L32_N_EQ_BLOCKS 4
|
||||
|
||||
#define CS48L32_DSP_N_RX_CHANNELS 8
|
||||
#define CS48L32_DSP_N_TX_CHANNELS 8
|
||||
|
||||
#define CS48L32_LHPF_MAX_COEFF 4095
|
||||
#define CS48L32_EQ_MAX_COEFF 4095
|
||||
|
||||
#define CS48L32_MIXER_CONTROLS(name, base) \
|
||||
SOC_SINGLE_RANGE_TLV(name " Input 1 Volume", base, \
|
||||
CS48L32_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
|
||||
cs48l32_mixer_tlv), \
|
||||
SOC_SINGLE_RANGE_TLV(name " Input 2 Volume", base + 4, \
|
||||
CS48L32_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
|
||||
cs48l32_mixer_tlv), \
|
||||
SOC_SINGLE_RANGE_TLV(name " Input 3 Volume", base + 8, \
|
||||
CS48L32_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
|
||||
cs48l32_mixer_tlv), \
|
||||
SOC_SINGLE_RANGE_TLV(name " Input 4 Volume", base + 12, \
|
||||
CS48L32_MIXER_VOL_SHIFT, 0x20, 0x50, 0, \
|
||||
cs48l32_mixer_tlv)
|
||||
|
||||
#define CS48L32_MUX_ENUM_DECL(name, reg) \
|
||||
SOC_VALUE_ENUM_SINGLE_DECL( \
|
||||
name, reg, 0, CS48L32_MIXER_SRC_MASK, \
|
||||
cs48l32_mixer_texts, cs48l32_mixer_values)
|
||||
|
||||
#define CS48L32_MUX_CTL_DECL(name) \
|
||||
const struct snd_kcontrol_new name##_mux = SOC_DAPM_ENUM("Route", name##_enum)
|
||||
|
||||
#define CS48L32_MUX_ENUMS(name, base_reg) \
|
||||
static CS48L32_MUX_ENUM_DECL(name##_enum, base_reg); \
|
||||
static CS48L32_MUX_CTL_DECL(name)
|
||||
|
||||
#define CS48L32_MIXER_ENUMS(name, base_reg) \
|
||||
CS48L32_MUX_ENUMS(name##_in1, base_reg); \
|
||||
CS48L32_MUX_ENUMS(name##_in2, base_reg + 4); \
|
||||
CS48L32_MUX_ENUMS(name##_in3, base_reg + 8); \
|
||||
CS48L32_MUX_ENUMS(name##_in4, base_reg + 12)
|
||||
|
||||
#define CS48L32_MUX(name, ctrl) SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
|
||||
|
||||
#define CS48L32_MUX_WIDGETS(name, name_str) CS48L32_MUX(name_str " Input 1", &name##_mux)
|
||||
|
||||
#define CS48L32_MIXER_WIDGETS(name, name_str) \
|
||||
CS48L32_MUX(name_str " Input 1", &name##_in1_mux), \
|
||||
CS48L32_MUX(name_str " Input 2", &name##_in2_mux), \
|
||||
CS48L32_MUX(name_str " Input 3", &name##_in3_mux), \
|
||||
CS48L32_MUX(name_str " Input 4", &name##_in4_mux), \
|
||||
SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
|
||||
|
||||
#define CS48L32_MUX_ROUTES(widget, name) \
|
||||
{ widget, NULL, name " Input 1" }, \
|
||||
CS48L32_MIXER_INPUT_ROUTES(name " Input 1")
|
||||
|
||||
#define CS48L32_MIXER_ROUTES(widget, name) \
|
||||
{ widget, NULL, name " Mixer" }, \
|
||||
{ name " Mixer", NULL, name " Input 1" }, \
|
||||
{ name " Mixer", NULL, name " Input 2" }, \
|
||||
{ name " Mixer", NULL, name " Input 3" }, \
|
||||
{ name " Mixer", NULL, name " Input 4" }, \
|
||||
CS48L32_MIXER_INPUT_ROUTES(name " Input 1"), \
|
||||
CS48L32_MIXER_INPUT_ROUTES(name " Input 2"), \
|
||||
CS48L32_MIXER_INPUT_ROUTES(name " Input 3"), \
|
||||
CS48L32_MIXER_INPUT_ROUTES(name " Input 4")
|
||||
|
||||
#define CS48L32_DSP_ROUTES_1_8_SYSCLK(name) \
|
||||
{ name, NULL, name " Preloader" }, \
|
||||
{ name, NULL, "SYSCLK" }, \
|
||||
{ name " Preload", NULL, name " Preloader" }, \
|
||||
CS48L32_MIXER_ROUTES(name, name "RX1"), \
|
||||
CS48L32_MIXER_ROUTES(name, name "RX2"), \
|
||||
CS48L32_MIXER_ROUTES(name, name "RX3"), \
|
||||
CS48L32_MIXER_ROUTES(name, name "RX4"), \
|
||||
CS48L32_MIXER_ROUTES(name, name "RX5"), \
|
||||
CS48L32_MIXER_ROUTES(name, name "RX6"), \
|
||||
CS48L32_MIXER_ROUTES(name, name "RX7"), \
|
||||
CS48L32_MIXER_ROUTES(name, name "RX8") \
|
||||
|
||||
#define CS48L32_DSP_ROUTES_1_8(name) \
|
||||
{ name, NULL, "DSPCLK" }, \
|
||||
CS48L32_DSP_ROUTES_1_8_SYSCLK(name) \
|
||||
|
||||
#define CS48L32_RATE_CONTROL(name, domain) SOC_ENUM(name, cs48l32_sample_rate[(domain) - 1])
|
||||
|
||||
#define CS48L32_RATE_ENUM(name, enum) \
|
||||
SOC_ENUM_EXT(name, enum, snd_soc_get_enum_double, cs48l32_rate_put)
|
||||
|
||||
#define CS48L32_DSP_RATE_CONTROL(name, num) \
|
||||
SOC_ENUM_EXT(name " Rate", cs48l32_dsp_rate_enum[num], \
|
||||
cs48l32_dsp_rate_get, cs48l32_dsp_rate_put)
|
||||
|
||||
#define CS48L32_EQ_COEFF_CONTROL(xname, xreg, xbase, xshift) \
|
||||
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
|
||||
.info = cs48l32_eq_coeff_info, .get = cs48l32_eq_coeff_get, \
|
||||
.put = cs48l32_eq_coeff_put, .private_value = \
|
||||
(unsigned long)&(struct cs48l32_eq_control) { .reg = xreg,\
|
||||
.shift = xshift, .block_base = xbase, .max = 65535 } }
|
||||
|
||||
#define CS48L32_EQ_REG_NAME_PASTER(eq, band, type) \
|
||||
CS48L32_ ## eq ## _ ## band ## _ ## type
|
||||
|
||||
#define CS48L32_EQ_BAND_COEFF_CONTROLS(name, band) \
|
||||
CS48L32_EQ_COEFF_CONTROL(#name " " #band " A", \
|
||||
CS48L32_EQ_REG_NAME_PASTER(name, band, COEFF1), \
|
||||
CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \
|
||||
0), \
|
||||
CS48L32_EQ_COEFF_CONTROL(#name " " #band " B", \
|
||||
CS48L32_EQ_REG_NAME_PASTER(name, band, COEFF1), \
|
||||
CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \
|
||||
16), \
|
||||
CS48L32_EQ_COEFF_CONTROL(#name " " #band " C", \
|
||||
CS48L32_EQ_REG_NAME_PASTER(name, band, COEFF2), \
|
||||
CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \
|
||||
0), \
|
||||
CS48L32_EQ_COEFF_CONTROL(#name " " #band " PG", \
|
||||
CS48L32_EQ_REG_NAME_PASTER(name, band, PG), \
|
||||
CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \
|
||||
0)
|
||||
|
||||
#define CS48L32_EQ_COEFF_CONTROLS(name) \
|
||||
CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND1), \
|
||||
CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND2), \
|
||||
CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND3), \
|
||||
CS48L32_EQ_BAND_COEFF_CONTROLS(name, BAND4), \
|
||||
CS48L32_EQ_COEFF_CONTROL(#name " BAND5 A", \
|
||||
CS48L32_EQ_REG_NAME_PASTER(name, BAND5, COEFF1), \
|
||||
CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \
|
||||
0), \
|
||||
CS48L32_EQ_COEFF_CONTROL(#name " BAND5 B", \
|
||||
CS48L32_EQ_REG_NAME_PASTER(name, BAND5, COEFF1), \
|
||||
CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \
|
||||
16), \
|
||||
CS48L32_EQ_COEFF_CONTROL(#name " BAND5 PG", \
|
||||
CS48L32_EQ_REG_NAME_PASTER(name, BAND5, PG), \
|
||||
CS48L32_EQ_REG_NAME_PASTER(name, BAND1, COEFF1), \
|
||||
0)
|
||||
|
||||
#define CS48L32_LHPF_CONTROL(xname, xbase) \
|
||||
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
|
||||
.info = snd_soc_bytes_info, .get = snd_soc_bytes_get, \
|
||||
.put = cs48l32_lhpf_coeff_put, .private_value = \
|
||||
((unsigned long)&(struct soc_bytes) { .base = xbase, \
|
||||
.num_regs = 1 }) }
|
||||
|
||||
/* these have a subseq number so they run after SYSCLK and DSPCLK widgets */
|
||||
#define CS48L32_DSP_FREQ_WIDGET_EV(name, num, event) \
|
||||
SND_SOC_DAPM_SUPPLY_S(name "FREQ", 100, SND_SOC_NOPM, num, 0, \
|
||||
event, SND_SOC_DAPM_POST_PMU)
|
||||
|
||||
#define CS48L32_RATES SNDRV_PCM_RATE_KNOT
|
||||
|
||||
#define CS48L32_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
|
||||
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
|
||||
|
||||
#define CS48L32_MIXER_INPUT_ROUTES(name) \
|
||||
{ name, "Tone Generator 1", "Tone Generator 1" }, \
|
||||
{ name, "Tone Generator 2", "Tone Generator 2" }, \
|
||||
{ name, "Noise Generator", "Noise Generator" }, \
|
||||
{ name, "IN1L", "IN1L PGA" }, \
|
||||
{ name, "IN1R", "IN1R PGA" }, \
|
||||
{ name, "IN2L", "IN2L PGA" }, \
|
||||
{ name, "IN2R", "IN2R PGA" }, \
|
||||
{ name, "ASP1RX1", "ASP1RX1" }, \
|
||||
{ name, "ASP1RX2", "ASP1RX2" }, \
|
||||
{ name, "ASP1RX3", "ASP1RX3" }, \
|
||||
{ name, "ASP1RX4", "ASP1RX4" }, \
|
||||
{ name, "ASP1RX5", "ASP1RX5" }, \
|
||||
{ name, "ASP1RX6", "ASP1RX6" }, \
|
||||
{ name, "ASP1RX7", "ASP1RX7" }, \
|
||||
{ name, "ASP1RX8", "ASP1RX8" }, \
|
||||
{ name, "ASP2RX1", "ASP2RX1" }, \
|
||||
{ name, "ASP2RX2", "ASP2RX2" }, \
|
||||
{ name, "ASP2RX3", "ASP2RX3" }, \
|
||||
{ name, "ASP2RX4", "ASP2RX4" }, \
|
||||
{ name, "ISRC1DEC1", "ISRC1DEC1" }, \
|
||||
{ name, "ISRC1DEC2", "ISRC1DEC2" }, \
|
||||
{ name, "ISRC1DEC3", "ISRC1DEC3" }, \
|
||||
{ name, "ISRC1DEC4", "ISRC1DEC4" }, \
|
||||
{ name, "ISRC1INT1", "ISRC1INT1" }, \
|
||||
{ name, "ISRC1INT2", "ISRC1INT2" }, \
|
||||
{ name, "ISRC1INT3", "ISRC1INT3" }, \
|
||||
{ name, "ISRC1INT4", "ISRC1INT4" }, \
|
||||
{ name, "ISRC2DEC1", "ISRC2DEC1" }, \
|
||||
{ name, "ISRC2DEC2", "ISRC2DEC2" }, \
|
||||
{ name, "ISRC2INT1", "ISRC2INT1" }, \
|
||||
{ name, "ISRC2INT2", "ISRC2INT2" }, \
|
||||
{ name, "ISRC3DEC1", "ISRC3DEC1" }, \
|
||||
{ name, "ISRC3DEC2", "ISRC3DEC2" }, \
|
||||
{ name, "ISRC3INT1", "ISRC3INT1" }, \
|
||||
{ name, "ISRC3INT2", "ISRC3INT2" }, \
|
||||
{ name, "EQ1", "EQ1" }, \
|
||||
{ name, "EQ2", "EQ2" }, \
|
||||
{ name, "EQ3", "EQ3" }, \
|
||||
{ name, "EQ4", "EQ4" }, \
|
||||
{ name, "DRC1L", "DRC1L" }, \
|
||||
{ name, "DRC1R", "DRC1R" }, \
|
||||
{ name, "DRC2L", "DRC2L" }, \
|
||||
{ name, "DRC2R", "DRC2R" }, \
|
||||
{ name, "LHPF1", "LHPF1" }, \
|
||||
{ name, "LHPF2", "LHPF2" }, \
|
||||
{ name, "LHPF3", "LHPF3" }, \
|
||||
{ name, "LHPF4", "LHPF4" }, \
|
||||
{ name, "Ultrasonic 1", "Ultrasonic 1" }, \
|
||||
{ name, "Ultrasonic 2", "Ultrasonic 2" }, \
|
||||
{ name, "DSP1.1", "DSP1" }, \
|
||||
{ name, "DSP1.2", "DSP1" }, \
|
||||
{ name, "DSP1.3", "DSP1" }, \
|
||||
{ name, "DSP1.4", "DSP1" }, \
|
||||
{ name, "DSP1.5", "DSP1" }, \
|
||||
{ name, "DSP1.6", "DSP1" }, \
|
||||
{ name, "DSP1.7", "DSP1" }, \
|
||||
{ name, "DSP1.8", "DSP1" }
|
||||
|
||||
struct cs48l32_enum {
|
||||
struct soc_enum mixer_enum;
|
||||
int val;
|
||||
};
|
||||
|
||||
struct cs48l32_eq_control {
|
||||
unsigned int reg;
|
||||
unsigned int shift;
|
||||
unsigned int block_base;
|
||||
unsigned int max;
|
||||
};
|
||||
|
||||
struct cs48l32_dai_priv {
|
||||
int clk;
|
||||
struct snd_pcm_hw_constraint_list constraint;
|
||||
};
|
||||
|
||||
struct cs48l32_dsp_power_reg_block {
|
||||
unsigned int start;
|
||||
unsigned int end;
|
||||
};
|
||||
|
||||
struct cs48l32_dsp_power_regs {
|
||||
const unsigned int *pwd;
|
||||
unsigned int n_pwd;
|
||||
const struct cs48l32_dsp_power_reg_block *ext;
|
||||
unsigned int n_ext;
|
||||
};
|
||||
|
||||
struct cs48l32;
|
||||
struct cs48l32_codec;
|
||||
struct spi_device;
|
||||
|
||||
struct cs48l32_fll_cfg {
|
||||
int n;
|
||||
unsigned int theta;
|
||||
unsigned int lambda;
|
||||
int refdiv;
|
||||
int fratio;
|
||||
int gain;
|
||||
int alt_gain;
|
||||
};
|
||||
|
||||
struct cs48l32_fll {
|
||||
struct cs48l32_codec *codec;
|
||||
int id;
|
||||
unsigned int base;
|
||||
|
||||
unsigned int sts_addr;
|
||||
unsigned int sts_mask;
|
||||
unsigned int fout;
|
||||
int ref_src;
|
||||
unsigned int ref_freq;
|
||||
|
||||
struct cs48l32_fll_cfg ref_cfg;
|
||||
};
|
||||
|
||||
struct cs48l32_codec {
|
||||
struct wm_adsp dsp; /* must be first */
|
||||
struct cs48l32 core;
|
||||
int sysclk;
|
||||
int dspclk;
|
||||
struct cs48l32_dai_priv dai[CS48L32_MAX_DAI];
|
||||
struct cs48l32_fll fll;
|
||||
|
||||
unsigned int in_up_pending;
|
||||
unsigned int in_vu_reg;
|
||||
|
||||
struct mutex rate_lock;
|
||||
|
||||
u8 dsp_dma_rates[CS48L32_DSP_N_RX_CHANNELS + CS48L32_DSP_N_TX_CHANNELS];
|
||||
|
||||
u8 in_type[CS48L32_MAX_ANALOG_INPUT][CS48L32_MAX_IN_MUX_WAYS];
|
||||
u8 pdm_sup[CS48L32_MAX_ANALOG_INPUT];
|
||||
u8 tdm_width[CS48L32_MAX_ASP];
|
||||
u8 tdm_slots[CS48L32_MAX_ASP];
|
||||
|
||||
unsigned int eq_mode[CS48L32_N_EQ_BLOCKS];
|
||||
__be16 eq_coefficients[CS48L32_N_EQ_BLOCKS][CS48L32_EQ_BLOCK_SZ / 2];
|
||||
|
||||
const struct cs48l32_dsp_power_regs *dsp_power_regs;
|
||||
};
|
||||
|
||||
#define cs48l32_fll_err(_fll, fmt, ...) \
|
||||
dev_err(_fll->codec->core.dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
|
||||
#define cs48l32_fll_warn(_fll, fmt, ...) \
|
||||
dev_warn(_fll->codec->core.dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
|
||||
#define cs48l32_fll_dbg(_fll, fmt, ...) \
|
||||
dev_dbg(_fll->codec->core.dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
|
||||
|
||||
#define cs48l32_asp_err(_dai, fmt, ...) \
|
||||
dev_err(_dai->component->dev, "ASP%d: " fmt, _dai->id, ##__VA_ARGS__)
|
||||
#define cs48l32_asp_warn(_dai, fmt, ...) \
|
||||
dev_warn(_dai->component->dev, "ASP%d: " fmt, _dai->id, ##__VA_ARGS__)
|
||||
#define cs48l32_asp_dbg(_dai, fmt, ...) \
|
||||
dev_dbg(_dai->component->dev, "ASP%d: " fmt, _dai->id, ##__VA_ARGS__)
|
||||
|
||||
int cs48l32_apply_patch(struct cs48l32 *cs48l32);
|
||||
int cs48l32_create_regmap(struct spi_device *spi, struct cs48l32 *cs48l32);
|
||||
int cs48l32_enable_asp1_pins(struct cs48l32_codec *cs48l32_codec);
|
||||
int cs48l32_enable_asp2_pins(struct cs48l32_codec *cs48l32_codec);
|
||||
int cs48l32_micvdd_voltage_index(u32 voltage);
|
||||
int cs48l32_micbias1_voltage_index(u32 voltage);
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Reference in a new issue