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drm/amd/display: clean up encoding checks

Browse source 
[Why]
All ASICS we support has YCbCr support, so
the check is unnecessary, the currently logic
in validate output also returns true all
the time, so the unneccessary logic is removed

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Yang 2018-09-14 15:55:01 -04:00 • committed by Alex Deucher
parent b7cd6487a5
commit e15fc81f11
9 changed files with 7 additions and 43 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
View file

@ -665,21 +665,7 @@ bool dce110_link_encoder_validate_dp_output(
if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
return false;
/* default RGB only */
if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
return true;
if (enc110->base.features.flags.bits.IS_YCBCR_CAPABLE)
return true;
/* for DCE 8.x or later DP Y-only feature,
* we need ASIC cap + FeatureSupportDPYonly, not support 666 */
if (crtc_timing->flags.Y_ONLY &&
enc110->base.features.flags.bits.IS_YCBCR_CAPABLE &&
crtc_timing->display_color_depth != COLOR_DEPTH_666)
return true;
return false;
return true;
}
void dce110_link_encoder_construct(

3
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
View file

@ -551,8 +551,7 @@ static const struct encoder_feature_support link_enc_feature = {
.max_hdmi_deep_color = COLOR_DEPTH_121212,
.max_hdmi_pixel_clock = 300000,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_YCBCR_CAPABLE = true
.flags.bits.IS_TPS3_CAPABLE = true
};
struct link_encoder *dce100_link_encoder_create(

3
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
View file

@ -570,8 +570,7 @@ static const struct encoder_feature_support link_enc_feature = {
.max_hdmi_deep_color = COLOR_DEPTH_121212,
.max_hdmi_pixel_clock = 594000,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_YCBCR_CAPABLE = true
.flags.bits.IS_TPS3_CAPABLE = true
};
static struct link_encoder *dce110_link_encoder_create(

3
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
View file

@ -555,8 +555,7 @@ static const struct encoder_feature_support link_enc_feature = {
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_HBR3_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_TPS4_CAPABLE = true,
.flags.bits.IS_YCBCR_CAPABLE = true
.flags.bits.IS_TPS4_CAPABLE = true
};
struct link_encoder *dce112_link_encoder_create(

1
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
View file

@ -609,7 +609,6 @@ static const struct encoder_feature_support link_enc_feature = {
.flags.bits.IS_HBR3_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_TPS4_CAPABLE = true,
.flags.bits.IS_YCBCR_CAPABLE = true
};
static struct link_encoder *dce120_link_encoder_create(

3
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
View file

@ -650,8 +650,7 @@ static const struct encoder_feature_support link_enc_feature = {
.max_hdmi_deep_color = COLOR_DEPTH_121212,
.max_hdmi_pixel_clock = 297000,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_YCBCR_CAPABLE = true
.flags.bits.IS_TPS3_CAPABLE = true
};
struct link_encoder *dce80_link_encoder_create(

17
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
View file

@ -609,22 +609,7 @@ bool dcn10_link_encoder_validate_dp_output(
if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
return false;
/* default RGB only */
if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB)
return true;
if (enc10->base.features.flags.bits.IS_YCBCR_CAPABLE)
return true;
/* for DCE 8.x or later DP Y-only feature,
* we need ASIC cap + FeatureSupportDPYonly, not support 666
*/
if (crtc_timing->flags.Y_ONLY &&
enc10->base.features.flags.bits.IS_YCBCR_CAPABLE &&
crtc_timing->display_color_depth != COLOR_DEPTH_666)
return true;
return false;
return true;
}
void dcn10_link_encoder_construct(

3
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
View file

@ -711,8 +711,7 @@ static const struct encoder_feature_support link_enc_feature = {
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_HBR3_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_TPS4_CAPABLE = true,
.flags.bits.IS_YCBCR_CAPABLE = true
.flags.bits.IS_TPS4_CAPABLE = true
};
struct link_encoder *dcn10_link_encoder_create(

1
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
View file

@ -58,7 +58,6 @@ struct encoder_feature_support {
uint32_t IS_HBR3_CAPABLE:1;
uint32_t IS_TPS3_CAPABLE:1;
uint32_t IS_TPS4_CAPABLE:1;
uint32_t IS_YCBCR_CAPABLE:1;
uint32_t HDMI_6GB_EN:1;
} bits;
uint32_t raw;