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memory: tegra: Rework update_clock_tree_delay()

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Further streamline this function by moving the delay post-processing
to the callers, leaving it only with the task of returning the measured
delay values.

Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Link: https://lore.kernel.org/r/20240704-tegra210_emcfreq-v4-7-3e450503c555@tecnico.ulisboa.pt
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Diogo Ivo 2024-07-04 12:31:26 +01:00 • committed by Krzysztof Kozlowski
parent b109656e9c
commit ddb869ea23
1 changed files with 48 additions and 74 deletions
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122
drivers/memory/tegra/tegra210-emc-cc-r21021.c
View file

@ -105,7 +105,7 @@ enum {
next->ptfv_list[w])) / \ next->ptfv_list[w])) / \
(next->ptfv_list[w] + 1); \ (next->ptfv_list[w] + 1); \
\ \
emc_dbg(emc, EMA_UPDATES, "%s: (s=%lu) EMA: %u\n", \ emc_dbg(emc, EMA_UPDATES, "%s: (s=%u) EMA: %u\n", \
__stringify(dev), nval, next->ptfv_list[dqs]); \ __stringify(dev), nval, next->ptfv_list[dqs]); \
} while (0) } while (0)
@ -130,93 +130,53 @@ static bool tegra210_emc_compare_update_delay(struct tegra210_emc_timing *timing
return false; return false;
} }
static bool update_clock_tree_delay(struct tegra210_emc *emc, int type) static void tegra210_emc_get_clktree_delay(struct tegra210_emc *emc,
u32 delay[DRAM_CLKTREE_NUM])
{ {
bool periodic_training_update = type == PERIODIC_TRAINING_UPDATE; struct tegra210_emc_timing *curr = emc->last;
struct tegra210_emc_timing *last = emc->last; u32 rate_mhz = curr->rate / 1000;
struct tegra210_emc_timing *next = emc->next; u32 msb, lsb, dqsosc, delay_us;
u32 last_timing_rate_mhz = last->rate / 1000;
bool dvfs_update = type == DVFS_UPDATE;
bool dvfs_pt1 = type == DVFS_PT1;
u32 temp[2][2], value, delay_us;
unsigned long cval = 0;
unsigned int c, d, idx; unsigned int c, d, idx;
bool over = false; unsigned long clocks;
if (dvfs_pt1 || periodic_training_update) { clocks = tegra210_emc_actual_osc_clocks(curr->run_clocks);
delay_us = tegra210_emc_actual_osc_clocks(last->run_clocks); delay_us = 2 + (clocks / rate_mhz);
delay_us *= 1000;
delay_us = 2 + (delay_us / last->rate);
tegra210_emc_start_periodic_compensation(emc); tegra210_emc_start_periodic_compensation(emc);
udelay(delay_us); udelay(delay_us);
}
for (d = 0; d < emc->num_devices; d++) { for (d = 0; d < emc->num_devices; d++) {
if (dvfs_pt1 || periodic_training_update) { /* Read DQSOSC from MRR18/19 */
/* Dev[d] MSB */ msb = tegra210_emc_mrr_read(emc, 2 - d, 19);
value = tegra210_emc_mrr_read(emc, 2 - d, 19); lsb = tegra210_emc_mrr_read(emc, 2 - d, 18);
for (c = 0; c < emc->num_channels; c++) {
temp[c][0] = (value & 0x00ff) << 8;
temp[c][1] = (value & 0xff00) << 0;
value >>= 16;
}
/* Dev[d] LSB */
value = tegra210_emc_mrr_read(emc, 2 - d, 18);
for (c = 0; c < emc->num_channels; c++) {
temp[c][0] |= (value & 0x00ff) >> 0;
temp[c][1] |= (value & 0xff00) >> 8;
value >>= 16;
}
}
for (c = 0; c < emc->num_channels; c++) { for (c = 0; c < emc->num_channels; c++) {
/* C[c]D[d]U[0] */ /* C[c]D[d]U[0] */
idx = c * 4 + d * 2; idx = c * 4 + d * 2;
if (dvfs_pt1 || periodic_training_update) { dqsosc = (msb & 0x00ff) << 8;
cval = tegra210_emc_actual_osc_clocks(last->run_clocks); dqsosc |= (lsb & 0x00ff) >> 0;
cval *= 1000000;
cval /= last_timing_rate_mhz * 2 * temp[c][0];
}
if (dvfs_pt1) /* Check for unpopulated channels */
__INCREMENT_PTFV(idx, cval); if (dqsosc)
else if (dvfs_update) delay[idx] = (clocks * 1000000) /
__AVERAGE_PTFV(idx); (rate_mhz * 2 * dqsosc);
else if (periodic_training_update)
__WEIGHTED_UPDATE_PTFV(idx, cval);
if (dvfs_update || periodic_training_update)
over |= tegra210_emc_compare_update_delay(next,
__MOVAVG_AC(next, idx), idx);
/* C[c]D[d]U[1] */ /* C[c]D[d]U[1] */
idx++; idx++;
if (dvfs_pt1 || periodic_training_update) { dqsosc = (msb & 0xff00) << 0;
cval = tegra210_emc_actual_osc_clocks(last->run_clocks); dqsosc |= (lsb & 0xff00) >> 8;
cval *= 1000000;
cval /= last_timing_rate_mhz * 2 * temp[c][1];
}
if (dvfs_pt1) /* Check for unpopulated channels */
__INCREMENT_PTFV(idx, cval); if (dqsosc)
else if (dvfs_update) delay[idx] = (clocks * 1000000) /
__AVERAGE_PTFV(idx); (rate_mhz * 2 * dqsosc);
else if (periodic_training_update)
__WEIGHTED_UPDATE_PTFV(idx, cval);
if (dvfs_update || periodic_training_update) msb >>= 16;
over |= tegra210_emc_compare_update_delay(next, lsb >>= 16;
__MOVAVG_AC(next, idx), idx);
} }
} }
return over;
} }
static bool periodic_compensation_handler(struct tegra210_emc *emc, u32 type, static bool periodic_compensation_handler(struct tegra210_emc *emc, u32 type,
@ -228,8 +188,8 @@ static bool periodic_compensation_handler(struct tegra210_emc *emc, u32 type,
(nt)->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; }) (nt)->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; })
u32 i, samples = next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; u32 i, samples = next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX];
u32 delay[DRAM_CLKTREE_NUM], idx;
bool over = false; bool over = false;
u32 idx;
if (!next->periodic_training) if (!next->periodic_training)
return 0; return 0;
@ -252,16 +212,30 @@ static bool periodic_compensation_handler(struct tegra210_emc *emc, u32 type,
for (i = 0; i < samples; i++) { for (i = 0; i < samples; i++) {
/* Generate next sample of data. */ /* Generate next sample of data. */
update_clock_tree_delay(emc, DVFS_PT1); tegra210_emc_get_clktree_delay(emc, delay);
for (idx = 0; idx < DRAM_CLKTREE_NUM; idx++)
__INCREMENT_PTFV(idx, delay[idx]);
} }
} }
/* Do the division part of the moving average */ for (idx = 0; idx < DRAM_CLKTREE_NUM; idx++) {
over = update_clock_tree_delay(emc, DVFS_UPDATE); /* Do the division part of the moving average */
__AVERAGE_PTFV(idx);
over |= tegra210_emc_compare_update_delay(next,
__MOVAVG_AC(next, idx), idx);
}
} }
if (type == PERIODIC_TRAINING_SEQUENCE) if (type == PERIODIC_TRAINING_SEQUENCE) {
over = update_clock_tree_delay(emc, PERIODIC_TRAINING_UPDATE); tegra210_emc_get_clktree_delay(emc, delay);
for (idx = 0; idx < DRAM_CLKTREE_NUM; idx++) {
__WEIGHTED_UPDATE_PTFV(idx, delay[idx]);
over |= tegra210_emc_compare_update_delay(next,
__MOVAVG_AC(next, idx), idx);
}
}
return over; return over;
} }