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drm/amdgpu: Nerf buff
buff --> buf. Essentially buffer abbreviates to buf, remove 1/2 of it, or just the iron part, as opposed to just the Er, Cc: Alexander Deucher <Alexander.Deucher@amd.com> Cc: Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Signed-off-by: Luben Tuikov <luben.tuikov@amd.com> Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Luben Tuikov
Alex Deucher
parent
e4e6a58935
commit
d7edde3dea
1 changed files with 49 additions and 49 deletions
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@ -117,10 +117,10 @@ static bool __get_eeprom_i2c_addr(struct amdgpu_device *adev,
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return true;
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}
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static void __encode_table_header_to_buff(struct amdgpu_ras_eeprom_table_header *hdr,
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unsigned char *buff)
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static void __encode_table_header_to_buf(struct amdgpu_ras_eeprom_table_header *hdr,
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unsigned char *buf)
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{
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uint32_t *pp = (uint32_t *) buff;
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uint32_t *pp = (uint32_t *) buf;
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pp[0] = cpu_to_le32(hdr->header);
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pp[1] = cpu_to_le32(hdr->version);
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@ -129,10 +129,10 @@ static void __encode_table_header_to_buff(struct amdgpu_ras_eeprom_table_header
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pp[4] = cpu_to_le32(hdr->checksum);
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}
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static void __decode_table_header_from_buff(struct amdgpu_ras_eeprom_table_header *hdr,
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unsigned char *buff)
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static void __decode_table_header_from_buf(struct amdgpu_ras_eeprom_table_header *hdr,
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unsigned char *buf)
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{
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uint32_t *pp = (uint32_t *)buff;
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u32 *pp = (uint32_t *) buf;
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hdr->header = le32_to_cpu(pp[0]);
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hdr->version = le32_to_cpu(pp[1]);
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@ -142,18 +142,18 @@ static void __decode_table_header_from_buff(struct amdgpu_ras_eeprom_table_heade
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}
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static int __write_table_header(struct amdgpu_ras_eeprom_control *control,
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unsigned char *buff)
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unsigned char *buf)
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{
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int ret = 0;
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struct amdgpu_device *adev = to_amdgpu_device(control);
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__encode_table_header_to_buff(&control->tbl_hdr, buff);
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__encode_table_header_to_buf(&control->tbl_hdr, buf);
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/* i2c may be unstable in gpu reset */
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down_read(&adev->reset_sem);
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ret = amdgpu_eeprom_write(&adev->pm.smu_i2c,
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control->i2c_address + RAS_HDR_START,
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buff, RAS_TABLE_HEADER_SIZE);
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buf, RAS_TABLE_HEADER_SIZE);
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up_read(&adev->reset_sem);
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if (ret < 1)
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@ -240,15 +240,15 @@ static int amdgpu_ras_eeprom_correct_header_tag(
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struct amdgpu_ras_eeprom_control *control,
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uint32_t header)
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{
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unsigned char buff[RAS_TABLE_HEADER_SIZE];
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unsigned char buf[RAS_TABLE_HEADER_SIZE];
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struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
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int ret = 0;
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memset(buff, 0, RAS_TABLE_HEADER_SIZE);
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memset(buf, 0, RAS_TABLE_HEADER_SIZE);
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mutex_lock(&control->tbl_mutex);
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hdr->header = header;
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ret = __write_table_header(control, buff);
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ret = __write_table_header(control, buf);
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mutex_unlock(&control->tbl_mutex);
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return ret;
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@ -256,7 +256,7 @@ static int amdgpu_ras_eeprom_correct_header_tag(
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int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
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{
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unsigned char buff[RAS_TABLE_HEADER_SIZE] = { 0 };
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unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 };
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struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
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int ret = 0;
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@ -269,7 +269,7 @@ int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
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__update_tbl_checksum(control, NULL, 0);
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control->next_addr = RAS_RECORD_START;
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ret = __write_table_header(control, buff);
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ret = __write_table_header(control, buf);
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mutex_unlock(&control->tbl_mutex);
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@ -282,7 +282,7 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
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{
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int ret = 0;
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struct amdgpu_device *adev = to_amdgpu_device(control);
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unsigned char buff[RAS_TABLE_HEADER_SIZE] = { 0 };
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unsigned char buf[RAS_TABLE_HEADER_SIZE] = { 0 };
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struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
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struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
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@ -303,13 +303,13 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
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/* Read/Create table header from EEPROM address 0 */
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ret = amdgpu_eeprom_read(&adev->pm.smu_i2c,
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control->i2c_address + RAS_HDR_START,
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buff, RAS_TABLE_HEADER_SIZE);
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buf, RAS_TABLE_HEADER_SIZE);
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if (ret < 1) {
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DRM_ERROR("Failed to read EEPROM table header, ret:%d", ret);
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return ret;
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}
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__decode_table_header_from_buff(hdr, buff);
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__decode_table_header_from_buf(hdr, buf);
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if (hdr->header == RAS_TABLE_HDR_VAL) {
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control->num_recs = (hdr->tbl_size - RAS_TABLE_HEADER_SIZE) /
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@ -341,57 +341,57 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
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return ret > 0 ? 0 : -EIO;
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}
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static void __encode_table_record_to_buff(struct amdgpu_ras_eeprom_control *control,
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struct eeprom_table_record *record,
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unsigned char *buff)
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static void __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control,
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struct eeprom_table_record *record,
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unsigned char *buf)
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{
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__le64 tmp = 0;
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int i = 0;
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/* Next are all record fields according to EEPROM page spec in LE foramt */
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buff[i++] = record->err_type;
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buf[i++] = record->err_type;
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buff[i++] = record->bank;
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buf[i++] = record->bank;
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tmp = cpu_to_le64(record->ts);
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memcpy(buff + i, &tmp, 8);
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memcpy(buf + i, &tmp, 8);
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i += 8;
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tmp = cpu_to_le64((record->offset & 0xffffffffffff));
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memcpy(buff + i, &tmp, 6);
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memcpy(buf + i, &tmp, 6);
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i += 6;
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buff[i++] = record->mem_channel;
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buff[i++] = record->mcumc_id;
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buf[i++] = record->mem_channel;
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buf[i++] = record->mcumc_id;
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tmp = cpu_to_le64((record->retired_page & 0xffffffffffff));
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memcpy(buff + i, &tmp, 6);
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memcpy(buf + i, &tmp, 6);
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}
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static void __decode_table_record_from_buff(struct amdgpu_ras_eeprom_control *control,
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struct eeprom_table_record *record,
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unsigned char *buff)
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static void __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control,
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struct eeprom_table_record *record,
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unsigned char *buf)
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{
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__le64 tmp = 0;
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int i = 0;
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/* Next are all record fields according to EEPROM page spec in LE foramt */
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record->err_type = buff[i++];
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record->err_type = buf[i++];
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record->bank = buff[i++];
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record->bank = buf[i++];
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memcpy(&tmp, buff + i, 8);
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memcpy(&tmp, buf + i, 8);
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record->ts = le64_to_cpu(tmp);
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i += 8;
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memcpy(&tmp, buff + i, 6);
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memcpy(&tmp, buf + i, 6);
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record->offset = (le64_to_cpu(tmp) & 0xffffffffffff);
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i += 6;
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record->mem_channel = buff[i++];
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record->mcumc_id = buff[i++];
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record->mem_channel = buf[i++];
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record->mcumc_id = buf[i++];
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memcpy(&tmp, buff + i, 6);
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memcpy(&tmp, buf + i, 6);
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record->retired_page = (le64_to_cpu(tmp) & 0xffffffffffff);
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}
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@ -440,7 +440,7 @@ static int amdgpu_ras_eeprom_xfer(struct amdgpu_ras_eeprom_control *control,
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const u32 num, bool write)
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{
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int i, ret = 0;
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unsigned char *buffs, *buff;
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unsigned char *bufs, *buf;
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struct eeprom_table_record *record;
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struct amdgpu_device *adev = to_amdgpu_device(control);
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struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
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@ -448,8 +448,8 @@ static int amdgpu_ras_eeprom_xfer(struct amdgpu_ras_eeprom_control *control,
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if (!__is_ras_eeprom_supported(adev))
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return 0;
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buffs = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
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if (!buffs)
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bufs = kcalloc(num, RAS_TABLE_RECORD_SIZE, GFP_KERNEL);
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if (!bufs)
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return -ENOMEM;
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mutex_lock(&control->tbl_mutex);
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@ -485,27 +485,27 @@ static int amdgpu_ras_eeprom_xfer(struct amdgpu_ras_eeprom_control *control,
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* 256b
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*/
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for (i = 0; i < num; i++) {
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buff = &buffs[i * RAS_TABLE_RECORD_SIZE];
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buf = &bufs[i * RAS_TABLE_RECORD_SIZE];
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record = &records[i];
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control->next_addr = __correct_eeprom_dest_address(control->next_addr);
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/* EEPROM table content is stored in LE format */
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if (write)
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__encode_table_record_to_buff(control, record, buff);
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__encode_table_record_to_buf(control, record, buf);
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/* i2c may be unstable in gpu reset */
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down_read(&adev->reset_sem);
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ret = amdgpu_eeprom_xfer(&adev->pm.smu_i2c,
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control->i2c_address + control->next_addr,
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buff, RAS_TABLE_RECORD_SIZE, !write);
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buf, RAS_TABLE_RECORD_SIZE, !write);
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up_read(&adev->reset_sem);
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if (ret < 1) {
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DRM_ERROR("Failed to process EEPROM table records, ret:%d", ret);
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/* TODO Restore prev next EEPROM address ? */
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goto free_buff;
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goto free_buf;
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}
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/*
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* The destination EEPROM address might need to be corrected to account
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@ -516,10 +516,10 @@ static int amdgpu_ras_eeprom_xfer(struct amdgpu_ras_eeprom_control *control,
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if (!write) {
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for (i = 0; i < num; i++) {
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buff = &buffs[i * RAS_TABLE_RECORD_SIZE];
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buf = &bufs[i * RAS_TABLE_RECORD_SIZE];
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record = &records[i];
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__decode_table_record_from_buff(control, record, buff);
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__decode_table_record_from_buf(control, record, buf);
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}
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}
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@ -539,15 +539,15 @@ static int amdgpu_ras_eeprom_xfer(struct amdgpu_ras_eeprom_control *control,
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control->num_recs * RAS_TABLE_RECORD_SIZE;
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__update_tbl_checksum(control, records, num);
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__write_table_header(control, buffs);
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__write_table_header(control, bufs);
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} else if (!__verify_tbl_checksum(control, records, num)) {
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DRM_WARN("EEPROM Table checksum mismatch!");
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/* TODO Uncomment when EEPROM read/write is relliable */
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/* ret = -EIO; */
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}
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free_buff:
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kfree(buffs);
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free_buf:
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kfree(bufs);
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mutex_unlock(&control->tbl_mutex);
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