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dt-bindings: xilinx: Switch xilinx.com emails to amd.com

Browse source 
@xilinx.com is still working but better to switch to new amd.com after
AMD/Xilinx acquisition.

Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Wolfram Sang <wsa@kernel.org> # for I2C
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Acked-by: Damien Le Moal <dlemoal@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f5b2bd1e78407e4128fc8f0b5874ba723e710a88.1684245058.git.michal.simek@amd.com
This commit is contained in:
Michal Simek 2023-05-16 15:51:08 +02:00
parent 45fe0dc4ea
commit d5c421d24d
29 changed files with 31 additions and 31 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/xilinx.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Platforms
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
description: |
Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC

2
Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ceva AHCI SATA Controller
maintainers:
- Piyush Mehta <piyush.mehta@xilinx.com>
- Piyush Mehta <piyush.mehta@amd.com>
description: |
The Ceva SATA controller mostly conforms to the AHCI interface with some

2
Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx clocking wizard
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
description:
The clocking wizard is a soft ip clocking block of Xilinx versal. It

2
Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Versal clock controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
- Jolly Shah <jolly.shah@xilinx.com>
- Rajan Vaja <rajan.vaja@xilinx.com>

4
Documentation/devicetree/bindings/crypto/xlnx,zynqmp-aes.yaml
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@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP AES-GCM Hardware Accelerator
maintainers:
- Kalyani Akula <kalyani.akula@xilinx.com>
- Michal Simek <michal.simek@xilinx.com>
- Kalyani Akula <kalyani.akula@amd.com>
- Michal Simek <michal.simek@amd.com>
description: |
The ZynqMP AES-GCM hardened cryptographic accelerator is used to

2
Documentation/devicetree/bindings/firmware/xilinx/xlnx,zynqmp-firmware.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx firmware driver
maintainers:
- Nava kishore Manne <nava.manne@xilinx.com>
- Nava kishore Manne <nava.kishore.manne@amd.com>
description: The zynqmp-firmware node describes the interface to platform
firmware. ZynqMP has an interface to communicate with secure firmware.

2
Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq FPGA Manager
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
properties:
compatible:

2
Documentation/devicetree/bindings/fpga/xlnx,versal-fpga.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Versal FPGA driver.
maintainers:
- Nava kishore Manne <nava.manne@xilinx.com>
- Nava kishore Manne <nava.kishore.manne@amd.com>
description: |
Device Tree Versal FPGA bindings for the Versal SoC, controlled

2
Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
maintainers:
- Nava kishore Manne <navam@xilinx.com>
- Nava kishore Manne <nava.kishore.manne@amd.com>
description: |
Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.

2
Documentation/devicetree/bindings/gpio/gpio-zynq.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq GPIO controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
properties:
compatible:

2
Documentation/devicetree/bindings/gpio/xlnx,gpio-xilinx.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx AXI GPIO controller
maintainers:
- Neeli Srinivas <srinivas.neeli@xilinx.com>
- Neeli Srinivas <srinivas.neeli@amd.com>
description:
The AXI GPIO design provides a general purpose input/output interface

2
Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml
View file

@ -12,7 +12,7 @@ description:
PS_MODE). Every pin can be configured as input/output.
maintainers:
- Piyush Mehta <piyush.mehta@xilinx.com>
- Piyush Mehta <piyush.mehta@amd.com>
properties:
compatible:

2
Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence I2C controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#

2
Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
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@ -33,7 +33,7 @@ description: |
+------------------------------------------+
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
properties:
compatible:

2
Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx MIPI CSI-2 Receiver Subsystem
maintainers:
- Vishal Sagar <vishal.sagar@xilinx.com>
- Vishal Sagar <vishal.sagar@amd.com>
description: |
The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2

2
Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
View file

@ -9,7 +9,7 @@ title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
- Manish Narani <manish.narani@xilinx.com>
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
description: |
Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of

2
Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
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@ -9,7 +9,7 @@ title: Zynq A05 DDR Memory Controller
maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
- Manish Narani <manish.narani@xilinx.com>
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
description:
The Zynq DDR ECC controller has an optional ECC support in half-bus width

2
Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: CPM Host Controller device tree for Xilinx Versal SoCs
maintainers:
- Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
- Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
allOf:
- $ref: /schemas/pci/pci-bus.yaml#

2
Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Pinctrl
maintainers:
- Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
- Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
description: |
Please refer to pinctrl-bindings.txt in this directory for details of the

2
Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP Pinctrl
maintainers:
- Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
- Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
- Rajan Vaja <rajan.vaja@xilinx.com>
description: |

2
Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq MPSoC Power Management
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
description: |
The zynqmp-power node describes the power management configurations.

2
Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
View file

@ -11,7 +11,7 @@ description:
The RTC controller has separate IRQ lines for seconds and alarm.
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
allOf:
- $ref: rtc.yaml#

2
Documentation/devicetree/bindings/serial/cdns,uart.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence UART Controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
properties:
compatible:

2
Documentation/devicetree/bindings/spi/spi-cadence.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence SPI controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
allOf:
- $ref: spi-controller.yaml#

2
Documentation/devicetree/bindings/spi/spi-xilinx.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx SPI controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
allOf:
- $ref: spi-controller.yaml#

2
Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
allOf:
- $ref: spi-controller.yaml#

2
Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml
View file

@ -14,7 +14,7 @@ allOf:
- $ref: spi-controller.yaml#
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
# Everything else is described in the common file
properties:

2
Documentation/devicetree/bindings/timer/cdns,ttc.yaml
View file

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence TTC - Triple Timer Counter
maintainers:
- Michal Simek <michal.simek@xilinx.com>
- Michal Simek <michal.simek@amd.com>
properties:
compatible:

4
Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
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@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx AXI/PLB softcore and window Watchdog Timer
maintainers:
- Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
- Srinivas Neeli <srinivas.neeli@xilinx.com>
- Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
- Srinivas Neeli <srinivas.neeli@amd.com>
description:
The Timebase watchdog timer(WDT) is a free-running 32 bit counter.