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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-10-31 16:54:21 +00:00
[MIPS] Add GT641xx IRQ routines.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Yoichi Yuasa
Ralf Baechle
parent
718f05f6dd
commit
d5ab1a6910
11 changed files with 307 additions and 135 deletions
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@ -64,6 +64,7 @@ config MIPS_COBALT
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select HW_HAS_PCI
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select I8259
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select IRQ_CPU
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select IRQ_GT641XX
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select PCI_GT64XXX_PCI0
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select SYS_HAS_CPU_NEVADA
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select SYS_HAS_EARLY_PRINTK
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@ -806,6 +807,9 @@ config IRQ_MSP_CIC
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config IRQ_TXX9
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bool
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config IRQ_GT641XX
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bool
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config MIPS_BOARDS_GEN
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bool
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@ -15,104 +15,48 @@
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#include <asm/i8259.h>
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#include <asm/irq_cpu.h>
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#include <asm/irq_gt641xx.h>
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#include <asm/gt64120.h>
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#include <cobalt.h>
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/*
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* We have two types of interrupts that we handle, ones that come in through
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* the CPU interrupt lines, and ones that come in on the via chip. The CPU
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* mappings are:
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*
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* 16 - Software interrupt 0 (unused) IE_SW0
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* 17 - Software interrupt 1 (unused) IE_SW1
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* 18 - Galileo chip (timer) IE_IRQ0
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* 19 - Tulip 0 + NCR SCSI IE_IRQ1
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* 20 - Tulip 1 IE_IRQ2
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* 21 - 16550 UART IE_IRQ3
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* 22 - VIA southbridge PIC IE_IRQ4
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* 23 - unused IE_IRQ5
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*
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* The VIA chip is a master/slave 8259 setup and has the following interrupts:
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*
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* 8 - RTC
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* 9 - PCI
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* 14 - IDE0
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* 15 - IDE1
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*/
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static inline void galileo_irq(void)
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{
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unsigned int mask, pending, devfn;
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mask = GT_READ(GT_INTRMASK_OFS);
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pending = GT_READ(GT_INTRCAUSE_OFS) & mask;
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if (pending & GT_INTR_T0EXP_MSK) {
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GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);
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do_IRQ(COBALT_GALILEO_IRQ);
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} else if (pending & GT_INTR_RETRYCTR0_MSK) {
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devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;
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GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);
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printk(KERN_WARNING
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"Galileo: PCI retry count exceeded (%02x.%u)\n",
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PCI_SLOT(devfn), PCI_FUNC(devfn));
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} else {
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GT_WRITE(GT_INTRMASK_OFS, mask & ~pending);
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printk(KERN_WARNING
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"Galileo: masking unexpected interrupt %08x\n", pending);
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}
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}
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static inline void via_pic_irq(void)
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{
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int irq;
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irq = i8259_irq();
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if (irq >= 0)
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do_IRQ(irq);
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}
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#include <irq.h>
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned pending = read_c0_status() & read_c0_cause();
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unsigned pending = read_c0_status() & read_c0_cause() & ST0_IM;
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int irq;
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if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */
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galileo_irq();
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else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */
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via_pic_irq();
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else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */
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do_IRQ(COBALT_CPU_IRQ + 3);
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else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */
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do_IRQ(COBALT_CPU_IRQ + 4);
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else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */
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do_IRQ(COBALT_CPU_IRQ + 5);
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else if (pending & CAUSEF_IP7) /* IRQ 23 */
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do_IRQ(COBALT_CPU_IRQ + 7);
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if (pending & CAUSEF_IP2)
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gt641xx_irq_dispatch();
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else if (pending & CAUSEF_IP6) {
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irq = i8259_irq();
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if (irq < 0)
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spurious_interrupt();
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else
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do_IRQ(irq);
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} else if (pending & CAUSEF_IP3)
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do_IRQ(MIPS_CPU_IRQ_BASE + 3);
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else if (pending & CAUSEF_IP4)
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do_IRQ(MIPS_CPU_IRQ_BASE + 4);
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else if (pending & CAUSEF_IP5)
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do_IRQ(MIPS_CPU_IRQ_BASE + 5);
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else if (pending & CAUSEF_IP7)
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do_IRQ(MIPS_CPU_IRQ_BASE + 7);
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else
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spurious_interrupt();
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}
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static struct irqaction irq_via = {
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.handler = no_action,
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.mask = CPU_MASK_NONE,
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.name = "cascade"
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static struct irqaction cascade = {
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.handler = no_action,
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.mask = CPU_MASK_NONE,
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.name = "cascade",
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};
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void __init arch_init_irq(void)
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{
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/*
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* Mask all Galileo interrupts. The Galileo
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* handler is set in cobalt_timer_setup()
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*/
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GT_WRITE(GT_INTRMASK_OFS, 0);
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mips_cpu_irq_init();
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gt641xx_irq_init();
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init_i8259_irqs();
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init_i8259_irqs(); /* 0 ... 15 */
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mips_cpu_irq_init(); /* 16 ... 23 */
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/*
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* Mask all cpu interrupts
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* (except IE4, we already masked those at VIA level)
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*/
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change_c0_status(ST0_IM, IE_IRQ4);
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setup_irq(COBALT_VIA_IRQ, &irq_via);
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setup_irq(GT641XX_CASCADE_IRQ, &cascade);
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setup_irq(I8259_CASCADE_IRQ, &cascade);
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}
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@ -20,6 +20,7 @@
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/mc146818rtc.h>
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#include <linux/platform_device.h>
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static struct resource cobalt_rtc_resource[] __initdata = {
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@ -29,8 +30,8 @@ static struct resource cobalt_rtc_resource[] __initdata = {
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.flags = IORESOURCE_IO,
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},
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{
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.start = 8,
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.end = 8,
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.start = RTC_IRQ,
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.end = RTC_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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};
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@ -24,6 +24,7 @@
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#include <linux/serial_8250.h>
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#include <cobalt.h>
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#include <irq.h>
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static struct resource cobalt_uart_resource[] __initdata = {
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{
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@ -32,15 +33,15 @@ static struct resource cobalt_uart_resource[] __initdata = {
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.flags = IORESOURCE_MEM,
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},
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{
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.start = COBALT_SERIAL_IRQ,
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.end = COBALT_SERIAL_IRQ,
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.start = SERIAL_IRQ,
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.end = SERIAL_IRQ,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct plat_serial8250_port cobalt_serial8250_port[] = {
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{
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.irq = COBALT_SERIAL_IRQ,
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.irq = SERIAL_IRQ,
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.uartclk = 18432000,
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.iotype = UPIO_MEM,
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.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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@ -20,6 +20,7 @@
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#include <asm/gt64120.h>
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#include <cobalt.h>
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#include <irq.h>
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extern void cobalt_machine_restart(char *command);
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extern void cobalt_machine_halt(void);
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@ -45,14 +46,10 @@ void __init plat_timer_setup(struct irqaction *irq)
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/* Load timer value for HZ (TCLK is 50MHz) */
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GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
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/* Enable timer */
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/* Enable timer0 */
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GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
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/* Register interrupt */
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setup_irq(COBALT_GALILEO_IRQ, irq);
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/* Enable interrupt */
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GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
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setup_irq(GT641XX_TIMER0_IRQ, irq);
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}
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/*
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@ -51,6 +51,7 @@ obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
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obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o
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obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o
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obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o
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obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o
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obj-$(CONFIG_32BIT) += scall32-o32.o
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obj-$(CONFIG_64BIT) += scall64-64.o
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131
arch/mips/kernel/irq-gt641xx.c
Normal file
131
arch/mips/kernel/irq-gt641xx.c
Normal file
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@ -0,0 +1,131 @@
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/*
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* GT641xx IRQ routines.
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*
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* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/hardirq.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <asm/gt64120.h>
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#define GT641XX_IRQ_TO_BIT(irq) (1U << (irq - GT641XX_IRQ_BASE))
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static DEFINE_SPINLOCK(gt641xx_irq_lock);
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static void ack_gt641xx_irq(unsigned int irq)
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{
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unsigned long flags;
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u32 cause;
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spin_lock_irqsave(>641xx_irq_lock, flags);
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cause = GT_READ(GT_INTRCAUSE_OFS);
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cause &= ~GT641XX_IRQ_TO_BIT(irq);
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GT_WRITE(GT_INTRCAUSE_OFS, cause);
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spin_unlock_irqrestore(>641xx_irq_lock, flags);
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}
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static void mask_gt641xx_irq(unsigned int irq)
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{
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unsigned long flags;
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u32 mask;
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spin_lock_irqsave(>641xx_irq_lock, flags);
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mask = GT_READ(GT_INTRMASK_OFS);
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mask &= ~GT641XX_IRQ_TO_BIT(irq);
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GT_WRITE(GT_INTRMASK_OFS, mask);
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spin_unlock_irqrestore(>641xx_irq_lock, flags);
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}
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static void mask_ack_gt641xx_irq(unsigned int irq)
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{
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unsigned long flags;
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u32 cause, mask;
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spin_lock_irqsave(>641xx_irq_lock, flags);
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mask = GT_READ(GT_INTRMASK_OFS);
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mask &= ~GT641XX_IRQ_TO_BIT(irq);
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GT_WRITE(GT_INTRMASK_OFS, mask);
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cause = GT_READ(GT_INTRCAUSE_OFS);
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cause &= ~GT641XX_IRQ_TO_BIT(irq);
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GT_WRITE(GT_INTRCAUSE_OFS, cause);
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spin_unlock_irqrestore(>641xx_irq_lock, flags);
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}
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static void unmask_gt641xx_irq(unsigned int irq)
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{
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unsigned long flags;
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u32 mask;
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spin_lock_irqsave(>641xx_irq_lock, flags);
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mask = GT_READ(GT_INTRMASK_OFS);
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mask |= GT641XX_IRQ_TO_BIT(irq);
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GT_WRITE(GT_INTRMASK_OFS, mask);
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spin_unlock_irqrestore(>641xx_irq_lock, flags);
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}
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static struct irq_chip gt641xx_irq_chip = {
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.name = "GT641xx",
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.ack = ack_gt641xx_irq,
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.mask = mask_gt641xx_irq,
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.mask_ack = mask_ack_gt641xx_irq,
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.unmask = unmask_gt641xx_irq,
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};
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void gt641xx_irq_dispatch(void)
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{
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u32 cause, mask;
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int i;
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cause = GT_READ(GT_INTRCAUSE_OFS);
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mask = GT_READ(GT_INTRMASK_OFS);
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cause &= mask;
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/*
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* bit0 : logical or of all the interrupt bits.
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* bit30: logical or of bits[29:26,20:1].
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* bit31: logical or of bits[25:1].
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*/
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for (i = 1; i < 30; i++) {
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if (cause & (1U << i)) {
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do_IRQ(GT641XX_IRQ_BASE + i);
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return;
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}
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}
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atomic_inc(&irq_err_count);
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}
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void __init gt641xx_irq_init(void)
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{
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int i;
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GT_WRITE(GT_INTRMASK_OFS, 0);
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GT_WRITE(GT_INTRCAUSE_OFS, 0);
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/*
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* bit0 : logical or of all the interrupt bits.
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* bit30: logical or of bits[29:26,20:1].
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* bit31: logical or of bits[25:1].
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*/
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for (i = 1; i < 30; i++)
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set_irq_chip_and_handler(GT641XX_IRQ_BASE + i,
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>641xx_irq_chip, handle_level_irq);
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}
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@ -18,6 +18,7 @@
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#include <asm/gt64120.h>
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#include <cobalt.h>
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#include <irq.h>
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static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
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{
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@ -132,29 +133,29 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
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static char irq_tab_qube1[] __initdata = {
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[COBALT_PCICONF_CPU] = 0,
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[COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ,
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[COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
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[COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ,
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[COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
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[COBALT_PCICONF_VIA] = 0,
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[COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
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[COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
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[COBALT_PCICONF_ETH1] = 0
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};
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static char irq_tab_cobalt[] __initdata = {
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[COBALT_PCICONF_CPU] = 0,
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[COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ,
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[COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
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[COBALT_PCICONF_ETH0] = ETH0_IRQ,
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[COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
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[COBALT_PCICONF_VIA] = 0,
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[COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
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[COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ
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[COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
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[COBALT_PCICONF_ETH1] = ETH1_IRQ
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};
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static char irq_tab_raq2[] __initdata = {
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[COBALT_PCICONF_CPU] = 0,
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[COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ,
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[COBALT_PCICONF_RAQSCSI] = COBALT_RAQ_SCSI_IRQ,
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[COBALT_PCICONF_ETH0] = ETH0_IRQ,
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[COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
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[COBALT_PCICONF_VIA] = 0,
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[COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
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[COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ
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[COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
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[COBALT_PCICONF_ETH1] = ETH1_IRQ
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};
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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60
include/asm-mips/irq_gt641xx.h
Normal file
60
include/asm-mips/irq_gt641xx.h
Normal file
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@ -0,0 +1,60 @@
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/*
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* Galileo/Marvell GT641xx IRQ definitions.
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*
|
||||
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
#ifndef _ASM_IRQ_GT641XX_H
|
||||
#define _ASM_IRQ_GT641XX_H
|
||||
|
||||
#ifndef GT641XX_IRQ_BASE
|
||||
#define GT641XX_IRQ_BASE 8
|
||||
#endif
|
||||
|
||||
#define GT641XX_MEMORY_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 1)
|
||||
#define GT641XX_DMA_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 2)
|
||||
#define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ (GT641XX_IRQ_BASE + 3)
|
||||
#define GT641XX_DMA0_IRQ (GT641XX_IRQ_BASE + 4)
|
||||
#define GT641XX_DMA1_IRQ (GT641XX_IRQ_BASE + 5)
|
||||
#define GT641XX_DMA2_IRQ (GT641XX_IRQ_BASE + 6)
|
||||
#define GT641XX_DMA3_IRQ (GT641XX_IRQ_BASE + 7)
|
||||
#define GT641XX_TIMER0_IRQ (GT641XX_IRQ_BASE + 8)
|
||||
#define GT641XX_TIMER1_IRQ (GT641XX_IRQ_BASE + 9)
|
||||
#define GT641XX_TIMER2_IRQ (GT641XX_IRQ_BASE + 10)
|
||||
#define GT641XX_TIMER3_IRQ (GT641XX_IRQ_BASE + 11)
|
||||
#define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 12)
|
||||
#define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 13)
|
||||
#define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ (GT641XX_IRQ_BASE + 14)
|
||||
#define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ (GT641XX_IRQ_BASE + 15)
|
||||
#define GT641XX_PCI_0_ADDRESS_ERROR_IRQ (GT641XX_IRQ_BASE + 16)
|
||||
#define GT641XX_MEMORY_ERROR_IRQ (GT641XX_IRQ_BASE + 17)
|
||||
#define GT641XX_PCI_0_MASTER_ABORT_IRQ (GT641XX_IRQ_BASE + 18)
|
||||
#define GT641XX_PCI_0_TARGET_ABORT_IRQ (GT641XX_IRQ_BASE + 19)
|
||||
#define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ (GT641XX_IRQ_BASE + 20)
|
||||
#define GT641XX_CPU_INT0_IRQ (GT641XX_IRQ_BASE + 21)
|
||||
#define GT641XX_CPU_INT1_IRQ (GT641XX_IRQ_BASE + 22)
|
||||
#define GT641XX_CPU_INT2_IRQ (GT641XX_IRQ_BASE + 23)
|
||||
#define GT641XX_CPU_INT3_IRQ (GT641XX_IRQ_BASE + 24)
|
||||
#define GT641XX_CPU_INT4_IRQ (GT641XX_IRQ_BASE + 25)
|
||||
#define GT641XX_PCI_INT0_IRQ (GT641XX_IRQ_BASE + 26)
|
||||
#define GT641XX_PCI_INT1_IRQ (GT641XX_IRQ_BASE + 27)
|
||||
#define GT641XX_PCI_INT2_IRQ (GT641XX_IRQ_BASE + 28)
|
||||
#define GT641XX_PCI_INT3_IRQ (GT641XX_IRQ_BASE + 29)
|
||||
|
||||
extern void gt641xx_irq_dispatch(void);
|
||||
extern void gt641xx_irq_init(void);
|
||||
|
||||
#endif /* _ASM_IRQ_GT641XX_H */
|
||||
|
|
@ -12,32 +12,6 @@
|
|||
#ifndef __ASM_COBALT_H
|
||||
#define __ASM_COBALT_H
|
||||
|
||||
#include <irq.h>
|
||||
|
||||
/*
|
||||
* i8259 legacy interrupts used on Cobalt:
|
||||
*
|
||||
* 8 - RTC
|
||||
* 9 - PCI
|
||||
* 14 - IDE0
|
||||
* 15 - IDE1
|
||||
*/
|
||||
#define COBALT_QUBE_SLOT_IRQ 9
|
||||
|
||||
/*
|
||||
* CPU IRQs are 16 ... 23
|
||||
*/
|
||||
#define COBALT_CPU_IRQ MIPS_CPU_IRQ_BASE
|
||||
|
||||
#define COBALT_GALILEO_IRQ (COBALT_CPU_IRQ + 2)
|
||||
#define COBALT_RAQ_SCSI_IRQ (COBALT_CPU_IRQ + 3)
|
||||
#define COBALT_ETH0_IRQ (COBALT_CPU_IRQ + 3)
|
||||
#define COBALT_QUBE1_ETH0_IRQ (COBALT_CPU_IRQ + 4)
|
||||
#define COBALT_ETH1_IRQ (COBALT_CPU_IRQ + 4)
|
||||
#define COBALT_SERIAL_IRQ (COBALT_CPU_IRQ + 5)
|
||||
#define COBALT_SCSI_IRQ (COBALT_CPU_IRQ + 5)
|
||||
#define COBALT_VIA_IRQ (COBALT_CPU_IRQ + 6) /* Chained to VIA ISA bridge */
|
||||
|
||||
/*
|
||||
* PCI configuration space manifest constants. These are wired into
|
||||
* the board layout according to the PCI spec to enable the software
|
||||
|
|
|
|||
58
include/asm-mips/mach-cobalt/irq.h
Normal file
58
include/asm-mips/mach-cobalt/irq.h
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Cobalt IRQ definitions.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 1997 Cobalt Microserver
|
||||
* Copyright (C) 1997, 2003 Ralf Baechle
|
||||
* Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv)
|
||||
* Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
|
||||
*/
|
||||
#ifndef _ASM_COBALT_IRQ_H
|
||||
#define _ASM_COBALT_IRQ_H
|
||||
|
||||
/*
|
||||
* i8259 interrupts used on Cobalt:
|
||||
*
|
||||
* 8 - RTC
|
||||
* 9 - PCI slot
|
||||
* 14 - IDE0
|
||||
* 15 - IDE1(no connector on board)
|
||||
*/
|
||||
#define I8259A_IRQ_BASE 0
|
||||
|
||||
#define PCISLOT_IRQ (I8259A_IRQ_BASE + 9)
|
||||
|
||||
/*
|
||||
* CPU interrupts used on Cobalt:
|
||||
*
|
||||
* 0 - Software interrupt 0 (unused)
|
||||
* 1 - Software interrupt 0 (unused)
|
||||
* 2 - cascade GT64111
|
||||
* 3 - ethernet or SCSI host controller
|
||||
* 4 - ethernet
|
||||
* 5 - 16550 UART
|
||||
* 6 - cascade i8259
|
||||
* 7 - CP0 counter (unused)
|
||||
*/
|
||||
#define MIPS_CPU_IRQ_BASE 16
|
||||
|
||||
#define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)
|
||||
#define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3)
|
||||
#define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3)
|
||||
#define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4)
|
||||
#define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4)
|
||||
#define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5)
|
||||
#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5)
|
||||
#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)
|
||||
|
||||
|
||||
#define GT641XX_IRQ_BASE 24
|
||||
|
||||
#include <asm/irq_gt641xx.h>
|
||||
|
||||
#define NR_IRQS (GT641XX_PCI_INT3_IRQ + 1)
|
||||
|
||||
#endif /* _ASM_COBALT_IRQ_H */
|
||||
Loading…
Add table
Reference in a new issue