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drm/amdgpu/gfx10: set tcp harvest for navi14
Update settings for navi14. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 3 additions and 1 deletions
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@ -1485,6 +1485,7 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
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/*
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* GCRD_TARGETS_DISABLE field contains
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* for Navi10: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
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* for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
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*/
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u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
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2 * max_wgp_per_sh + /* TCP */
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@ -1493,6 +1494,7 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
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/*
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* UTCL1_UTCL0_INVREQ_DISABLE field contains
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* for Navi10: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
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* for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
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*/
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u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
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2 * max_wgp_per_sh + /* TCP */
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@ -1500,7 +1502,7 @@ static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
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4 + /* RMI */
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1); /* SQG */
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if (adev->asic_type == CHIP_NAVI10) {
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if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_NAVI14) {
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mutex_lock(&adev->grbm_idx_mutex);
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for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
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for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
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