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powerpc/32: Use SPRN_SPRG_SCRATCH2 in exception prologs

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Use SPRN_SPRG_SCRATCH2 as a third scratch register in
exception prologs in order to simplify them and avoid
data going back and forth from/to CR.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/6f5c8a7faa8cc54acb89c55c20aa579a2f30a4e9.1606285014.git.christophe.leroy@csgroup.eu
This commit is contained in:
Christophe Leroy 2020-11-25 07:10:53 +00:00 • committed by Michael Ellerman
parent de1cd07906
commit d2e0060360
1 changed files with 7 additions and 15 deletions
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22
arch/powerpc/kernel/head_32.h
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@ -40,7 +40,7 @@
.macro EXCEPTION_PROLOG_1 for_rtas=0 .macro EXCEPTION_PROLOG_1 for_rtas=0
#ifdef CONFIG_VMAP_STACK #ifdef CONFIG_VMAP_STACK
mr r11, r1 mtspr SPRN_SPRG_SCRATCH2,r1
subi r1, r1, INT_FRAME_SIZE /* use r1 if kernel */ subi r1, r1, INT_FRAME_SIZE /* use r1 if kernel */
beq 1f beq 1f
mfspr r1,SPRN_SPRG_THREAD mfspr r1,SPRN_SPRG_THREAD
@ -61,15 +61,10 @@
.macro EXCEPTION_PROLOG_2 handle_dar_dsisr=0 .macro EXCEPTION_PROLOG_2 handle_dar_dsisr=0
#ifdef CONFIG_VMAP_STACK #ifdef CONFIG_VMAP_STACK
mtcr r10 li r11, MSR_KERNEL & ~(MSR_IR | MSR_RI) /* can take DTLB miss */
li r10, MSR_KERNEL & ~(MSR_IR | MSR_RI) /* can take DTLB miss */ mtmsr r11
mtmsr r10
isync isync
#else mfspr r11, SPRN_SPRG_SCRATCH2
stw r10,_CCR(r11) /* save registers */
#endif
mfspr r10, SPRN_SPRG_SCRATCH0
#ifdef CONFIG_VMAP_STACK
stw r11,GPR1(r1) stw r11,GPR1(r1)
stw r11,0(r1) stw r11,0(r1)
mr r11, r1 mr r11, r1
@ -78,14 +73,12 @@
stw r1,0(r11) stw r1,0(r11)
tovirt(r1, r11) /* set new kernel sp */ tovirt(r1, r11) /* set new kernel sp */
#endif #endif
stw r10,_CCR(r11) /* save registers */
stw r12,GPR12(r11) stw r12,GPR12(r11)
stw r9,GPR9(r11) stw r9,GPR9(r11)
stw r10,GPR10(r11) mfspr r10,SPRN_SPRG_SCRATCH0
#ifdef CONFIG_VMAP_STACK
mfcr r10
stw r10, _CCR(r11)
#endif
mfspr r12,SPRN_SPRG_SCRATCH1 mfspr r12,SPRN_SPRG_SCRATCH1
stw r10,GPR10(r11)
stw r12,GPR11(r11) stw r12,GPR11(r11)
mflr r10 mflr r10
stw r10,_LINK(r11) stw r10,_LINK(r11)
@ -99,7 +92,6 @@
stw r10, _DSISR(r11) stw r10, _DSISR(r11)
.endif .endif
lwz r9, SRR1(r12) lwz r9, SRR1(r12)
andi. r10, r9, MSR_PR
lwz r12, SRR0(r12) lwz r12, SRR0(r12)
#else #else
mfspr r12,SPRN_SRR0 mfspr r12,SPRN_SRR0