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drm/nouveau/sec2: switch to instanced constructor

Browse source 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2020-12-04 16:11:29 +10:00
parent 400c2a456c
commit d1866250a2
10 changed files with 27 additions and 27 deletions
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2
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View file

@ -60,7 +60,6 @@ struct nvkm_device {
struct notifier_block nb; struct notifier_block nb;
} acpi; } acpi;
struct nvkm_sec2 *sec2;
struct nvkm_sw *sw; struct nvkm_sw *sw;
struct nvkm_engine *vic; struct nvkm_engine *vic;
@ -104,7 +103,6 @@ struct nvkm_device_chip {
#undef NVKM_LAYOUT_INST #undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE #undef NVKM_LAYOUT_ONCE
int (*sec2 )(struct nvkm_device *, int idx, struct nvkm_sec2 **);
int (*sw )(struct nvkm_device *, int idx, struct nvkm_sw **); int (*sw )(struct nvkm_device *, int idx, struct nvkm_sw **);
int (*vic )(struct nvkm_device *, int idx, struct nvkm_engine **); int (*vic )(struct nvkm_device *, int idx, struct nvkm_engine **);
}; };

1
drivers/gpu/drm/nouveau/include/nvkm/core/layout.h
View file

@ -43,4 +43,5 @@ NVKM_LAYOUT_INST(NVKM_ENGINE_NVDEC , struct nvkm_nvdec , nvdec, 3)
NVKM_LAYOUT_INST(NVKM_ENGINE_NVENC , struct nvkm_nvenc , nvenc, 3) NVKM_LAYOUT_INST(NVKM_ENGINE_NVENC , struct nvkm_nvenc , nvenc, 3)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_PM , struct nvkm_pm , pm) NVKM_LAYOUT_ONCE(NVKM_ENGINE_PM , struct nvkm_pm , pm)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_SEC , struct nvkm_engine , sec) NVKM_LAYOUT_ONCE(NVKM_ENGINE_SEC , struct nvkm_engine , sec)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_SEC2 , struct nvkm_sec2 , sec2)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_VP , struct nvkm_engine , vp) NVKM_LAYOUT_ONCE(NVKM_ENGINE_VP , struct nvkm_engine , vp)

6
drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h
View file

@ -18,7 +18,7 @@ struct nvkm_sec2 {
bool initmsg_received; bool initmsg_received;
}; };
int gp102_sec2_new(struct nvkm_device *, int, struct nvkm_sec2 **); int gp102_sec2_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sec2 **);
int gp108_sec2_new(struct nvkm_device *, int, struct nvkm_sec2 **); int gp108_sec2_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sec2 **);
int tu102_sec2_new(struct nvkm_device *, int, struct nvkm_sec2 **); int tu102_sec2_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sec2 **);
#endif #endif

1
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View file

@ -33,7 +33,6 @@ nvkm_subdev_type[NVKM_SUBDEV_NR] = {
#include <core/layout.h> #include <core/layout.h>
#undef NVKM_LAYOUT_ONCE #undef NVKM_LAYOUT_ONCE
#undef NVKM_LAYOUT_INST #undef NVKM_LAYOUT_INST
[NVKM_ENGINE_SEC2 ] = "sec2",
[NVKM_ENGINE_SW ] = "sw", [NVKM_ENGINE_SW ] = "sw",
[NVKM_ENGINE_VIC ] = "vic", [NVKM_ENGINE_VIC ] = "vic",
}; };

23
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View file

@ -2199,7 +2199,7 @@ nv132_chipset = {
.gr = { 0x00000001, gp102_gr_new }, .gr = { 0x00000001, gp102_gr_new },
.nvdec = { 0x00000001, gm107_nvdec_new }, .nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc = { 0x00000003, gm107_nvenc_new }, .nvenc = { 0x00000003, gm107_nvenc_new },
.sec2 = gp102_sec2_new, .sec2 = { 0x00000001, gp102_sec2_new },
.sw = gf100_sw_new, .sw = gf100_sw_new,
}; };
@ -2233,7 +2233,7 @@ nv134_chipset = {
.gr = { 0x00000001, gp104_gr_new }, .gr = { 0x00000001, gp104_gr_new },
.nvdec = { 0x00000001, gm107_nvdec_new }, .nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc = { 0x00000003, gm107_nvenc_new }, .nvenc = { 0x00000003, gm107_nvenc_new },
.sec2 = gp102_sec2_new, .sec2 = { 0x00000001, gp102_sec2_new },
.sw = gf100_sw_new, .sw = gf100_sw_new,
}; };
@ -2267,7 +2267,7 @@ nv136_chipset = {
.gr = { 0x00000001, gp104_gr_new }, .gr = { 0x00000001, gp104_gr_new },
.nvdec = { 0x00000001, gm107_nvdec_new }, .nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc = { 0x00000001, gm107_nvenc_new }, .nvenc = { 0x00000001, gm107_nvenc_new },
.sec2 = gp102_sec2_new, .sec2 = { 0x00000001, gp102_sec2_new },
.sw = gf100_sw_new, .sw = gf100_sw_new,
}; };
@ -2301,7 +2301,7 @@ nv137_chipset = {
.gr = { 0x00000001, gp107_gr_new }, .gr = { 0x00000001, gp107_gr_new },
.nvdec = { 0x00000001, gm107_nvdec_new }, .nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc = { 0x00000003, gm107_nvenc_new }, .nvenc = { 0x00000003, gm107_nvenc_new },
.sec2 = gp102_sec2_new, .sec2 = { 0x00000001, gp102_sec2_new },
.sw = gf100_sw_new, .sw = gf100_sw_new,
}; };
@ -2334,7 +2334,7 @@ nv138_chipset = {
.fifo = { 0x00000001, gp100_fifo_new }, .fifo = { 0x00000001, gp100_fifo_new },
.gr = { 0x00000001, gp108_gr_new }, .gr = { 0x00000001, gp108_gr_new },
.nvdec = { 0x00000001, gm107_nvdec_new }, .nvdec = { 0x00000001, gm107_nvdec_new },
.sec2 = gp108_sec2_new, .sec2 = { 0x00000001, gp108_sec2_new },
.sw = gf100_sw_new, .sw = gf100_sw_new,
}; };
@ -2393,7 +2393,7 @@ nv140_chipset = {
.gr = { 0x00000001, gv100_gr_new }, .gr = { 0x00000001, gv100_gr_new },
.nvdec = { 0x00000001, gm107_nvdec_new }, .nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc = { 0x00000007, gm107_nvenc_new }, .nvenc = { 0x00000007, gm107_nvenc_new },
.sec2 = gp108_sec2_new, .sec2 = { 0x00000001, gp108_sec2_new },
}; };
static const struct nvkm_device_chip static const struct nvkm_device_chip
@ -2427,7 +2427,7 @@ nv162_chipset = {
.gr = { 0x00000001, tu102_gr_new }, .gr = { 0x00000001, tu102_gr_new },
.nvdec = { 0x00000001, gm107_nvdec_new }, .nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc = { 0x00000001, gm107_nvenc_new }, .nvenc = { 0x00000001, gm107_nvenc_new },
.sec2 = tu102_sec2_new, .sec2 = { 0x00000001, tu102_sec2_new },
}; };
static const struct nvkm_device_chip static const struct nvkm_device_chip
@ -2461,7 +2461,7 @@ nv164_chipset = {
.gr = { 0x00000001, tu102_gr_new }, .gr = { 0x00000001, tu102_gr_new },
.nvdec = { 0x00000003, gm107_nvdec_new }, .nvdec = { 0x00000003, gm107_nvdec_new },
.nvenc = { 0x00000001, gm107_nvenc_new }, .nvenc = { 0x00000001, gm107_nvenc_new },
.sec2 = tu102_sec2_new, .sec2 = { 0x00000001, tu102_sec2_new },
}; };
static const struct nvkm_device_chip static const struct nvkm_device_chip
@ -2495,7 +2495,7 @@ nv166_chipset = {
.gr = { 0x00000001, tu102_gr_new }, .gr = { 0x00000001, tu102_gr_new },
.nvdec = { 0x00000007, gm107_nvdec_new }, .nvdec = { 0x00000007, gm107_nvdec_new },
.nvenc = { 0x00000001, gm107_nvenc_new }, .nvenc = { 0x00000001, gm107_nvenc_new },
.sec2 = tu102_sec2_new, .sec2 = { 0x00000001, tu102_sec2_new },
}; };
static const struct nvkm_device_chip static const struct nvkm_device_chip
@ -2529,7 +2529,7 @@ nv167_chipset = {
.gr = { 0x00000001, tu102_gr_new }, .gr = { 0x00000001, tu102_gr_new },
.nvdec = { 0x00000001, gm107_nvdec_new }, .nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc = { 0x00000001, gm107_nvenc_new }, .nvenc = { 0x00000001, gm107_nvenc_new },
.sec2 = tu102_sec2_new, .sec2 = { 0x00000001, tu102_sec2_new },
}; };
static const struct nvkm_device_chip static const struct nvkm_device_chip
@ -2563,7 +2563,7 @@ nv168_chipset = {
.gr = { 0x00000001, tu102_gr_new }, .gr = { 0x00000001, tu102_gr_new },
.nvdec = { 0x00000001, gm107_nvdec_new }, .nvdec = { 0x00000001, gm107_nvdec_new },
.nvenc = { 0x00000001, gm107_nvenc_new }, .nvenc = { 0x00000001, gm107_nvenc_new },
.sec2 = tu102_sec2_new, .sec2 = { 0x00000001, tu102_sec2_new },
}; };
static const struct nvkm_device_chip static const struct nvkm_device_chip
@ -3162,7 +3162,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
#include <core/layout.h> #include <core/layout.h>
#undef NVKM_LAYOUT_INST #undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE #undef NVKM_LAYOUT_ONCE
_(NVKM_ENGINE_SEC2 , sec2);
_(NVKM_ENGINE_SW , sw); _(NVKM_ENGINE_SW , sw);
_(NVKM_ENGINE_VIC , vic); _(NVKM_ENGINE_VIC , vic);
case NVKM_ENGINE_CE1: case NVKM_ENGINE_CE1:

4
drivers/gpu/drm/nouveau/nvkm/engine/sec2/base.c
View file

@ -85,7 +85,7 @@ nvkm_sec2 = {
int int
nvkm_sec2_new_(const struct nvkm_sec2_fwif *fwif, struct nvkm_device *device, nvkm_sec2_new_(const struct nvkm_sec2_fwif *fwif, struct nvkm_device *device,
int index, u32 addr, struct nvkm_sec2 **psec2) enum nvkm_subdev_type type, int inst, u32 addr, struct nvkm_sec2 **psec2)
{ {
struct nvkm_sec2 *sec2; struct nvkm_sec2 *sec2;
int ret; int ret;
@ -93,7 +93,7 @@ nvkm_sec2_new_(const struct nvkm_sec2_fwif *fwif, struct nvkm_device *device,
if (!(sec2 = *psec2 = kzalloc(sizeof(*sec2), GFP_KERNEL))) if (!(sec2 = *psec2 = kzalloc(sizeof(*sec2), GFP_KERNEL)))
return -ENOMEM; return -ENOMEM;
ret = nvkm_engine_ctor(&nvkm_sec2, device, index, true, &sec2->engine); ret = nvkm_engine_ctor(&nvkm_sec2, device, type, inst, true, &sec2->engine);
if (ret) if (ret)
return ret; return ret;

5
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp102.c
View file

@ -343,7 +343,8 @@ gp102_sec2_fwif[] = {
}; };
int int
gp102_sec2_new(struct nvkm_device *device, int index, struct nvkm_sec2 **psec2) gp102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_sec2 **psec2)
{ {
return nvkm_sec2_new_(gp102_sec2_fwif, device, index, 0, psec2); return nvkm_sec2_new_(gp102_sec2_fwif, device, type, inst, 0, psec2);
} }

5
drivers/gpu/drm/nouveau/nvkm/engine/sec2/gp108.c
View file

@ -36,7 +36,8 @@ gp108_sec2_fwif[] = {
}; };
int int
gp108_sec2_new(struct nvkm_device *device, int index, struct nvkm_sec2 **psec2) gp108_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_sec2 **psec2)
{ {
return nvkm_sec2_new_(gp108_sec2_fwif, device, index, 0, psec2); return nvkm_sec2_new_(gp108_sec2_fwif, device, type, inst, 0, psec2);
} }

2
drivers/gpu/drm/nouveau/nvkm/engine/sec2/priv.h
View file

@ -25,6 +25,6 @@ int gp102_sec2_load(struct nvkm_sec2 *, int, const struct nvkm_sec2_fwif *);
extern const struct nvkm_sec2_func gp102_sec2; extern const struct nvkm_sec2_func gp102_sec2;
extern const struct nvkm_acr_lsf_func gp102_sec2_acr_1; extern const struct nvkm_acr_lsf_func gp102_sec2_acr_1;
int nvkm_sec2_new_(const struct nvkm_sec2_fwif *, struct nvkm_device *, int nvkm_sec2_new_(const struct nvkm_sec2_fwif *, struct nvkm_device *, enum nvkm_subdev_type,
int, u32 addr, struct nvkm_sec2 **); int, u32 addr, struct nvkm_sec2 **);
#endif #endif

5
drivers/gpu/drm/nouveau/nvkm/engine/sec2/tu102.c
View file

@ -72,10 +72,11 @@ tu102_sec2_fwif[] = {
}; };
int int
tu102_sec2_new(struct nvkm_device *device, int index, struct nvkm_sec2 **psec2) tu102_sec2_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_sec2 **psec2)
{ {
/* TOP info wasn't updated on Turing to reflect the PRI /* TOP info wasn't updated on Turing to reflect the PRI
* address change for some reason. We override it here. * address change for some reason. We override it here.
*/ */
return nvkm_sec2_new_(tu102_sec2_fwif, device, index, 0x840000, psec2); return nvkm_sec2_new_(tu102_sec2_fwif, device, type, inst, 0x840000, psec2);
} }