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This is the big bulk of pin control changes for the v4.14 kernel:

Browse source 
Core changes:
 - Decision to wrap the sleep mode of the Spreadtrum and in the future
   others into a specially tagged state. The generic DT bindings and the
   new Spreadtrum driver conforms to this. Others should be moved over
   if possible.
 
 New drivers:
 - New driver for Spreadtrum SoCs especially the SC9860 SoC.
 - New driver for Storlink/Cortina Gemini 3512 and 3516 SoCs.
 
 New subdrivers:
 - Intel Denverton subdriver.
 - Intel Cannon Lake subdriver.
 - Intel Lewisburg subdriver.
 - Allwinner sunxi: R40 subdriver for A10.
 - Socionext uniphier PXs3 subdriver.
 - Rockchip RK3128 subdriver.
 - Renesas SH-PFC R8A77995 subdriver.
 
 Miscellaneous:
 - Qualcomm APQ8064 can handle general purpose clock muxing.
 - Mediatek MT7623 PCIe mux data fixed up.
 - Intel GPIO IRQs are disabled during suspend.
 - Several fixes and addtions to Renesas r8a7796.
 - Qualcomm SPMI GPIO supports dtest route and LV/MV subtype.
 - Input schmitt trigger support in Rockchip RV1108.
 - Aspeed G4 and G5 USB host/device pin control control added.
 - Qualcomm IPQ4019 has matured with a few missing pin groups and
   control bits put in place.
 - Lots of constification, this is the latest in cocinelle fixes.
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Merge tag 'pinctrl-v4.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the big bulk of pin control changes for the v4.14 kernel.
  There are just a few bigger changes (new drivers mostly) and then a
  lot of small patches all over the place.

  Core changes:
   - Decision to wrap the sleep mode of the Spreadtrum and in the future
     others into a specially tagged state. The generic DT bindings and
     the new Spreadtrum driver conforms to this. Others should be moved
     over if possible.

  New drivers:
   - Spreadtrum SoCs especially the SC9860 SoC.
   - Storlink/Cortina Gemini 3512 and 3516 SoCs.

  New subdrivers:
   - Intel Denverton subdriver.
   - Intel Cannon Lake subdriver.
   - Intel Lewisburg subdriver.
   - Allwinner sunxi: R40 subdriver for A10.
   - Socionext uniphier PXs3 subdriver.
   - Rockchip RK3128 subdriver.
   - Renesas SH-PFC R8A77995 subdriver.

  Miscellaneous:
   - Qualcomm APQ8064 can handle general purpose clock muxing.
   - Mediatek MT7623 PCIe mux data fixed up.
   - Intel GPIO IRQs are disabled during suspend.
   - Several fixes and addtions to Renesas r8a7796.
   - Qualcomm SPMI GPIO supports dtest route and LV/MV subtype.
   - Input schmitt trigger support in Rockchip RV1108.
   - Aspeed G4 and G5 USB host/device pin control control added.
   - Qualcomm IPQ4019 has matured with a few missing pin groups and
     control bits put in place.
   - Lots of constification, this is the latest in cocinelle fixes"

* tag 'pinctrl-v4.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (147 commits)
  Revert "pinctrl: sunxi: Don't enforce bias disable (for now)"
  pinctrl: uniphier: fix members of rmii group for Pro4
  pinctrl: Delete an error message
  pinctrl: core: Delete an error message
  pinctrl: intel: Read back TX buffer state
  pinctrl: rockchip: Add rv1108 recalculated iomux support
  pinctrl: intel: Decrease indentation in intel_gpio_set()
  pinctrl: rza1: Remove suffix from gpiochip label
  pinctrl: qcom: spmi-gpio: Correct power_source range check
  pinctrl: freescale: make mxs_regs const
  pinctrl: aspeed: Rework strap register write logic for the AST2500
  pinctrl: rza1: off by one in rza1_parse_gpiochip()
  pinctrl: qcom: General Purpose clocks for apq8064
  pinctrl: sprd: Add Spreadtrum pin control driver
  dt-bindings: pinctrl: Add DT bindings for Spreadtrum SC9860
  pinctrl: Add sleep related state to indicate sleep related configs
  pinctrl: mediatek: update PCIe mux data for MT7623
  pinctrl: intel: Add Intel Lewisburg GPIO support
  pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support
  pinctrl: aspeed: Fix ast2500 strap register write logic
  ...
This commit is contained in:
Linus Torvalds 2017-09-05 11:45:33 -07:00
commit d16605c912
124 changed files with 13257 additions and 3901 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

59
Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt Normal file
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@ -0,0 +1,59 @@
Cortina Systems Gemini pin controller
This pin controller is found in the Cortina Systems Gemini SoC family,
see further arm/gemini.txt. It is a purely group-based multiplexing pin
controller.
The pin controller node must be a subnode of the system controller node.
Required properties:
- compatible: "cortina,gemini-pinctrl"
Subnodes of the pin controller contain pin control multiplexing set-up.
Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes.
Example:
syscon {
compatible = "cortina,gemini-syscon";
...
pinctrl {
compatible = "cortina,gemini-pinctrl";
pinctrl-names = "default";
pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
<&vcontrol_default_pins>;
dram_default_pins: pinctrl-dram {
mux {
function = "dram";
groups = "dramgrp";
};
};
rtc_default_pins: pinctrl-rtc {
mux {
function = "rtc";
groups = "rtcgrp";
};
};
power_default_pins: pinctrl-power {
mux {
function = "power";
groups = "powergrp";
};
};
system_default_pins: pinctrl-system {
mux {
function = "system";
groups = "systemgrp";
};
};
(...)
uart_default_pins: pinctrl-uart {
mux {
function = "uart";
groups = "uartrxtxgrp";
};
};
};
};

61
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt Normal file
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@ -0,0 +1,61 @@
* Freescale i.MX7ULP IOMUX Controller
i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
ports and IOMUXC DDR for DDR interface.
Note:
This binding doc is only for the IOMUXC1 support in A7 Domain and it only
supports generic pin config.
Please also refer pinctrl-bindings.txt in this directory for generic pinctrl
binding.
=== Pin Controller Node ===
Required properties:
- compatible: "fsl,imx7ulp-iomuxc1"
- reg: Should contain the base physical address and size of the iomuxc
registers.
=== Pin Configuration Node ===
- pinmux: One integers array, represents a group of pins mux setting.
The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
a specific function.
NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
and config register as follows:
<mux_conf_reg input_reg mux_mode input_val>
Refer to imx7ulp-pinfunc.h in in device tree source folder for all
available imx7ulp PIN_FUNC_ID.
Optional Properties:
- drive-strength Integer. Controls Drive Strength
0: Standard
1: Hi Driver
- drive-push-pull Bool. Enable Pin Push-pull
- drive-open-drain Bool. Enable Pin Open-drian
- slew-rate: Integer. Controls Slew Rate
0: Standard
1: Slow
- bias-disable: Bool. Pull disabled
- bias-pull-down: Bool. Pull down on pin
- bias-pull-up: Bool. Pull up on pin
Examples:
#include "imx7ulp-pinfunc.h"
/* Pin Controller Node */
iomuxc1: iomuxc@40ac0000 {
compatible = "fsl,imx7ulp-iomuxc1";
reg = <0x40ac0000 0x1000>;
/* Pin Configuration Node */
pinctrl_lpuart4: lpuart4grp {
pinmux = <
IMX7ULP_PAD_PTC3__LPUART4_RX
IMX7ULP_PAD_PTC2__LPUART4_TX
>;
bias-pull-up;
};
};

8
Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
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@ -69,8 +69,9 @@ PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS
VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2
TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USB11D1 USB11H2 USB2D1
USB2H1 USBCKI VGABIOS_ROM VGAHS VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1
WDTRST2
aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
@ -86,7 +87,8 @@ SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9
SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ
SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0
SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2
TXD3 TXD4 UART6 USBCKI VGABIOSROM VGAHS VGAVS VPI24 VPO WDTRST1 WDTRST2
TXD3 TXD4 UART6 USB11BHID USB2AD USB2AH USB2BD USB2BH USBCKI VGABIOSROM VGAHS
VGAVS VPI24 VPO WDTRST1 WDTRST2
Examples
========

2
Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
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@ -268,6 +268,8 @@ output-enable - enable output on a pin without actively driving it
(such as enabling an output buffer)
output-low - set the pin to output mode with low level
output-high - set the pin to output mode with high level
sleep-hardware-state - indicate this is sleep related state which will be programmed
into the registers for the sleep state.
slew-rate - set the slew rate
For example:

1
Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
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@ -5,6 +5,7 @@ The Mediatek's Pin controller is used to control SoC pins.
Required properties:
- compatible: value should be one of the following.
"mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
"mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.
"mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
"mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.

3
Documentation/devicetree/bindings/pinctrl/qcom,apq8064-pinctrl.txt
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@ -46,7 +46,8 @@ Valid values for pins are:
gpio0-gpio89
Valid values for function are:
cam_mclk, codec_mic_i2s, codec_spkr_i2s, gpio, gsbi1, gsbi2, gsbi3, gsbi4,
cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a, gp_clk_0b, gp_clk_1a,
gp_clk_1b, gp_clk_2a, gp_clk_2b, gpio, gsbi1, gsbi2, gsbi3, gsbi4,
gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6,
gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1,
gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm,

6
Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.txt
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@ -50,7 +50,11 @@ Valid values for qcom,pins are:
Supports mux, bias and drive-strength
Valid values for qcom,function are:
gpio, blsp_uart1, blsp_i2c0, blsp_i2c1, blsp_uart0, blsp_spi1, blsp_spi0
aud_pin, audio_pwm, blsp_i2c0, blsp_i2c1, blsp_spi0, blsp_spi1, blsp_uart0,
blsp_uart1, chip_rst, gpio, i2s_rx, i2s_spdif_in, i2s_spdif_out, i2s_td, i2s_tx,
jtag, led0, led1, led2, led3, led4, led5, led6, led7, led8, led9, led10, led11,
mdc, mdio, pcie, pmu, prng_rosc, qpic, rgmii, rmii, sdio, smart0, smart1,
smart2, smart3, tm, wifi0, wifi1
Example:

26
Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
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@ -16,6 +16,7 @@ PMIC's from Qualcomm.
"qcom,pm8941-gpio"
"qcom,pm8994-gpio"
"qcom,pma8084-gpio"
"qcom,pmi8994-gpio"
And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio"
if the device is on an spmi bus or an ssbi bus respectively
@ -85,6 +86,7 @@ to specify in a pin configuration subnode:
gpio1-gpio36 for pm8941
gpio1-gpio22 for pm8994
gpio1-gpio22 for pma8084
gpio1-gpio10 for pmi8994
- function:
Usage: required
@ -98,7 +100,10 @@ to specify in a pin configuration subnode:
"dtest1",
"dtest2",
"dtest3",
"dtest4"
"dtest4",
And following values are supported by LV/MV GPIO subtypes:
"func3",
"func4"
- bias-disable:
Usage: optional
@ -183,6 +188,25 @@ to specify in a pin configuration subnode:
Value type: <none>
Definition: The specified pins are configured in open-source mode.
- qcom,analog-pass:
Usage: optional
Value type: <none>
Definition: The specified pins are configured in analog-pass-through mode.
- qcom,atest:
Usage: optional
Value type: <u32>
Definition: Selects ATEST rail to route to GPIO when it's configured
in analog-pass-through mode.
Valid values are 1-4 corresponding to ATEST1 to ATEST4.
- qcom,dtest-buffer:
Usage: optional
Value type: <u32>
Definition: Selects DTEST rail to route to GPIO when it's configured
as digital input.
Valid values are 1-4 corresponding to DTEST1 to DTEST4.
Example:
pm8921_gpio: gpio@150 {

1
Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt
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@ -24,6 +24,7 @@ Required Properties:
- "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller.
- "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller.
- "renesas,pfc-r8a7796": for R8A7796 (R-Car M3-W) compatible pin-controller.
- "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller.
- "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller.
- reg: Base address and length of each memory resource used by the pin

1
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
View file

@ -24,6 +24,7 @@ Required properties for iomux controller:
"rockchip,rk2928-pinctrl": for Rockchip RK2928
"rockchip,rk3066a-pinctrl": for Rockchip RK3066a
"rockchip,rk3066b-pinctrl": for Rockchip RK3066b
"rockchip,rk3128-pinctrl": for Rockchip RK3128
"rockchip,rk3188-pinctrl": for Rockchip RK3188
"rockchip,rk3228-pinctrl": for Rockchip RK3228
"rockchip,rk3288-pinctrl": for Rockchip RK3288

83
Documentation/devicetree/bindings/pinctrl/sprd,pinctrl.txt Normal file
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@ -0,0 +1,83 @@
* Spreadtrum Pin Controller
The Spreadtrum pin controller are organized in 3 blocks (types).
The first block comprises some global control registers, and each
register contains several bit fields with one bit or several bits
to configure for some global common configuration, such as domain
pad driving level, system control select and so on ("domain pad
driving level": One pin can output 3.0v or 1.8v, depending on the
related domain pad driving selection, if the related domain pad
slect 3.0v, then the pin can output 3.0v. "system control" is used
to choose one function (like: UART0) for which system, since we
have several systems (AP/CP/CM4) on one SoC.).
There are too much various configuration that we can not list all
of them, so we can not make every Spreadtrum-special configuration
as one generic configuration, and maybe it will add more strange
global configuration in future. Then we add one "sprd,control" to
set these various global control configuration, and we need use
magic number for this property.
Moreover we recognise every fields comprising one bit or several
bits in one global control register as one pin, thus we should
record every pin's bit offset, bit width and register offset to
configure this field (pin).
The second block comprises some common registers which have unified
register definition, and each register described one pin is used
to configure the pin sleep mode, function select and sleep related
configuration.
Now we have 4 systems for sleep mode on SC9860 SoC: AP system,
PUBCP system, TGLDSP system and AGDSP system. And the pin sleep
related configuration are:
- input-enable
- input-disable
- output-high
- output-low
- bias-pull-up
- bias-pull-down
In some situation we need set the pin sleep mode and pin sleep related
configuration, to set the pin sleep related configuration automatically
by hardware when the system specified by sleep mode goes into deep
sleep mode. For example, if we set the pin sleep mode as PUBCP_SLEEP
and set the pin sleep related configuration as "input-enable", which
means when PUBCP system goes into deep sleep mode, this pin will be set
input enable automatically.
Moreover we can not use the "sleep" state, since some systems (like:
PUBCP system) do not run linux kernel OS (only AP system run linux
kernel on SC9860 platform), then we can not select "sleep" state
when the PUBCP system goes into deep sleep mode. Thus we introduce
"sprd,sleep-mode" property to set pin sleep mode.
The last block comprises some misc registers which also have unified
register definition, and each register described one pin is used to
configure drive strength, pull up/down and so on. Especially for pull
up, we have two kind pull up resistor: 20K and 4.7K.
Required properties for Spreadtrum pin controller:
- compatible: "sprd,<soc>-pinctrl"
Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported SoCs.
- reg: The register address of pin controller device.
- pins : An array of pin names.
Optional properties:
- function: Specified the function name.
- drive-strength: Drive strength in mA.
- input-schmitt-disable: Enable schmitt-trigger mode.
- input-schmitt-enable: Disable schmitt-trigger mode.
- bias-disable: Disable pin bias.
- bias-pull-down: Pull down on pin.
- bias-pull-up: Pull up on pin.
- input-enable: Enable pin input.
- input-disable: Enable pin output.
- output-high: Set the pin as an output level high.
- output-low: Set the pin as an output level low.
- sleep-hardware-state: Indicate these configs in this state are sleep related.
- sprd,control: Control values referring to databook for global control pins.
- sprd,sleep-mode: Sleep mode selection.
Please refer to each sprd,<soc>-pinctrl.txt binding doc for supported values.

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@ -0,0 +1,70 @@
* Spreadtrum SC9860 Pin Controller
Please refer to sprd,pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: Must be "sprd,sc9860-pinctrl".
- reg: The register address of pin controller device.
- pins : An array of strings, each string containing the name of a pin.
Optional properties:
- function: A string containing the name of the function, values must be
one of: "func1", "func2", "func3" and "func4".
- drive-strength: Drive strength in mA. Supported values: 2, 4, 6, 8, 10,
12, 14, 16, 20, 21, 24, 25, 27, 29, 31 and 33.
- input-schmitt-disable: Enable schmitt-trigger mode.
- input-schmitt-enable: Disable schmitt-trigger mode.
- bias-disable: Disable pin bias.
- bias-pull-down: Pull down on pin.
- bias-pull-up: Pull up on pin. Supported values: 20000 for pull-up resistor
is 20K and 4700 for pull-up resistor is 4.7K.
- input-enable: Enable pin input.
- input-disable: Enable pin output.
- output-high: Set the pin as an output level high.
- output-low: Set the pin as an output level low.
- sleep-hardware-state: Indicate these configs in this state are sleep related.
- sprd,control: Control values referring to databook for global control pins.
- sprd,sleep-mode: Choose the pin sleep mode, and supported values are:
AP_SLEEP, PUBCP_SLEEP, TGLDSP_SLEEP and AGDSP_SLEEP.
Pin sleep mode definition:
enum pin_sleep_mode {
AP_SLEEP = BIT(0),
PUBCP_SLEEP = BIT(1),
TGLDSP_SLEEP = BIT(2),
AGDSP_SLEEP = BIT(3),
};
Example:
pin_controller: pinctrl@402a0000 {
compatible = "sprd,sc9860-pinctrl";
reg = <0x402a0000 0x10000>;
grp1: sd0 {
pins = "SC9860_VIO_SD2_IRTE", "SC9860_VIO_SD0_IRTE";
sprd,control = <0x1>;
};
grp2: rfctl_33 {
pins = "SC9860_RFCTL33";
function = "func2";
sprd,sleep-mode = <AP_SLEEP | PUBCP_SLEEP>;
grp2_sleep_mode: rfctl_33_sleep {
pins = "SC9860_RFCTL33";
sleep-hardware-state;
output-low;
}
};
grp3: rfctl_misc_20 {
pins = "SC9860_RFCTL20_MISC";
drive-strength = <10>;
bias-pull-up = <4700>;
grp3_sleep_mode: rfctl_misc_sleep {
pins = "SC9860_RFCTL20_MISC";
sleep-hardware-state;
bias-pull-up;
}
};
};

5
MAINTAINERS
View file

@ -1282,10 +1282,15 @@ S: Maintained
ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE
M: Hans Ulli Kroll <ulli.kroll@googlemail.com>
M: Linus Walleij <linus.walleij@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
T: git git://github.com/ulli-kroll/linux.git
S: Maintained
F: Documentation/devicetree/bindings/arm/gemini.txt
F: Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt
F: Documentation/devicetree/bindings/rtc/faraday,ftrtc010.txt
F: arch/arm/mach-gemini/
F: drivers/pinctrl/pinctrl-gemini.c
F: drivers/rtc/rtc-ftrtc010.c
ARM/CSR SIRFPRIMA2 MACHINE SUPPORT

468
arch/arm/boot/dts/imx7ulp-pinfunc.h Normal file
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@ -0,0 +1,468 @@
/*
* Copyright 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_IMX7ULP_PINFUNC_H
#define __DTS_IMX7ULP_PINFUNC_H
/*
* The pin function ID is a tuple of
* <mux_conf_reg input_reg mux_mode input_val>
*/
#define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
#define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
#define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
#define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
#define IMX7ULP_PAD_PTC1__TPM4_CH0 0x0004 0x0280 0x6 0x1
#define IMX7ULP_PAD_PTC1__FB_AD1 0x0004 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC2__PTC2 0x0008 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC2__TRACE_D13 0x0008 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC2__LPUART4_TX 0x0008 0x024c 0x4 0x1
#define IMX7ULP_PAD_PTC2__LPI2C4_HREQ 0x0008 0x0274 0x5 0x1
#define IMX7ULP_PAD_PTC2__TPM4_CH1 0x0008 0x0284 0x6 0x1
#define IMX7ULP_PAD_PTC2__FB_AD2 0x0008 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC3__PTC3 0x000c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC3__TRACE_D12 0x000c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC3__LPUART4_RX 0x000c 0x0248 0x4 0x1
#define IMX7ULP_PAD_PTC3__TPM4_CH2 0x000c 0x0288 0x6 0x1
#define IMX7ULP_PAD_PTC3__FB_AD3 0x000c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC4__PTC4 0x0010 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC4__TRACE_D11 0x0010 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC4__FXIO1_D0 0x0010 0x0204 0x2 0x1
#define IMX7ULP_PAD_PTC4__LPSPI2_PCS1 0x0010 0x02a0 0x3 0x1
#define IMX7ULP_PAD_PTC4__LPUART5_CTS_B 0x0010 0x0250 0x4 0x1
#define IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x0010 0x02bc 0x5 0x1
#define IMX7ULP_PAD_PTC4__TPM4_CH3 0x0010 0x028c 0x6 0x1
#define IMX7ULP_PAD_PTC4__FB_AD4 0x0010 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC5__PTC5 0x0014 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC5__TRACE_D10 0x0014 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC5__FXIO1_D1 0x0014 0x0208 0x2 0x1
#define IMX7ULP_PAD_PTC5__LPSPI2_PCS2 0x0014 0x02a4 0x3 0x1
#define IMX7ULP_PAD_PTC5__LPUART5_RTS_B 0x0014 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x0014 0x02c0 0x5 0x1
#define IMX7ULP_PAD_PTC5__TPM4_CH4 0x0014 0x0290 0x6 0x1
#define IMX7ULP_PAD_PTC5__FB_AD5 0x0014 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC6__PTC6 0x0018 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC6__TRACE_D9 0x0018 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC6__FXIO1_D2 0x0018 0x020c 0x2 0x1
#define IMX7ULP_PAD_PTC6__LPSPI2_PCS3 0x0018 0x02a8 0x3 0x1
#define IMX7ULP_PAD_PTC6__LPUART5_TX 0x0018 0x0258 0x4 0x1
#define IMX7ULP_PAD_PTC6__LPI2C5_HREQ 0x0018 0x02b8 0x5 0x1
#define IMX7ULP_PAD_PTC6__TPM4_CH5 0x0018 0x0294 0x6 0x1
#define IMX7ULP_PAD_PTC6__FB_AD6 0x0018 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC7__PTC7 0x001c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC7__TRACE_D8 0x001c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC7__FXIO1_D3 0x001c 0x0210 0x2 0x1
#define IMX7ULP_PAD_PTC7__LPUART5_RX 0x001c 0x0254 0x4 0x1
#define IMX7ULP_PAD_PTC7__TPM5_CH1 0x001c 0x02c8 0x6 0x1
#define IMX7ULP_PAD_PTC7__FB_AD7 0x001c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC8__PTC8 0x0020 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC8__TRACE_D7 0x0020 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC8__FXIO1_D4 0x0020 0x0214 0x2 0x1
#define IMX7ULP_PAD_PTC8__LPSPI2_SIN 0x0020 0x02b0 0x3 0x1
#define IMX7ULP_PAD_PTC8__LPUART6_CTS_B 0x0020 0x025c 0x4 0x1
#define IMX7ULP_PAD_PTC8__LPI2C6_SCL 0x0020 0x02fc 0x5 0x1
#define IMX7ULP_PAD_PTC8__TPM5_CLKIN 0x0020 0x02cc 0x6 0x1
#define IMX7ULP_PAD_PTC8__FB_AD8 0x0020 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC9__PTC9 0x0024 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC9__TRACE_D6 0x0024 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC9__FXIO1_D5 0x0024 0x0218 0x2 0x1
#define IMX7ULP_PAD_PTC9__LPSPI2_SOUT 0x0024 0x02b4 0x3 0x1
#define IMX7ULP_PAD_PTC9__LPUART6_RTS_B 0x0024 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTC9__LPI2C6_SDA 0x0024 0x0300 0x5 0x1
#define IMX7ULP_PAD_PTC9__TPM5_CH0 0x0024 0x02c4 0x6 0x1
#define IMX7ULP_PAD_PTC9__FB_AD9 0x0024 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC10__PTC10 0x0028 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC10__TRACE_D5 0x0028 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC10__FXIO1_D6 0x0028 0x021c 0x2 0x1
#define IMX7ULP_PAD_PTC10__LPSPI2_SCK 0x0028 0x02ac 0x3 0x1
#define IMX7ULP_PAD_PTC10__LPUART6_TX 0x0028 0x0264 0x4 0x1
#define IMX7ULP_PAD_PTC10__LPI2C6_HREQ 0x0028 0x02f8 0x5 0x1
#define IMX7ULP_PAD_PTC10__TPM7_CH3 0x0028 0x02e8 0x6 0x1
#define IMX7ULP_PAD_PTC10__FB_AD10 0x0028 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC11__PTC11 0x002c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC11__TRACE_D4 0x002c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC11__FXIO1_D7 0x002c 0x0220 0x2 0x1
#define IMX7ULP_PAD_PTC11__LPSPI2_PCS0 0x002c 0x029c 0x3 0x1
#define IMX7ULP_PAD_PTC11__LPUART6_RX 0x002c 0x0260 0x4 0x1
#define IMX7ULP_PAD_PTC11__TPM7_CH4 0x002c 0x02ec 0x6 0x1
#define IMX7ULP_PAD_PTC11__FB_AD11 0x002c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC12__PTC12 0x0030 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC12__TRACE_D3 0x0030 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC12__FXIO1_D8 0x0030 0x0224 0x2 0x1
#define IMX7ULP_PAD_PTC12__LPSPI3_PCS1 0x0030 0x0314 0x3 0x1
#define IMX7ULP_PAD_PTC12__LPUART7_CTS_B 0x0030 0x0268 0x4 0x1
#define IMX7ULP_PAD_PTC12__LPI2C7_SCL 0x0030 0x0308 0x5 0x1
#define IMX7ULP_PAD_PTC12__TPM7_CH5 0x0030 0x02f0 0x6 0x1
#define IMX7ULP_PAD_PTC12__FB_AD12 0x0030 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC13__PTC13 0x0034 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC13__TRACE_D2 0x0034 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC13__FXIO1_D9 0x0034 0x0228 0x2 0x1
#define IMX7ULP_PAD_PTC13__LPSPI3_PCS2 0x0034 0x0318 0x3 0x1
#define IMX7ULP_PAD_PTC13__LPUART7_RTS_B 0x0034 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTC13__LPI2C7_SDA 0x0034 0x030c 0x5 0x1
#define IMX7ULP_PAD_PTC13__TPM7_CLKIN 0x0034 0x02f4 0x6 0x1
#define IMX7ULP_PAD_PTC13__FB_AD13 0x0034 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC14__PTC14 0x0038 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC14__TRACE_D1 0x0038 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC14__FXIO1_D10 0x0038 0x022c 0x2 0x1
#define IMX7ULP_PAD_PTC14__LPSPI3_PCS3 0x0038 0x031c 0x3 0x1
#define IMX7ULP_PAD_PTC14__LPUART7_TX 0x0038 0x0270 0x4 0x1
#define IMX7ULP_PAD_PTC14__LPI2C7_HREQ 0x0038 0x0304 0x5 0x1
#define IMX7ULP_PAD_PTC14__TPM7_CH0 0x0038 0x02dc 0x6 0x1
#define IMX7ULP_PAD_PTC14__FB_AD14 0x0038 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC15__PTC15 0x003c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC15__TRACE_D0 0x003c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC15__FXIO1_D11 0x003c 0x0230 0x2 0x1
#define IMX7ULP_PAD_PTC15__LPUART7_RX 0x003c 0x026c 0x4 0x1
#define IMX7ULP_PAD_PTC15__TPM7_CH1 0x003c 0x02e0 0x6 0x1
#define IMX7ULP_PAD_PTC15__FB_AD15 0x003c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC16__PTC16 0x0040 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC16__TRACE_CLKOUT 0x0040 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTC16__FXIO1_D12 0x0040 0x0234 0x2 0x1
#define IMX7ULP_PAD_PTC16__LPSPI3_SIN 0x0040 0x0324 0x3 0x1
#define IMX7ULP_PAD_PTC16__TPM7_CH2 0x0040 0x02e4 0x6 0x1
#define IMX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B 0x0040 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC17__PTC17 0x0044 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC17__FXIO1_D13 0x0044 0x0238 0x2 0x1
#define IMX7ULP_PAD_PTC17__LPSPI3_SOUT 0x0044 0x0328 0x3 0x1
#define IMX7ULP_PAD_PTC17__TPM6_CLKIN 0x0044 0x02d8 0x6 0x1
#define IMX7ULP_PAD_PTC17__FB_CS0_B 0x0044 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC18__PTC18 0x0048 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC18__FXIO1_D14 0x0048 0x023c 0x2 0x1
#define IMX7ULP_PAD_PTC18__LPSPI3_SCK 0x0048 0x0320 0x3 0x1
#define IMX7ULP_PAD_PTC18__TPM6_CH0 0x0048 0x02d0 0x6 0x1
#define IMX7ULP_PAD_PTC18__FB_OE_B 0x0048 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTC19__PTC19 0x004c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTC19__FXIO1_D15 0x004c 0x0240 0x2 0x1
#define IMX7ULP_PAD_PTC19__LPSPI3_PCS0 0x004c 0x0310 0x3 0x1
#define IMX7ULP_PAD_PTC19__TPM6_CH1 0x004c 0x02d4 0x6 0x1
#define IMX7ULP_PAD_PTC19__FB_A16 0x004c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTD0__PTD0 0x0080 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD0__SDHC0_RESET_B 0x0080 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD1__PTD1 0x0084 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD1__SDHC0_CMD 0x0084 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD2__PTD2 0x0088 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD2__SDHC0_CLK 0x0088 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD3__PTD3 0x008c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD3__SDHC0_D7 0x008c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD4__PTD4 0x0090 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD4__SDHC0_D6 0x0090 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD5__PTD5 0x0094 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD5__SDHC0_D5 0x0094 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD6__PTD6 0x0098 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD6__SDHC0_D4 0x0098 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD7__PTD7 0x009c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD7__SDHC0_D3 0x009c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD8__PTD8 0x00a0 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD8__TPM4_CLKIN 0x00a0 0x0298 0x6 0x2
#define IMX7ULP_PAD_PTD8__SDHC0_D2 0x00a0 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD9__PTD9 0x00a4 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD9__TPM4_CH0 0x00a4 0x0280 0x6 0x2
#define IMX7ULP_PAD_PTD9__SDHC0_D1 0x00a4 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD10__PTD10 0x00a8 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD10__TPM4_CH1 0x00a8 0x0284 0x6 0x2
#define IMX7ULP_PAD_PTD10__SDHC0_D0 0x00a8 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTD11__PTD11 0x00ac 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTD11__TPM4_CH2 0x00ac 0x0288 0x6 0x2
#define IMX7ULP_PAD_PTD11__SDHC0_DQS 0x00ac 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE0__PTE0 0x0100 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE0__FXIO1_D31 0x0100 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE0__LPSPI2_PCS1 0x0100 0x02a0 0x3 0x2
#define IMX7ULP_PAD_PTE0__LPUART4_CTS_B 0x0100 0x0244 0x4 0x2
#define IMX7ULP_PAD_PTE0__LPI2C4_SCL 0x0100 0x0278 0x5 0x2
#define IMX7ULP_PAD_PTE0__SDHC1_D1 0x0100 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE0__FB_A25 0x0100 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE1__PTE1 0x0104 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE1__FXIO1_D30 0x0104 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE1__LPSPI2_PCS2 0x0104 0x02a4 0x3 0x2
#define IMX7ULP_PAD_PTE1__LPUART4_RTS_B 0x0104 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTE1__LPI2C4_SDA 0x0104 0x027c 0x5 0x2
#define IMX7ULP_PAD_PTE1__SDHC1_D0 0x0104 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE1__FB_A26 0x0104 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE2__PTE2 0x0108 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE2__FXIO1_D29 0x0108 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE2__LPSPI2_PCS3 0x0108 0x02a8 0x3 0x2
#define IMX7ULP_PAD_PTE2__LPUART4_TX 0x0108 0x024c 0x4 0x2
#define IMX7ULP_PAD_PTE2__LPI2C4_HREQ 0x0108 0x0274 0x5 0x2
#define IMX7ULP_PAD_PTE2__SDHC1_CLK 0x0108 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE3__PTE3 0x010c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE3__FXIO1_D28 0x010c 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE3__LPUART4_RX 0x010c 0x0248 0x4 0x2
#define IMX7ULP_PAD_PTE3__TPM5_CH1 0x010c 0x02c8 0x6 0x2
#define IMX7ULP_PAD_PTE3__SDHC1_CMD 0x010c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE4__PTE4 0x0110 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE4__FXIO1_D27 0x0110 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE4__LPSPI2_SIN 0x0110 0x02b0 0x3 0x2
#define IMX7ULP_PAD_PTE4__LPUART5_CTS_B 0x0110 0x0250 0x4 0x2
#define IMX7ULP_PAD_PTE4__LPI2C5_SCL 0x0110 0x02bc 0x5 0x2
#define IMX7ULP_PAD_PTE4__TPM5_CLKIN 0x0110 0x02cc 0x6 0x2
#define IMX7ULP_PAD_PTE4__SDHC1_D3 0x0110 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE5__PTE5 0x0114 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE5__FXIO1_D26 0x0114 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE5__LPSPI2_SOUT 0x0114 0x02b4 0x3 0x2
#define IMX7ULP_PAD_PTE5__LPUART5_RTS_B 0x0114 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTE5__LPI2C5_SDA 0x0114 0x02c0 0x5 0x2
#define IMX7ULP_PAD_PTE5__TPM5_CH0 0x0114 0x02c4 0x6 0x2
#define IMX7ULP_PAD_PTE5__SDHC1_D2 0x0114 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE6__PTE6 0x0118 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE6__FXIO1_D25 0x0118 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE6__LPSPI2_SCK 0x0118 0x02ac 0x3 0x2
#define IMX7ULP_PAD_PTE6__LPUART5_TX 0x0118 0x0258 0x4 0x2
#define IMX7ULP_PAD_PTE6__LPI2C5_HREQ 0x0118 0x02b8 0x5 0x2
#define IMX7ULP_PAD_PTE6__TPM7_CH3 0x0118 0x02e8 0x6 0x2
#define IMX7ULP_PAD_PTE6__SDHC1_D4 0x0118 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE6__FB_A17 0x0118 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE7__PTE7 0x011c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE7__TRACE_D7 0x011c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE7__VIU_FID 0x011c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE7__FXIO1_D24 0x011c 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE7__LPSPI2_PCS0 0x011c 0x029c 0x3 0x2
#define IMX7ULP_PAD_PTE7__LPUART5_RX 0x011c 0x0254 0x4 0x2
#define IMX7ULP_PAD_PTE7__TPM7_CH4 0x011c 0x02ec 0x6 0x2
#define IMX7ULP_PAD_PTE7__SDHC1_D5 0x011c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE7__FB_A18 0x011c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE8__PTE8 0x0120 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE8__TRACE_D6 0x0120 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE8__VIU_D16 0x0120 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE8__FXIO1_D23 0x0120 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE8__LPSPI3_PCS1 0x0120 0x0314 0x3 0x2
#define IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x0120 0x025c 0x4 0x2
#define IMX7ULP_PAD_PTE8__LPI2C6_SCL 0x0120 0x02fc 0x5 0x2
#define IMX7ULP_PAD_PTE8__TPM7_CH5 0x0120 0x02f0 0x6 0x2
#define IMX7ULP_PAD_PTE8__SDHC1_WP 0x0120 0x0200 0x7 0x1
#define IMX7ULP_PAD_PTE8__SDHC1_D6 0x0120 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B 0x0120 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE9__PTE9 0x0124 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE9__TRACE_D5 0x0124 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE9__VIU_D17 0x0124 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE9__FXIO1_D22 0x0124 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE9__LPSPI3_PCS2 0x0124 0x0318 0x3 0x2
#define IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x0124 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTE9__LPI2C6_SDA 0x0124 0x0300 0x5 0x2
#define IMX7ULP_PAD_PTE9__TPM7_CLKIN 0x0124 0x02f4 0x6 0x2
#define IMX7ULP_PAD_PTE9__SDHC1_CD 0x0124 0x032c 0x7 0x1
#define IMX7ULP_PAD_PTE9__SDHC1_D7 0x0124 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B 0x0124 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE10__PTE10 0x0128 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE10__TRACE_D4 0x0128 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE10__VIU_D18 0x0128 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE10__FXIO1_D21 0x0128 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE10__LPSPI3_PCS3 0x0128 0x031c 0x3 0x2
#define IMX7ULP_PAD_PTE10__LPUART6_TX 0x0128 0x0264 0x4 0x2
#define IMX7ULP_PAD_PTE10__LPI2C6_HREQ 0x0128 0x02f8 0x5 0x2
#define IMX7ULP_PAD_PTE10__TPM7_CH0 0x0128 0x02dc 0x6 0x2
#define IMX7ULP_PAD_PTE10__SDHC1_VS 0x0128 0x0000 0x7 0x0
#define IMX7ULP_PAD_PTE10__SDHC1_DQS 0x0128 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE10__FB_A19 0x0128 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE11__PTE11 0x012c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE11__TRACE_D3 0x012c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE11__VIU_D19 0x012c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE11__FXIO1_D20 0x012c 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE11__LPUART6_RX 0x012c 0x0260 0x4 0x2
#define IMX7ULP_PAD_PTE11__TPM7_CH1 0x012c 0x02e0 0x6 0x2
#define IMX7ULP_PAD_PTE11__SDHC1_RESET_B 0x012c 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE11__FB_A20 0x012c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE12__PTE12 0x0130 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE12__TRACE_D2 0x0130 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE12__VIU_D20 0x0130 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE12__FXIO1_D19 0x0130 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE12__LPSPI3_SIN 0x0130 0x0324 0x3 0x2
#define IMX7ULP_PAD_PTE12__LPUART7_CTS_B 0x0130 0x0268 0x4 0x2
#define IMX7ULP_PAD_PTE12__LPI2C7_SCL 0x0130 0x0308 0x5 0x2
#define IMX7ULP_PAD_PTE12__TPM7_CH2 0x0130 0x02e4 0x6 0x2
#define IMX7ULP_PAD_PTE12__SDHC1_WP 0x0130 0x0200 0x8 0x2
#define IMX7ULP_PAD_PTE12__FB_A21 0x0130 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE13__PTE13 0x0134 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE13__TRACE_D1 0x0134 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE13__VIU_D21 0x0134 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE13__FXIO1_D18 0x0134 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE13__LPSPI3_SOUT 0x0134 0x0328 0x3 0x2
#define IMX7ULP_PAD_PTE13__LPUART7_RTS_B 0x0134 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTE13__LPI2C7_SDA 0x0134 0x030c 0x5 0x2
#define IMX7ULP_PAD_PTE13__TPM6_CLKIN 0x0134 0x02d8 0x6 0x2
#define IMX7ULP_PAD_PTE13__SDHC1_CD 0x0134 0x032c 0x8 0x2
#define IMX7ULP_PAD_PTE13__FB_A22 0x0134 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE14__PTE14 0x0138 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE14__TRACE_D0 0x0138 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE14__VIU_D22 0x0138 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE14__FXIO1_D17 0x0138 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE14__LPSPI3_SCK 0x0138 0x0320 0x3 0x2
#define IMX7ULP_PAD_PTE14__LPUART7_TX 0x0138 0x0270 0x4 0x2
#define IMX7ULP_PAD_PTE14__LPI2C7_HREQ 0x0138 0x0304 0x5 0x2
#define IMX7ULP_PAD_PTE14__TPM6_CH0 0x0138 0x02d0 0x6 0x2
#define IMX7ULP_PAD_PTE14__SDHC1_VS 0x0138 0x0000 0x8 0x0
#define IMX7ULP_PAD_PTE14__FB_A23 0x0138 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTE15__PTE15 0x013c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTE15__TRACE_CLKOUT 0x013c 0x0000 0xa 0x0
#define IMX7ULP_PAD_PTE15__VIU_D23 0x013c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTE15__FXIO1_D16 0x013c 0x0000 0x2 0x0
#define IMX7ULP_PAD_PTE15__LPSPI3_PCS0 0x013c 0x0310 0x3 0x2
#define IMX7ULP_PAD_PTE15__LPUART7_RX 0x013c 0x026c 0x4 0x2
#define IMX7ULP_PAD_PTE15__TPM6_CH1 0x013c 0x02d4 0x6 0x2
#define IMX7ULP_PAD_PTE15__FB_A24 0x013c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF0__PTF0 0x0180 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF0__VIU_DE 0x0180 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF0__LPUART4_CTS_B 0x0180 0x0244 0x4 0x3
#define IMX7ULP_PAD_PTF0__LPI2C4_SCL 0x0180 0x0278 0x5 0x3
#define IMX7ULP_PAD_PTF0__TPM4_CLKIN 0x0180 0x0298 0x6 0x3
#define IMX7ULP_PAD_PTF0__FB_RW_B 0x0180 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF1__PTF1 0x0184 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF1__VIU_HSYNC 0x0184 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF1__LPUART4_RTS_B 0x0184 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTF1__LPI2C4_SDA 0x0184 0x027c 0x5 0x3
#define IMX7ULP_PAD_PTF1__TPM4_CH0 0x0184 0x0280 0x6 0x3
#define IMX7ULP_PAD_PTF1__CLKOUT 0x0184 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF2__PTF2 0x0188 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF2__VIU_VSYNC 0x0188 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF2__LPUART4_TX 0x0188 0x024c 0x4 0x3
#define IMX7ULP_PAD_PTF2__LPI2C4_HREQ 0x0188 0x0274 0x5 0x3
#define IMX7ULP_PAD_PTF2__TPM4_CH1 0x0188 0x0284 0x6 0x3
#define IMX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B 0x0188 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF3__PTF3 0x018c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF3__VIU_PCLK 0x018c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF3__LPUART4_RX 0x018c 0x0248 0x4 0x3
#define IMX7ULP_PAD_PTF3__TPM4_CH2 0x018c 0x0288 0x6 0x3
#define IMX7ULP_PAD_PTF3__FB_AD16 0x018c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF4__PTF4 0x0190 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF4__VIU_D0 0x0190 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF4__FXIO1_D0 0x0190 0x0204 0x2 0x2
#define IMX7ULP_PAD_PTF4__LPSPI2_PCS1 0x0190 0x02a0 0x3 0x3
#define IMX7ULP_PAD_PTF4__LPUART5_CTS_B 0x0190 0x0250 0x4 0x3
#define IMX7ULP_PAD_PTF4__LPI2C5_SCL 0x0190 0x02bc 0x5 0x3
#define IMX7ULP_PAD_PTF4__TPM4_CH3 0x0190 0x028c 0x6 0x2
#define IMX7ULP_PAD_PTF4__FB_AD17 0x0190 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF5__PTF5 0x0194 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF5__VIU_D1 0x0194 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF5__FXIO1_D1 0x0194 0x0208 0x2 0x2
#define IMX7ULP_PAD_PTF5__LPSPI2_PCS2 0x0194 0x02a4 0x3 0x3
#define IMX7ULP_PAD_PTF5__LPUART5_RTS_B 0x0194 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTF5__LPI2C5_SDA 0x0194 0x02c0 0x5 0x3
#define IMX7ULP_PAD_PTF5__TPM4_CH4 0x0194 0x0290 0x6 0x2
#define IMX7ULP_PAD_PTF5__FB_AD18 0x0194 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF6__PTF6 0x0198 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF6__VIU_D2 0x0198 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF6__FXIO1_D2 0x0198 0x020c 0x2 0x2
#define IMX7ULP_PAD_PTF6__LPSPI2_PCS3 0x0198 0x02a8 0x3 0x3
#define IMX7ULP_PAD_PTF6__LPUART5_TX 0x0198 0x0258 0x4 0x3
#define IMX7ULP_PAD_PTF6__LPI2C5_HREQ 0x0198 0x02b8 0x5 0x3
#define IMX7ULP_PAD_PTF6__TPM4_CH5 0x0198 0x0294 0x6 0x2
#define IMX7ULP_PAD_PTF6__FB_AD19 0x0198 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF7__PTF7 0x019c 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF7__VIU_D3 0x019c 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF7__FXIO1_D3 0x019c 0x0210 0x2 0x2
#define IMX7ULP_PAD_PTF7__LPUART5_RX 0x019c 0x0254 0x4 0x3
#define IMX7ULP_PAD_PTF7__TPM5_CH1 0x019c 0x02c8 0x6 0x3
#define IMX7ULP_PAD_PTF7__FB_AD20 0x019c 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF8__PTF8 0x01a0 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF8__USB1_ULPI_CLK 0x01a0 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF8__VIU_D4 0x01a0 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF8__FXIO1_D4 0x01a0 0x0214 0x2 0x2
#define IMX7ULP_PAD_PTF8__LPSPI2_SIN 0x01a0 0x02b0 0x3 0x3
#define IMX7ULP_PAD_PTF8__LPUART6_CTS_B 0x01a0 0x025c 0x4 0x3
#define IMX7ULP_PAD_PTF8__LPI2C6_SCL 0x01a0 0x02fc 0x5 0x3
#define IMX7ULP_PAD_PTF8__TPM5_CLKIN 0x01a0 0x02cc 0x6 0x3
#define IMX7ULP_PAD_PTF8__FB_AD21 0x01a0 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF9__PTF9 0x01a4 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF9__USB1_ULPI_NXT 0x01a4 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF9__VIU_D5 0x01a4 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF9__FXIO1_D5 0x01a4 0x0218 0x2 0x2
#define IMX7ULP_PAD_PTF9__LPSPI2_SOUT 0x01a4 0x02b4 0x3 0x3
#define IMX7ULP_PAD_PTF9__LPUART6_RTS_B 0x01a4 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTF9__LPI2C6_SDA 0x01a4 0x0300 0x5 0x3
#define IMX7ULP_PAD_PTF9__TPM5_CH0 0x01a4 0x02c4 0x6 0x3
#define IMX7ULP_PAD_PTF9__FB_AD22 0x01a4 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF10__PTF10 0x01a8 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF10__USB1_ULPI_STP 0x01a8 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF10__VIU_D6 0x01a8 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF10__FXIO1_D6 0x01a8 0x021c 0x2 0x2
#define IMX7ULP_PAD_PTF10__LPSPI2_SCK 0x01a8 0x02ac 0x3 0x3
#define IMX7ULP_PAD_PTF10__LPUART6_TX 0x01a8 0x0264 0x4 0x3
#define IMX7ULP_PAD_PTF10__LPI2C6_HREQ 0x01a8 0x02f8 0x5 0x3
#define IMX7ULP_PAD_PTF10__TPM7_CH3 0x01a8 0x02e8 0x6 0x3
#define IMX7ULP_PAD_PTF10__FB_AD23 0x01a8 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF11__PTF11 0x01ac 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF11__USB1_ULPI_DIR 0x01ac 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF11__VIU_D7 0x01ac 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF11__FXIO1_D7 0x01ac 0x0220 0x2 0x2
#define IMX7ULP_PAD_PTF11__LPSPI2_PCS0 0x01ac 0x029c 0x3 0x3
#define IMX7ULP_PAD_PTF11__LPUART6_RX 0x01ac 0x0260 0x4 0x3
#define IMX7ULP_PAD_PTF11__TPM7_CH4 0x01ac 0x02ec 0x6 0x3
#define IMX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B 0x01ac 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF12__PTF12 0x01b0 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF12__USB1_ULPI_DATA0 0x01b0 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF12__VIU_D8 0x01b0 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF12__FXIO1_D8 0x01b0 0x0224 0x2 0x2
#define IMX7ULP_PAD_PTF12__LPSPI3_PCS1 0x01b0 0x0314 0x3 0x3
#define IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x01b0 0x0268 0x4 0x3
#define IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x01b0 0x0308 0x5 0x3
#define IMX7ULP_PAD_PTF12__TPM7_CH5 0x01b0 0x02f0 0x6 0x3
#define IMX7ULP_PAD_PTF12__FB_AD24 0x01b0 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF13__PTF13 0x01b4 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF13__USB1_ULPI_DATA1 0x01b4 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF13__VIU_D9 0x01b4 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF13__FXIO1_D9 0x01b4 0x0228 0x2 0x2
#define IMX7ULP_PAD_PTF13__LPSPI3_PCS2 0x01b4 0x0318 0x3 0x3
#define IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x01b4 0x0000 0x4 0x0
#define IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x01b4 0x030c 0x5 0x3
#define IMX7ULP_PAD_PTF13__TPM7_CLKIN 0x01b4 0x02f4 0x6 0x3
#define IMX7ULP_PAD_PTF13__FB_AD25 0x01b4 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF14__PTF14 0x01b8 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF14__USB1_ULPI_DATA2 0x01b8 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF14__VIU_D10 0x01b8 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF14__FXIO1_D10 0x01b8 0x022c 0x2 0x2
#define IMX7ULP_PAD_PTF14__LPSPI3_PCS3 0x01b8 0x031c 0x3 0x3
#define IMX7ULP_PAD_PTF14__LPUART7_TX 0x01b8 0x0270 0x4 0x3
#define IMX7ULP_PAD_PTF14__LPI2C7_HREQ 0x01b8 0x0304 0x5 0x3
#define IMX7ULP_PAD_PTF14__TPM7_CH0 0x01b8 0x02dc 0x6 0x3
#define IMX7ULP_PAD_PTF14__FB_AD26 0x01b8 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF15__PTF15 0x01bc 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF15__USB1_ULPI_DATA3 0x01bc 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF15__VIU_D11 0x01bc 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF15__FXIO1_D11 0x01bc 0x0230 0x2 0x2
#define IMX7ULP_PAD_PTF15__LPUART7_RX 0x01bc 0x026c 0x4 0x3
#define IMX7ULP_PAD_PTF15__TPM7_CH1 0x01bc 0x02e0 0x6 0x3
#define IMX7ULP_PAD_PTF15__FB_AD27 0x01bc 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF16__PTF16 0x01c0 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF16__USB1_ULPI_DATA4 0x01c0 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF16__VIU_D12 0x01c0 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF16__FXIO1_D12 0x01c0 0x0234 0x2 0x2
#define IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x01c0 0x0324 0x3 0x3
#define IMX7ULP_PAD_PTF16__TPM7_CH2 0x01c0 0x02e4 0x6 0x3
#define IMX7ULP_PAD_PTF16__FB_AD28 0x01c0 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF17__PTF17 0x01c4 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF17__USB1_ULPI_DATA5 0x01c4 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF17__VIU_D13 0x01c4 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF17__FXIO1_D13 0x01c4 0x0238 0x2 0x2
#define IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x01c4 0x0328 0x3 0x3
#define IMX7ULP_PAD_PTF17__TPM6_CLKIN 0x01c4 0x02d8 0x6 0x3
#define IMX7ULP_PAD_PTF17__FB_AD29 0x01c4 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF18__PTF18 0x01c8 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF18__USB1_ULPI_DATA6 0x01c8 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF18__VIU_D14 0x01c8 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF18__FXIO1_D14 0x01c8 0x023c 0x2 0x2
#define IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x01c8 0x0320 0x3 0x3
#define IMX7ULP_PAD_PTF18__TPM6_CH0 0x01c8 0x02d0 0x6 0x3
#define IMX7ULP_PAD_PTF18__FB_AD30 0x01c8 0x0000 0x9 0x0
#define IMX7ULP_PAD_PTF19__PTF19 0x01cc 0x0000 0x1 0x0
#define IMX7ULP_PAD_PTF19__USB1_ULPI_DATA7 0x01cc 0x0000 0xb 0x0
#define IMX7ULP_PAD_PTF19__VIU_D15 0x01cc 0x0000 0xc 0x0
#define IMX7ULP_PAD_PTF19__FXIO1_D15 0x01cc 0x0240 0x2 0x2
#define IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x01cc 0x0310 0x3 0x3
#define IMX7ULP_PAD_PTF19__TPM6_CH1 0x01cc 0x02d4 0x6 0x3
#define IMX7ULP_PAD_PTF19__FB_AD31 0x01cc 0x0000 0x9 0x0
#endif /* __DTS_IMX7ULP_PINFUNC_H */

8
drivers/pinctrl/Kconfig
View file

@ -146,6 +146,13 @@ config PINCTRL_FALCON
depends on SOC_FALCON
depends on PINCTRL_LANTIQ
config PINCTRL_GEMINI
bool
depends on ARCH_GEMINI
default ARCH_GEMINI
select PINMUX
select MFD_SYSCON
config PINCTRL_MCP23S08
tristate "Microchip MCP23xxx I/O expander"
depends on SPI_MASTER || I2C
@ -343,6 +350,7 @@ source "drivers/pinctrl/qcom/Kconfig"
source "drivers/pinctrl/samsung/Kconfig"
source "drivers/pinctrl/sh-pfc/Kconfig"
source "drivers/pinctrl/spear/Kconfig"
source "drivers/pinctrl/sprd/Kconfig"
source "drivers/pinctrl/stm32/Kconfig"
source "drivers/pinctrl/sunxi/Kconfig"
source "drivers/pinctrl/tegra/Kconfig"

2
drivers/pinctrl/Makefile
View file

@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o
obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o
obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o
obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o
obj-$(CONFIG_PINCTRL_MESON) += meson/
@ -55,6 +56,7 @@ obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/
obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
obj-$(CONFIG_PINCTRL_SPEAR) += spear/
obj-y += sprd/
obj-$(CONFIG_PINCTRL_STM32) += stm32/
obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
obj-y += ti/

70
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
View file

@ -1006,15 +1006,23 @@ SS_PIN_DECL(H3, GPIOQ5, SDA14);
FUNC_GROUP_DECL(I2C14, H4, H3);
#define DASH9028_DESC SIG_DESC_SET(SCU90, 28)
/*
* There are several opportunities to document USB port 4 in the datasheet, but
* it is only mentioned in one location. Particularly, the Multi-function Pins
* Mapping and Control table in the datasheet elides the signal names,
* suggesting that port 4 may not actually be functional. As such we define the
* signal names and control bit, but don't export the capability's function or
* group.
*/
#define USB11H3_DESC SIG_DESC_SET(SCU90, 28)
#define H2 134
SIG_EXPR_LIST_DECL_SINGLE(DASHH2, DASHH2, DASH9028_DESC);
SS_PIN_DECL(H2, GPIOQ6, DASHH2);
SIG_EXPR_LIST_DECL_SINGLE(USB11HDP3, USB11H3, USB11H3_DESC);
SS_PIN_DECL(H2, GPIOQ6, USB11HDP3);
#define H1 135
SIG_EXPR_LIST_DECL_SINGLE(DASHH1, DASHH1, DASH9028_DESC);
SS_PIN_DECL(H1, GPIOQ7, DASHH1);
SIG_EXPR_LIST_DECL_SINGLE(USB11HDN3, USB11H3, USB11H3_DESC);
SS_PIN_DECL(H1, GPIOQ7, USB11HDN3);
#define V20 136
SSSF_PIN_DECL(V20, GPIOR0, ROMCS1, SIG_DESC_SET(SCU88, 24));
@ -1706,10 +1714,42 @@ FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20, R22, P18, P19, P20, P21, P22, M19,
FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19,
P20, P21, P22, M19, M20, M21, M22, L18, L19);
#define USB11H2_DESC SIG_DESC_SET(SCU90, 3)
#define USB11D1_DESC SIG_DESC_BIT(SCU90, 3, 0)
#define K4 220
SIG_EXPR_LIST_DECL_SINGLE(USB11HDP2, USB11H2, USB11H2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(USB11DP1, USB11D1, USB11D1_DESC);
MS_PIN_DECL_(K4, SIG_EXPR_LIST_PTR(USB11HDP2), SIG_EXPR_LIST_PTR(USB11DP1));
#define K3 221
SIG_EXPR_LIST_DECL_SINGLE(USB11HDN1, USB11H2, USB11H2_DESC);
SIG_EXPR_LIST_DECL_SINGLE(USB11DDN1, USB11D1, USB11D1_DESC);
MS_PIN_DECL_(K3, SIG_EXPR_LIST_PTR(USB11HDN1), SIG_EXPR_LIST_PTR(USB11DDN1));
FUNC_GROUP_DECL(USB11H2, K4, K3);
FUNC_GROUP_DECL(USB11D1, K4, K3);
#define USB2H1_DESC SIG_DESC_SET(SCU90, 29)
#define USB2D1_DESC SIG_DESC_BIT(SCU90, 29, 0)
#define AB21 222
SIG_EXPR_LIST_DECL_SINGLE(USB2HDP1, USB2H1, USB2H1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(USB2DDP1, USB2D1, USB2D1_DESC);
MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(USB2HDP1), SIG_EXPR_LIST_PTR(USB2DDP1));
#define AB20 223
SIG_EXPR_LIST_DECL_SINGLE(USB2HDN1, USB2H1, USB2H1_DESC);
SIG_EXPR_LIST_DECL_SINGLE(USB2DDN1, USB2D1, USB2D1_DESC);
MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(USB2HDN1), SIG_EXPR_LIST_PTR(USB2DDN1));
FUNC_GROUP_DECL(USB2H1, AB21, AB20);
FUNC_GROUP_DECL(USB2D1, AB21, AB20);
/* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216
* pins becomes 220.
* pins becomes 220. Four additional non-GPIO-capable pins are present for USB.
*/
#define ASPEED_G4_NR_PINS 220
#define ASPEED_G4_NR_PINS 224
/* Pins, groups and functions are sort(1):ed alphabetically for sanity */
@ -1749,6 +1789,8 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
ASPEED_PINCTRL_PIN(AB5),
ASPEED_PINCTRL_PIN(AB6),
ASPEED_PINCTRL_PIN(AB7),
ASPEED_PINCTRL_PIN(AB20),
ASPEED_PINCTRL_PIN(AB21),
ASPEED_PINCTRL_PIN(B1),
ASPEED_PINCTRL_PIN(B10),
ASPEED_PINCTRL_PIN(B11),
@ -1848,6 +1890,8 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
ASPEED_PINCTRL_PIN(J5),
ASPEED_PINCTRL_PIN(K18),
ASPEED_PINCTRL_PIN(K20),
ASPEED_PINCTRL_PIN(K3),
ASPEED_PINCTRL_PIN(K4),
ASPEED_PINCTRL_PIN(K5),
ASPEED_PINCTRL_PIN(L1),
ASPEED_PINCTRL_PIN(L18),
@ -2070,6 +2114,10 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = {
ASPEED_PINCTRL_GROUP(TXD3),
ASPEED_PINCTRL_GROUP(TXD4),
ASPEED_PINCTRL_GROUP(UART6),
ASPEED_PINCTRL_GROUP(USB11D1),
ASPEED_PINCTRL_GROUP(USB11H2),
ASPEED_PINCTRL_GROUP(USB2D1),
ASPEED_PINCTRL_GROUP(USB2H1),
ASPEED_PINCTRL_GROUP(USBCKI),
ASPEED_PINCTRL_GROUP(VGABIOS_ROM),
ASPEED_PINCTRL_GROUP(VGAHS),
@ -2221,6 +2269,10 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
ASPEED_PINCTRL_FUNC(TXD3),
ASPEED_PINCTRL_FUNC(TXD4),
ASPEED_PINCTRL_FUNC(UART6),
ASPEED_PINCTRL_FUNC(USB11D1),
ASPEED_PINCTRL_FUNC(USB11H2),
ASPEED_PINCTRL_FUNC(USB2D1),
ASPEED_PINCTRL_FUNC(USB2H1),
ASPEED_PINCTRL_FUNC(USBCKI),
ASPEED_PINCTRL_FUNC(VGABIOS_ROM),
ASPEED_PINCTRL_FUNC(VGAHS),
@ -2349,7 +2401,7 @@ static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = {
.nconfigs = ARRAY_SIZE(aspeed_g4_configs),
};
static struct pinmux_ops aspeed_g4_pinmux_ops = {
static const struct pinmux_ops aspeed_g4_pinmux_ops = {
.get_functions_count = aspeed_pinmux_get_fn_count,
.get_function_name = aspeed_pinmux_get_fn_name,
.get_function_groups = aspeed_pinmux_get_fn_groups,
@ -2358,7 +2410,7 @@ static struct pinmux_ops aspeed_g4_pinmux_ops = {
.strict = true,
};
static struct pinctrl_ops aspeed_g4_pinctrl_ops = {
static const struct pinctrl_ops aspeed_g4_pinctrl_ops = {
.get_groups_count = aspeed_pinctrl_get_groups_count,
.get_group_name = aspeed_pinctrl_get_group_name,
.get_group_pins = aspeed_pinctrl_get_group_pins,

64
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
View file

@ -25,7 +25,7 @@
#include "../pinctrl-utils.h"
#include "pinctrl-aspeed.h"
#define ASPEED_G5_NR_PINS 232
#define ASPEED_G5_NR_PINS 236
#define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 }
#define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
@ -1724,6 +1724,48 @@ FUNC_GROUP_DECL(LPCRST, G22);
FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22);
#define A7 232
SIG_EXPR_LIST_DECL_SINGLE(USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29));
SIG_EXPR_LIST_DECL_SINGLE(USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
MS_PIN_DECL_(A7, SIG_EXPR_LIST_PTR(USB2AHDP), SIG_EXPR_LIST_PTR(USB2ADDP));
#define A8 233
SIG_EXPR_LIST_DECL_SINGLE(USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29));
SIG_EXPR_LIST_DECL_SINGLE(USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0));
MS_PIN_DECL_(A8, SIG_EXPR_LIST_PTR(USB2AHDN), SIG_EXPR_LIST_PTR(USB2ADDN));
FUNC_GROUP_DECL(USB2AH, A7, A8);
FUNC_GROUP_DECL(USB2AD, A7, A8);
#define USB11BHID_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 0, 0 }
#define USB2BD_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 1, 0 }
#define USB2BH1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 2, 0 }
#define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 }
#define B6 234
SIG_EXPR_LIST_DECL_SINGLE(USB11BDP, USB11BHID, USB11BHID_DESC);
SIG_EXPR_LIST_DECL_SINGLE(USB2BDDP, USB2BD, USB2BD_DESC);
SIG_EXPR_DECL(USB2BHDP1, USB2BH, USB2BH1_DESC);
SIG_EXPR_DECL(USB2BHDP2, USB2BH, USB2BH2_DESC);
SIG_EXPR_LIST_DECL(USB2BHDP, SIG_EXPR_PTR(USB2BHDP1, USB2BH),
SIG_EXPR_PTR(USB2BHDP2, USB2BH));
MS_PIN_DECL_(B6, SIG_EXPR_LIST_PTR(USB11BDP), SIG_EXPR_LIST_PTR(USB2BDDP),
SIG_EXPR_LIST_PTR(USB2BHDP));
#define A6 235
SIG_EXPR_LIST_DECL_SINGLE(USB11BDN, USB11BHID, USB11BHID_DESC);
SIG_EXPR_LIST_DECL_SINGLE(USB2BDN, USB2BD, USB2BD_DESC);
SIG_EXPR_DECL(USB2BHDN1, USB2BH, USB2BH1_DESC);
SIG_EXPR_DECL(USB2BHDN2, USB2BH, USB2BH2_DESC);
SIG_EXPR_LIST_DECL(USB2BHDN, SIG_EXPR_PTR(USB2BHDN1, USB2BH),
SIG_EXPR_PTR(USB2BHDN2, USB2BH));
MS_PIN_DECL_(A6, SIG_EXPR_LIST_PTR(USB11BDN), SIG_EXPR_LIST_PTR(USB2BDN),
SIG_EXPR_LIST_PTR(USB2BHDN));
FUNC_GROUP_DECL(USB11BHID, B6, A6);
FUNC_GROUP_DECL(USB2BD, B6, A6);
FUNC_GROUP_DECL(USB2BH, B6, A6);
/* Pins, groups and functions are sort(1):ed alphabetically for sanity */
static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
@ -1743,6 +1785,9 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(A3),
ASPEED_PINCTRL_PIN(A4),
ASPEED_PINCTRL_PIN(A5),
ASPEED_PINCTRL_PIN(A6),
ASPEED_PINCTRL_PIN(A7),
ASPEED_PINCTRL_PIN(A8),
ASPEED_PINCTRL_PIN(A9),
ASPEED_PINCTRL_PIN(AA1),
ASPEED_PINCTRL_PIN(AA19),
@ -1777,6 +1822,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(B3),
ASPEED_PINCTRL_PIN(B4),
ASPEED_PINCTRL_PIN(B5),
ASPEED_PINCTRL_PIN(B6),
ASPEED_PINCTRL_PIN(B9),
ASPEED_PINCTRL_PIN(C1),
ASPEED_PINCTRL_PIN(C11),
@ -2111,6 +2157,11 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = {
ASPEED_PINCTRL_GROUP(TXD3),
ASPEED_PINCTRL_GROUP(TXD4),
ASPEED_PINCTRL_GROUP(UART6),
ASPEED_PINCTRL_GROUP(USB11BHID),
ASPEED_PINCTRL_GROUP(USB2AD),
ASPEED_PINCTRL_GROUP(USB2AH),
ASPEED_PINCTRL_GROUP(USB2BD),
ASPEED_PINCTRL_GROUP(USB2BH),
ASPEED_PINCTRL_GROUP(USBCKI),
ASPEED_PINCTRL_GROUP(VGABIOSROM),
ASPEED_PINCTRL_GROUP(VGAHS),
@ -2275,6 +2326,11 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
ASPEED_PINCTRL_FUNC(TXD3),
ASPEED_PINCTRL_FUNC(TXD4),
ASPEED_PINCTRL_FUNC(UART6),
ASPEED_PINCTRL_FUNC(USB11BHID),
ASPEED_PINCTRL_FUNC(USB2AD),
ASPEED_PINCTRL_FUNC(USB2AH),
ASPEED_PINCTRL_FUNC(USB2BD),
ASPEED_PINCTRL_FUNC(USB2BH),
ASPEED_PINCTRL_FUNC(USBCKI),
ASPEED_PINCTRL_FUNC(VGABIOSROM),
ASPEED_PINCTRL_FUNC(VGAHS),
@ -2436,7 +2492,7 @@ static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
.nconfigs = ARRAY_SIZE(aspeed_g5_configs),
};
static struct pinmux_ops aspeed_g5_pinmux_ops = {
static const struct pinmux_ops aspeed_g5_pinmux_ops = {
.get_functions_count = aspeed_pinmux_get_fn_count,
.get_function_name = aspeed_pinmux_get_fn_name,
.get_function_groups = aspeed_pinmux_get_fn_groups,
@ -2445,7 +2501,7 @@ static struct pinmux_ops aspeed_g5_pinmux_ops = {
.strict = true,
};
static struct pinctrl_ops aspeed_g5_pinctrl_ops = {
static const struct pinctrl_ops aspeed_g5_pinctrl_ops = {
.get_groups_count = aspeed_pinctrl_get_groups_count,
.get_group_name = aspeed_pinctrl_get_group_name,
.get_group_pins = aspeed_pinctrl_get_group_pins,
@ -2454,7 +2510,7 @@ static struct pinctrl_ops aspeed_g5_pinctrl_ops = {
.dt_free_map = pinctrl_utils_free_map,
};
static struct pinconf_ops aspeed_g5_conf_ops = {
static const struct pinconf_ops aspeed_g5_conf_ops = {
.is_generic = true,
.pin_config_get = aspeed_pin_config_get,
.pin_config_set = aspeed_pin_config_set,

21
drivers/pinctrl/aspeed/pinctrl-aspeed.c
View file

@ -213,6 +213,27 @@ static int aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP2)
continue;
/* On AST2500, Set bits in SCU7C are cleared from SCU70 */
if (desc->ip == ASPEED_IP_SCU && desc->reg == HW_STRAP1) {
unsigned int rev_id;
ret = regmap_read(maps[ASPEED_IP_SCU],
HW_REVISION_ID, &rev_id);
if (ret < 0)
return ret;
if (0x04 == (rev_id >> 24)) {
u32 value = ~val & desc->mask;
if (value) {
ret = regmap_write(maps[desc->ip],
HW_REVISION_ID, value);
if (ret < 0)
return ret;
}
}
}
ret = regmap_update_bits(maps[desc->ip], desc->reg,
desc->mask, val);

1
drivers/pinctrl/aspeed/pinctrl-aspeed.h
View file

@ -251,6 +251,7 @@
#define SCU3C 0x3C /* System Reset Control/Status Register */
#define SCU48 0x48 /* MAC Interface Clock Delay Setting */
#define HW_STRAP1 0x70 /* AST2400 strapping is 33 bits, is split */
#define HW_REVISION_ID 0x7C /* Silicon revision ID register */
#define SCU80 0x80 /* Multi-function Pin Control #1 */
#define SCU84 0x84 /* Multi-function Pin Control #2 */
#define SCU88 0x88 /* Multi-function Pin Control #3 */

2
drivers/pinctrl/bcm/pinctrl-bcm281xx.c
View file

@ -1384,7 +1384,7 @@ static int bcm281xx_pinctrl_pin_config_set(struct pinctrl_dev *pctldev,
return 0;
}
static struct pinconf_ops bcm281xx_pinctrl_pinconf_ops = {
static const struct pinconf_ops bcm281xx_pinctrl_pinconf_ops = {
.pin_config_get = bcm281xx_pinctrl_pin_config_get,
.pin_config_set = bcm281xx_pinctrl_pin_config_set,
};

31
drivers/pinctrl/bcm/pinctrl-bcm2835.c
View file

@ -92,7 +92,6 @@ struct bcm2835_pinctrl {
struct gpio_chip gpio_chip;
struct pinctrl_gpio_range gpio_range;
int irq_group[BCM2835_NUM_IRQS];
spinlock_t irq_lock[BCM2835_NUM_BANKS];
};
@ -353,7 +352,7 @@ static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
return pinctrl_gpio_direction_output(chip->base + offset);
}
static struct gpio_chip bcm2835_gpio_chip = {
static const struct gpio_chip bcm2835_gpio_chip = {
.label = MODULE_NAME,
.owner = THIS_MODULE,
.request = gpiochip_generic_request,
@ -400,7 +399,7 @@ static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
for (i = 0; i < ARRAY_SIZE(pc->irq); i++) {
if (pc->irq[i] == irq) {
group = pc->irq_group[i];
group = i;
break;
}
}
@ -692,8 +691,7 @@ static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
struct pinctrl_map *map = *maps;
if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
dev_err(pc->dev, "%s: invalid brcm,function %d\n",
of_node_full_name(np), fnum);
dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
return -EINVAL;
}
@ -713,8 +711,7 @@ static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
unsigned long *configs;
if (pull > 2) {
dev_err(pc->dev, "%s: invalid brcm,pull %d\n",
of_node_full_name(np), pull);
dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
return -EINVAL;
}
@ -745,8 +742,7 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
pins = of_find_property(np, "brcm,pins", NULL);
if (!pins) {
dev_err(pc->dev, "%s: missing brcm,pins property\n",
of_node_full_name(np));
dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
return -EINVAL;
}
@ -755,8 +751,8 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
if (!funcs && !pulls) {
dev_err(pc->dev,
"%s: neither brcm,function nor brcm,pull specified\n",
of_node_full_name(np));
"%pOF: neither brcm,function nor brcm,pull specified\n",
np);
return -EINVAL;
}
@ -766,15 +762,15 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
if (num_funcs > 1 && num_funcs != num_pins) {
dev_err(pc->dev,
"%s: brcm,function must have 1 or %d entries\n",
of_node_full_name(np), num_pins);
"%pOF: brcm,function must have 1 or %d entries\n",
np, num_pins);
return -EINVAL;
}
if (num_pulls > 1 && num_pulls != num_pins) {
dev_err(pc->dev,
"%s: brcm,pull must have 1 or %d entries\n",
of_node_full_name(np), num_pins);
"%pOF: brcm,pull must have 1 or %d entries\n",
np, num_pins);
return -EINVAL;
}
@ -793,8 +789,8 @@ static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
if (err)
goto out;
if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
dev_err(pc->dev, "%s: invalid brcm,pins value %d\n",
of_node_full_name(np), pin);
dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
np, pin);
err = -EINVAL;
goto out;
}
@ -1047,7 +1043,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
for (i = 0; i < BCM2835_NUM_IRQS; i++) {
pc->irq[i] = irq_of_parse_and_map(np, i);
pc->irq_group[i] = i;
if (pc->irq[i] == 0)
continue;

4
drivers/pinctrl/berlin/berlin.c
View file

@ -206,8 +206,8 @@ static int berlin_pinctrl_add_function(struct berlin_pinctrl *pctrl,
static int berlin_pinctrl_build_state(struct platform_device *pdev)
{
struct berlin_pinctrl *pctrl = platform_get_drvdata(pdev);
struct berlin_desc_group const *desc_group;
struct berlin_desc_function const *desc_function;
const struct berlin_desc_group *desc_group;
const struct berlin_desc_function *desc_function;
int i, max_functions = 0;
pctrl->nfunctions = 0;

17
drivers/pinctrl/core.c
View file

@ -264,7 +264,7 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev,
}
static int pinctrl_register_pins(struct pinctrl_dev *pctldev,
struct pinctrl_pin_desc const *pins,
const struct pinctrl_pin_desc *pins,
unsigned num_descs)
{
unsigned i;
@ -686,7 +686,7 @@ EXPORT_SYMBOL_GPL(pinctrl_generic_remove_group);
static void pinctrl_generic_free_groups(struct pinctrl_dev *pctldev)
{
struct radix_tree_iter iter;
void **slot;
void __rcu **slot;
radix_tree_for_each_slot(slot, &pctldev->pin_group_tree, &iter, 0)
radix_tree_delete(&pctldev->pin_group_tree, iter.index);
@ -907,7 +907,7 @@ static struct pinctrl_state *create_state(struct pinctrl *p,
}
static int add_setting(struct pinctrl *p, struct pinctrl_dev *pctldev,
struct pinctrl_map const *map)
const struct pinctrl_map *map)
{
struct pinctrl_state *state;
struct pinctrl_setting *setting;
@ -995,7 +995,7 @@ static struct pinctrl *create_pinctrl(struct device *dev,
const char *devname;
struct pinctrl_maps *maps_node;
int i;
struct pinctrl_map const *map;
const struct pinctrl_map *map;
int ret;
/*
@ -1321,7 +1321,7 @@ void devm_pinctrl_put(struct pinctrl *p)
}
EXPORT_SYMBOL_GPL(devm_pinctrl_put);
int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps,
bool dup)
{
int i, ret;
@ -1380,7 +1380,6 @@ int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
maps_node->maps = kmemdup(maps, sizeof(*maps) * num_maps,
GFP_KERNEL);
if (!maps_node->maps) {
pr_err("failed to duplicate mapping table\n");
kfree(maps_node);
return -ENOMEM;
}
@ -1402,13 +1401,13 @@ int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
* function will perform a shallow copy for the mapping entries.
* @num_maps: the number of maps in the mapping table
*/
int pinctrl_register_mappings(struct pinctrl_map const *maps,
int pinctrl_register_mappings(const struct pinctrl_map *maps,
unsigned num_maps)
{
return pinctrl_register_map(maps, num_maps, true);
}
void pinctrl_unregister_map(struct pinctrl_map const *map)
void pinctrl_unregister_map(const struct pinctrl_map *map)
{
struct pinctrl_maps *maps_node;
@ -1702,7 +1701,7 @@ static int pinctrl_maps_show(struct seq_file *s, void *what)
{
struct pinctrl_maps *maps_node;
int i;
struct pinctrl_map const *map;
const struct pinctrl_map *map;
seq_puts(s, "Pinctrl maps:\n");

6
drivers/pinctrl/core.h
View file

@ -179,7 +179,7 @@ struct pin_desc {
*/
struct pinctrl_maps {
struct list_head node;
struct pinctrl_map const *maps;
const struct pinctrl_map *maps;
unsigned num_maps;
};
@ -243,9 +243,9 @@ extern struct pinctrl_gpio_range *
pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev,
unsigned int pin);
int pinctrl_register_map(struct pinctrl_map const *maps, unsigned num_maps,
int pinctrl_register_map(const struct pinctrl_map *maps, unsigned num_maps,
bool dup);
void pinctrl_unregister_map(struct pinctrl_map const *map);
void pinctrl_unregister_map(const struct pinctrl_map *map);
extern int pinctrl_force_sleep(struct pinctrl_dev *pctldev);
extern int pinctrl_force_default(struct pinctrl_dev *pctldev);

9
drivers/pinctrl/devicetree.c
View file

@ -83,7 +83,6 @@ static int dt_remember_or_free_map(struct pinctrl *p, const char *statename,
/* Remember the converted mapping table entries */
dt_map = kzalloc(sizeof(*dt_map), GFP_KERNEL);
if (!dt_map) {
dev_err(p->dev, "failed to alloc struct pinctrl_dt_map\n");
dt_free_map(pctldev, map, num_maps);
return -ENOMEM;
}
@ -117,8 +116,8 @@ static int dt_to_map_one_config(struct pinctrl *p,
for (;;) {
np_pctldev = of_get_next_parent(np_pctldev);
if (!np_pctldev || of_node_is_root(np_pctldev)) {
dev_info(p->dev, "could not find pctldev for node %s, deferring probe\n",
np_config->full_name);
dev_info(p->dev, "could not find pctldev for node %pOF, deferring probe\n",
np_config);
of_node_put(np_pctldev);
/* OK let's just assume this will appear later then */
return -EPROBE_DEFER;
@ -158,10 +157,8 @@ static int dt_remember_dummy_state(struct pinctrl *p, const char *statename)
struct pinctrl_map *map;
map = kzalloc(sizeof(*map), GFP_KERNEL);
if (!map) {
dev_err(p->dev, "failed to alloc struct pinctrl_map\n");
if (!map)
return -ENOMEM;
}
/* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
map->type = PIN_MAP_TYPE_DUMMY_STATE;

7
drivers/pinctrl/freescale/Kconfig
View file

@ -103,6 +103,13 @@ config PINCTRL_IMX7D
help
Say Y here to enable the imx7d pinctrl driver
config PINCTRL_IMX7ULP
bool "IMX7ULP pinctrl driver"
depends on SOC_IMX7ULP
select PINCTRL_IMX
help
Say Y here to enable the imx7ulp pinctrl driver
config PINCTRL_VF610
bool "Freescale Vybrid VF610 pinctrl driver"
depends on SOC_VF610

1
drivers/pinctrl/freescale/Makefile
View file

@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o

131
drivers/pinctrl/freescale/pinctrl-imx.c
View file

@ -35,18 +35,6 @@
#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
#define IMX_PAD_SION 0x40000000 /* set SION */
/**
* @dev: a pointer back to containing device
* @base: the offset to the controller in virtual memory
*/
struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
void __iomem *input_sel_base;
struct imx_pinctrl_soc_info *info;
};
static inline const struct group_desc *imx_pinctrl_find_group_by_name(
struct pinctrl_dev *pctldev,
const char *name)
@ -255,111 +243,11 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
return 0;
}
static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
struct group_desc *grp;
struct imx_pin *imx_pin;
unsigned int pin, group;
u32 reg;
/* Currently implementation only for shared mux/conf register */
if (!(info->flags & SHARE_MUX_CONF_REG))
return 0;
pin_reg = &info->pin_regs[offset];
if (pin_reg->mux_reg == -1)
return -EINVAL;
/* Find the pinctrl config with GPIO mux mode for the requested pin */
for (group = 0; group < pctldev->num_groups; group++) {
grp = pinctrl_generic_get_group(pctldev, group);
if (!grp)
continue;
for (pin = 0; pin < grp->num_pins; pin++) {
imx_pin = &((struct imx_pin *)(grp->data))[pin];
if (imx_pin->pin == offset && !imx_pin->mux_mode)
goto mux_pin;
}
}
return -EINVAL;
mux_pin:
reg = readl(ipctl->base + pin_reg->mux_reg);
reg &= ~info->mux_mask;
reg |= imx_pin->config;
writel(reg, ipctl->base + pin_reg->mux_reg);
return 0;
}
static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
u32 reg;
/*
* Only Vybrid has the input/output buffer enable flags (IBE/OBE)
* They are part of the shared mux/conf register.
*/
if (!(info->flags & SHARE_MUX_CONF_REG))
return;
pin_reg = &info->pin_regs[offset];
if (pin_reg->mux_reg == -1)
return;
/* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */
reg = readl(ipctl->base + pin_reg->mux_reg);
reg &= ~0x7;
writel(reg, ipctl->base + pin_reg->mux_reg);
}
static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range, unsigned offset, bool input)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
u32 reg;
/*
* Only Vybrid has the input/output buffer enable flags (IBE/OBE)
* They are part of the shared mux/conf register.
*/
if (!(info->flags & SHARE_MUX_CONF_REG))
return 0;
pin_reg = &info->pin_regs[offset];
if (pin_reg->mux_reg == -1)
return -EINVAL;
/* IBE always enabled allows us to read the value "on the wire" */
reg = readl(ipctl->base + pin_reg->mux_reg);
if (input)
reg &= ~0x2;
else
reg |= 0x2;
writel(reg, ipctl->base + pin_reg->mux_reg);
return 0;
}
static const struct pinmux_ops imx_pmx_ops = {
struct pinmux_ops imx_pmx_ops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
.set_mux = imx_pmx_set,
.gpio_request_enable = imx_pmx_gpio_request_enable,
.gpio_disable_free = imx_pmx_gpio_disable_free,
.gpio_set_direction = imx_pmx_gpio_set_direction,
};
/* decode generic config into raw register values */
@ -563,26 +451,24 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
* do sanity check and calculate pins number
*
* First try legacy 'fsl,pins' property, then fall back to the
* generic 'pins'.
* generic 'pinmux'.
*
* Note: for generic 'pins' case, there's no CONFIG part in
* Note: for generic 'pinmux' case, there's no CONFIG part in
* the binding format.
*/
list = of_get_property(np, "fsl,pins", &size);
if (!list) {
list = of_get_property(np, "pins", &size);
list = of_get_property(np, "pinmux", &size);
if (!list) {
dev_err(info->dev,
"no fsl,pins and pins property in node %s\n",
np->full_name);
"no fsl,pins and pins property in node %pOF\n", np);
return -EINVAL;
}
}
/* we do not check return since it's safe node passed down */
if (!size || size % pin_size) {
dev_err(info->dev, "Invalid fsl,pins or pins property in node %s\n",
np->full_name);
dev_err(info->dev, "Invalid fsl,pins or pins property in node %pOF\n", np);
return -EINVAL;
}
@ -666,7 +552,7 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
func->name = np->name;
func->num_group_names = of_get_child_count(np);
if (func->num_group_names == 0) {
dev_err(info->dev, "no groups defined in %s\n", np->full_name);
dev_err(info->dev, "no groups defined in %pOF\n", np);
return -EINVAL;
}
func->group_names = devm_kcalloc(info->dev, func->num_group_names,
@ -862,6 +748,9 @@ int imx_pinctrl_probe(struct platform_device *pdev,
imx_pinctrl_desc->custom_params = info->custom_params;
imx_pinctrl_desc->num_custom_params = info->num_custom_params;
/* platform specific callback */
imx_pmx_ops.gpio_set_direction = info->gpio_set_direction;
mutex_init(&info->mutex);
ipctl->info = info;

20
drivers/pinctrl/freescale/pinctrl-imx.h
View file

@ -16,9 +16,12 @@
#define __DRIVERS_PINCTRL_IMX_H
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinmux.h>
struct platform_device;
extern struct pinmux_ops imx_pmx_ops;
/**
* struct imx_pin - describes a single i.MX pin
* @pin: the pin_id of this pin
@ -76,6 +79,23 @@ struct imx_pinctrl_soc_info {
unsigned int num_decodes;
void (*fixup)(unsigned long *configs, unsigned int num_configs,
u32 *raw_config);
int (*gpio_set_direction)(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset,
bool input);
};
/**
* @dev: a pointer back to containing device
* @base: the offset to the controller in virtual memory
*/
struct imx_pinctrl {
struct device *dev;
struct pinctrl_dev *pctl;
void __iomem *base;
void __iomem *input_sel_base;
struct imx_pinctrl_soc_info *info;
};
#define IMX_CFG_PARAMS_DECODE(p, m, o) \

2
drivers/pinctrl/freescale/pinctrl-imx23.c
View file

@ -257,7 +257,7 @@ static const struct pinctrl_pin_desc imx23_pins[] = {
MXS_PINCTRL_PIN(EMI_CLKN),
};
static struct mxs_regs imx23_regs = {
static const struct mxs_regs imx23_regs = {
.muxsel = 0x100,
.drive = 0x200,
.pull = 0x400,

2
drivers/pinctrl/freescale/pinctrl-imx28.c
View file

@ -373,7 +373,7 @@ static const struct pinctrl_pin_desc imx28_pins[] = {
MXS_PINCTRL_PIN(EMI_CKE),
};
static struct mxs_regs imx28_regs = {
static const struct mxs_regs imx28_regs = {
.muxsel = 0x100,
.drive = 0x300,
.pull = 0x600,

364
drivers/pinctrl/freescale/pinctrl-imx7ulp.c Normal file
View file

@ -0,0 +1,364 @@
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright (C) 2017 NXP
*
* Author: Dong Aisheng <aisheng.dong@nxp.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-imx.h"
enum imx7ulp_pads {
IMX7ULP_PAD_PTC0 = 0,
IMX7ULP_PAD_PTC1,
IMX7ULP_PAD_PTC2,
IMX7ULP_PAD_PTC3,
IMX7ULP_PAD_PTC4,
IMX7ULP_PAD_PTC5,
IMX7ULP_PAD_PTC6,
IMX7ULP_PAD_PTC7,
IMX7ULP_PAD_PTC8,
IMX7ULP_PAD_PTC9,
IMX7ULP_PAD_PTC10,
IMX7ULP_PAD_PTC11,
IMX7ULP_PAD_PTC12,
IMX7ULP_PAD_PTC13,
IMX7ULP_PAD_PTC14,
IMX7ULP_PAD_PTC15,
IMX7ULP_PAD_PTC16,
IMX7ULP_PAD_PTC17,
IMX7ULP_PAD_PTC18,
IMX7ULP_PAD_PTC19,
IMX7ULP_PAD_RESERVE0,
IMX7ULP_PAD_RESERVE1,
IMX7ULP_PAD_RESERVE2,
IMX7ULP_PAD_RESERVE3,
IMX7ULP_PAD_RESERVE4,
IMX7ULP_PAD_RESERVE5,
IMX7ULP_PAD_RESERVE6,
IMX7ULP_PAD_RESERVE7,
IMX7ULP_PAD_RESERVE8,
IMX7ULP_PAD_RESERVE9,
IMX7ULP_PAD_RESERVE10,
IMX7ULP_PAD_RESERVE11,
IMX7ULP_PAD_PTD0,
IMX7ULP_PAD_PTD1,
IMX7ULP_PAD_PTD2,
IMX7ULP_PAD_PTD3,
IMX7ULP_PAD_PTD4,
IMX7ULP_PAD_PTD5,
IMX7ULP_PAD_PTD6,
IMX7ULP_PAD_PTD7,
IMX7ULP_PAD_PTD8,
IMX7ULP_PAD_PTD9,
IMX7ULP_PAD_PTD10,
IMX7ULP_PAD_PTD11,
IMX7ULP_PAD_RESERVE12,
IMX7ULP_PAD_RESERVE13,
IMX7ULP_PAD_RESERVE14,
IMX7ULP_PAD_RESERVE15,
IMX7ULP_PAD_RESERVE16,
IMX7ULP_PAD_RESERVE17,
IMX7ULP_PAD_RESERVE18,
IMX7ULP_PAD_RESERVE19,
IMX7ULP_PAD_RESERVE20,
IMX7ULP_PAD_RESERVE21,
IMX7ULP_PAD_RESERVE22,
IMX7ULP_PAD_RESERVE23,
IMX7ULP_PAD_RESERVE24,
IMX7ULP_PAD_RESERVE25,
IMX7ULP_PAD_RESERVE26,
IMX7ULP_PAD_RESERVE27,
IMX7ULP_PAD_RESERVE28,
IMX7ULP_PAD_RESERVE29,
IMX7ULP_PAD_RESERVE30,
IMX7ULP_PAD_RESERVE31,
IMX7ULP_PAD_PTE0,
IMX7ULP_PAD_PTE1,
IMX7ULP_PAD_PTE2,
IMX7ULP_PAD_PTE3,
IMX7ULP_PAD_PTE4,
IMX7ULP_PAD_PTE5,
IMX7ULP_PAD_PTE6,
IMX7ULP_PAD_PTE7,
IMX7ULP_PAD_PTE8,
IMX7ULP_PAD_PTE9,
IMX7ULP_PAD_PTE10,
IMX7ULP_PAD_PTE11,
IMX7ULP_PAD_PTE12,
IMX7ULP_PAD_PTE13,
IMX7ULP_PAD_PTE14,
IMX7ULP_PAD_PTE15,
IMX7ULP_PAD_RESERVE32,
IMX7ULP_PAD_RESERVE33,
IMX7ULP_PAD_RESERVE34,
IMX7ULP_PAD_RESERVE35,
IMX7ULP_PAD_RESERVE36,
IMX7ULP_PAD_RESERVE37,
IMX7ULP_PAD_RESERVE38,
IMX7ULP_PAD_RESERVE39,
IMX7ULP_PAD_RESERVE40,
IMX7ULP_PAD_RESERVE41,
IMX7ULP_PAD_RESERVE42,
IMX7ULP_PAD_RESERVE43,
IMX7ULP_PAD_RESERVE44,
IMX7ULP_PAD_RESERVE45,
IMX7ULP_PAD_RESERVE46,
IMX7ULP_PAD_RESERVE47,
IMX7ULP_PAD_PTF0,
IMX7ULP_PAD_PTF1,
IMX7ULP_PAD_PTF2,
IMX7ULP_PAD_PTF3,
IMX7ULP_PAD_PTF4,
IMX7ULP_PAD_PTF5,
IMX7ULP_PAD_PTF6,
IMX7ULP_PAD_PTF7,
IMX7ULP_PAD_PTF8,
IMX7ULP_PAD_PTF9,
IMX7ULP_PAD_PTF10,
IMX7ULP_PAD_PTF11,
IMX7ULP_PAD_PTF12,
IMX7ULP_PAD_PTF13,
IMX7ULP_PAD_PTF14,
IMX7ULP_PAD_PTF15,
IMX7ULP_PAD_PTF16,
IMX7ULP_PAD_PTF17,
IMX7ULP_PAD_PTF18,
IMX7ULP_PAD_PTF19,
};
/* Pad names for the pinmux subsystem */
static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = {
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC0),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC1),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC2),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC3),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC4),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC5),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC6),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC7),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC8),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC9),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC10),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC11),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC12),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC13),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC14),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC15),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC16),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC17),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC18),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTC19),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE0),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE1),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE2),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE3),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE4),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE5),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE6),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE7),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE8),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE9),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE10),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE11),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD0),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD1),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD2),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD3),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD4),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD5),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD6),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD7),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD8),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD9),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD10),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTD11),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE12),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE13),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE14),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE15),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE16),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE17),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE18),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE19),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE20),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE21),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE22),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE23),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE24),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE25),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE26),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE27),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE28),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE29),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE30),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE31),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE0),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE1),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE2),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE3),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE4),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE5),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE6),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE7),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE8),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE9),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE10),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE11),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE12),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE13),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE14),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTE15),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE32),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE33),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE34),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE35),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE36),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE37),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE38),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE39),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE40),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE41),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE42),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE43),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE44),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE45),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE46),
IMX_PINCTRL_PIN(IMX7ULP_PAD_RESERVE47),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF0),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF1),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF2),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF3),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF4),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF5),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF6),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF7),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF8),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF9),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF10),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF11),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF12),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF13),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF14),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF15),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF16),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF17),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF18),
IMX_PINCTRL_PIN(IMX7ULP_PAD_PTF19),
};
#define BM_OBE_ENABLED BIT(17)
#define BM_IBE_ENABLED BIT(16)
#define BM_LK_ENABLED BIT(15)
#define BM_MUX_MODE 0xf00
#define BP_MUX_MODE 8
#define BM_PULL_ENABLED BIT(1)
struct imx_cfg_params_decode imx7ulp_cfg_decodes[] = {
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_STRENGTH, BIT(6), 6),
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_PUSH_PULL, BIT(5), 5),
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_SLEW_RATE, BIT(2), 2),
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_DISABLE, BIT(1), 1),
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_BIAS_PULL_UP, BIT(0), 0),
IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_DRIVE_OPEN_DRAIN, BIT(5), 5),
IMX_CFG_PARAMS_DECODE_INVERT(PIN_CONFIG_BIAS_PULL_DOWN, BIT(0), 0),
};
static void imx7ulp_cfg_params_fixup(unsigned long *configs,
unsigned int num_configs,
u32 *raw_config)
{
enum pin_config_param param;
u32 param_val;
int i;
/* lock field disabled */
*raw_config &= ~BM_LK_ENABLED;
for (i = 0; i < num_configs; i++) {
param = pinconf_to_config_param(configs[i]);
param_val = pinconf_to_config_argument(configs[i]);
if ((param == PIN_CONFIG_BIAS_PULL_UP) ||
(param == PIN_CONFIG_BIAS_PULL_DOWN)) {
/* pull enabled */
*raw_config |= BM_PULL_ENABLED;
return;
}
}
}
static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset, bool input)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
u32 reg;
pin_reg = &info->pin_regs[offset];
if (pin_reg->mux_reg == -1)
return -EINVAL;
reg = readl(ipctl->base + pin_reg->mux_reg);
if (input)
reg = (reg & ~BM_OBE_ENABLED) | BM_IBE_ENABLED;
else
reg = (reg & ~BM_IBE_ENABLED) | BM_OBE_ENABLED;
writel(reg, ipctl->base + pin_reg->mux_reg);
return 0;
}
static struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
.pins = imx7ulp_pinctrl_pads,
.npins = ARRAY_SIZE(imx7ulp_pinctrl_pads),
.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
.gpio_set_direction = imx7ulp_pmx_gpio_set_direction,
.mux_mask = BM_MUX_MODE,
.mux_shift = BP_MUX_MODE,
.generic_pinconf = true,
.decodes = imx7ulp_cfg_decodes,
.num_decodes = ARRAY_SIZE(imx7ulp_cfg_decodes),
.fixup = imx7ulp_cfg_params_fixup,
};
static const struct of_device_id imx7ulp_pinctrl_of_match[] = {
{ .compatible = "fsl,imx7ulp-iomuxc1", },
{ /* sentinel */ }
};
static int imx7ulp_pinctrl_probe(struct platform_device *pdev)
{
return imx_pinctrl_probe(pdev, &imx7ulp_pinctrl_info);
}
static struct platform_driver imx7ulp_pinctrl_driver = {
.driver = {
.name = "imx7ulp-pinctrl",
.of_match_table = of_match_ptr(imx7ulp_pinctrl_of_match),
.suppress_bind_attrs = true,
},
.probe = imx7ulp_pinctrl_probe,
};
static int __init imx7ulp_pinctrl_init(void)
{
return platform_driver_register(&imx7ulp_pinctrl_driver);
}
arch_initcall(imx7ulp_pinctrl_init);

25
drivers/pinctrl/freescale/pinctrl-vf610.c
View file

@ -295,10 +295,35 @@ static const struct pinctrl_pin_desc vf610_pinctrl_pads[] = {
IMX_PINCTRL_PIN(VF610_PAD_PTA7),
};
static int vf610_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned offset, bool input)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
u32 reg;
pin_reg = &info->pin_regs[offset];
if (pin_reg->mux_reg == -1)
return -EINVAL;
/* IBE always enabled allows us to read the value "on the wire" */
reg = readl(ipctl->base + pin_reg->mux_reg);
if (input)
reg &= ~0x2;
else
reg |= 0x2;
writel(reg, ipctl->base + pin_reg->mux_reg);
return 0;
}
static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
.pins = vf610_pinctrl_pads,
.npins = ARRAY_SIZE(vf610_pinctrl_pads),
.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
.gpio_set_direction = vf610_pmx_gpio_set_direction,
.mux_mask = 0x700000,
.mux_shift = 20,
};

19
drivers/pinctrl/intel/Kconfig
View file

@ -1,6 +1,7 @@
#
# Intel pin control drivers
#
if (X86 || COMPILE_TEST)
config PINCTRL_BAYTRAIL
bool "Intel Baytrail GPIO pin control"
@ -64,6 +65,14 @@ config PINCTRL_CANNONLAKE
This pinctrl driver provides an interface that allows configuring
of Intel Cannon Lake PCH pins and using them as GPIOs.
config PINCTRL_DENVERTON
tristate "Intel Denverton pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL
help
This pinctrl driver provides an interface that allows configuring
of Intel Denverton SoC pins and using them as GPIOs.
config PINCTRL_GEMINILAKE
tristate "Intel Gemini Lake SoC pinctrl and GPIO driver"
depends on ACPI
@ -72,6 +81,14 @@ config PINCTRL_GEMINILAKE
This pinctrl driver provides an interface that allows configuring
of Intel Gemini Lake SoC pins and using them as GPIOs.
config PINCTRL_LEWISBURG
tristate "Intel Lewisburg pinctrl and GPIO driver"
depends on ACPI
select PINCTRL_INTEL
help
This pinctrl driver provides an interface that allows configuring
of Intel Lewisburg pins and using them as GPIOs.
config PINCTRL_SUNRISEPOINT
tristate "Intel Sunrisepoint pinctrl and GPIO driver"
depends on ACPI
@ -80,3 +97,5 @@ config PINCTRL_SUNRISEPOINT
Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
provides an interface that allows configuring of PCH pins and
using them as GPIOs.
endif

2
drivers/pinctrl/intel/Makefile
View file

@ -6,5 +6,7 @@ obj-$(CONFIG_PINCTRL_MERRIFIELD) += pinctrl-merrifield.o
obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
obj-$(CONFIG_PINCTRL_BROXTON) += pinctrl-broxton.o
obj-$(CONFIG_PINCTRL_CANNONLAKE) += pinctrl-cannonlake.o
obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o
obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o
obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o
obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o

4
drivers/pinctrl/intel/pinctrl-baytrail.c
View file

@ -981,12 +981,12 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
*/
value = readl(reg) & BYT_PIN_MUX;
gpio_mux = byt_get_gpio_mux(vg, offset);
if (WARN_ON(gpio_mux != value)) {
if (gpio_mux != value) {
value = readl(reg) & ~BYT_PIN_MUX;
value |= gpio_mux;
writel(value, reg);
dev_warn(&vg->pdev->dev,
dev_warn(&vg->pdev->dev, FW_BUG
"pin %u forcibly re-configured as GPIO\n", offset);
}

424
drivers/pinctrl/intel/pinctrl-cannonlake.c
View file

@ -2,7 +2,8 @@
* Intel Cannon Lake PCH pinctrl/GPIO driver
*
* Copyright (C) 2017, Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
* Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
* Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -42,6 +43,426 @@
.ngpps = ARRAY_SIZE(g), \
}
/* Cannon Lake-H */
static const struct pinctrl_pin_desc cnlh_pins[] = {
/* GPP_A */
PINCTRL_PIN(0, "RCINB"),
PINCTRL_PIN(1, "LAD_0"),
PINCTRL_PIN(2, "LAD_1"),
PINCTRL_PIN(3, "LAD_2"),
PINCTRL_PIN(4, "LAD_3"),
PINCTRL_PIN(5, "LFRAMEB"),
PINCTRL_PIN(6, "SERIRQ"),
PINCTRL_PIN(7, "PIRQAB"),
PINCTRL_PIN(8, "CLKRUNB"),
PINCTRL_PIN(9, "CLKOUT_LPC_0"),
PINCTRL_PIN(10, "CLKOUT_LPC_1"),
PINCTRL_PIN(11, "PMEB"),
PINCTRL_PIN(12, "BM_BUSYB"),
PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
PINCTRL_PIN(14, "SUS_STATB"),
PINCTRL_PIN(15, "SUSACKB"),
PINCTRL_PIN(16, "CLKOUT_48"),
PINCTRL_PIN(17, "SD_VDD1_PWR_EN_B"),
PINCTRL_PIN(18, "ISH_GP_0"),
PINCTRL_PIN(19, "ISH_GP_1"),
PINCTRL_PIN(20, "ISH_GP_2"),
PINCTRL_PIN(21, "ISH_GP_3"),
PINCTRL_PIN(22, "ISH_GP_4"),
PINCTRL_PIN(23, "ISH_GP_5"),
PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"),
/* GPP_B */
PINCTRL_PIN(25, "GSPI0_CS1B"),
PINCTRL_PIN(26, "GSPI1_CS1B"),
PINCTRL_PIN(27, "VRALERTB"),
PINCTRL_PIN(28, "CPU_GP_2"),
PINCTRL_PIN(29, "CPU_GP_3"),
PINCTRL_PIN(30, "SRCCLKREQB_0"),
PINCTRL_PIN(31, "SRCCLKREQB_1"),
PINCTRL_PIN(32, "SRCCLKREQB_2"),
PINCTRL_PIN(33, "SRCCLKREQB_3"),
PINCTRL_PIN(34, "SRCCLKREQB_4"),
PINCTRL_PIN(35, "SRCCLKREQB_5"),
PINCTRL_PIN(36, "SSP_MCLK"),
PINCTRL_PIN(37, "SLP_S0B"),
PINCTRL_PIN(38, "PLTRSTB"),
PINCTRL_PIN(39, "SPKR"),
PINCTRL_PIN(40, "GSPI0_CS0B"),
PINCTRL_PIN(41, "GSPI0_CLK"),
PINCTRL_PIN(42, "GSPI0_MISO"),
PINCTRL_PIN(43, "GSPI0_MOSI"),
PINCTRL_PIN(44, "GSPI1_CS0B"),
PINCTRL_PIN(45, "GSPI1_CLK"),
PINCTRL_PIN(46, "GSPI1_MISO"),
PINCTRL_PIN(47, "GSPI1_MOSI"),
PINCTRL_PIN(48, "SML1ALERTB"),
PINCTRL_PIN(49, "GSPI0_CLK_LOOPBK"),
PINCTRL_PIN(50, "GSPI1_CLK_LOOPBK"),
/* GPP_C */
PINCTRL_PIN(51, "SMBCLK"),
PINCTRL_PIN(52, "SMBDATA"),
PINCTRL_PIN(53, "SMBALERTB"),
PINCTRL_PIN(54, "SML0CLK"),
PINCTRL_PIN(55, "SML0DATA"),
PINCTRL_PIN(56, "SML0ALERTB"),
PINCTRL_PIN(57, "SML1CLK"),
PINCTRL_PIN(58, "SML1DATA"),
PINCTRL_PIN(59, "UART0_RXD"),
PINCTRL_PIN(60, "UART0_TXD"),
PINCTRL_PIN(61, "UART0_RTSB"),
PINCTRL_PIN(62, "UART0_CTSB"),
PINCTRL_PIN(63, "UART1_RXD"),
PINCTRL_PIN(64, "UART1_TXD"),
PINCTRL_PIN(65, "UART1_RTSB"),
PINCTRL_PIN(66, "UART1_CTSB"),
PINCTRL_PIN(67, "I2C0_SDA"),
PINCTRL_PIN(68, "I2C0_SCL"),
PINCTRL_PIN(69, "I2C1_SDA"),
PINCTRL_PIN(70, "I2C1_SCL"),
PINCTRL_PIN(71, "UART2_RXD"),
PINCTRL_PIN(72, "UART2_TXD"),
PINCTRL_PIN(73, "UART2_RTSB"),
PINCTRL_PIN(74, "UART2_CTSB"),
/* GPP_D */
PINCTRL_PIN(75, "SPI1_CSB"),
PINCTRL_PIN(76, "SPI1_CLK"),
PINCTRL_PIN(77, "SPI1_MISO_IO_1"),
PINCTRL_PIN(78, "SPI1_MOSI_IO_0"),
PINCTRL_PIN(79, "ISH_I2C2_SDA"),
PINCTRL_PIN(80, "SSP2_SFRM"),
PINCTRL_PIN(81, "SSP2_TXD"),
PINCTRL_PIN(82, "SSP2_RXD"),
PINCTRL_PIN(83, "SSP2_SCLK"),
PINCTRL_PIN(84, "ISH_SPI_CSB"),
PINCTRL_PIN(85, "ISH_SPI_CLK"),
PINCTRL_PIN(86, "ISH_SPI_MISO"),
PINCTRL_PIN(87, "ISH_SPI_MOSI"),
PINCTRL_PIN(88, "ISH_UART0_RXD"),
PINCTRL_PIN(89, "ISH_UART0_TXD"),
PINCTRL_PIN(90, "ISH_UART0_RTSB"),
PINCTRL_PIN(91, "ISH_UART0_CTSB"),
PINCTRL_PIN(92, "DMIC_CLK_1"),
PINCTRL_PIN(93, "DMIC_DATA_1"),
PINCTRL_PIN(94, "DMIC_CLK_0"),
PINCTRL_PIN(95, "DMIC_DATA_0"),
PINCTRL_PIN(96, "SPI1_IO_2"),
PINCTRL_PIN(97, "SPI1_IO_3"),
PINCTRL_PIN(98, "ISH_I2C2_SCL"),
/* GPP_G */
PINCTRL_PIN(99, "SD3_CMD"),
PINCTRL_PIN(100, "SD3_D0"),
PINCTRL_PIN(101, "SD3_D1"),
PINCTRL_PIN(102, "SD3_D2"),
PINCTRL_PIN(103, "SD3_D3"),
PINCTRL_PIN(104, "SD3_CDB"),
PINCTRL_PIN(105, "SD3_CLK"),
PINCTRL_PIN(106, "SD3_WP"),
/* AZA */
PINCTRL_PIN(107, "HDA_BCLK"),
PINCTRL_PIN(108, "HDA_RSTB"),
PINCTRL_PIN(109, "HDA_SYNC"),
PINCTRL_PIN(110, "HDA_SDO"),
PINCTRL_PIN(111, "HDA_SDI_0"),
PINCTRL_PIN(112, "HDA_SDI_1"),
PINCTRL_PIN(113, "SSP1_SFRM"),
PINCTRL_PIN(114, "SSP1_TXD"),
/* vGPIO */
PINCTRL_PIN(115, "CNV_BTEN"),
PINCTRL_PIN(116, "CNV_GNEN"),
PINCTRL_PIN(117, "CNV_WFEN"),
PINCTRL_PIN(118, "CNV_WCEN"),
PINCTRL_PIN(119, "CNV_BT_HOST_WAKEB"),
PINCTRL_PIN(120, "vCNV_GNSS_HOST_WAKEB"),
PINCTRL_PIN(121, "vSD3_CD_B"),
PINCTRL_PIN(122, "CNV_BT_IF_SELECT"),
PINCTRL_PIN(123, "vCNV_BT_UART_TXD"),
PINCTRL_PIN(124, "vCNV_BT_UART_RXD"),
PINCTRL_PIN(125, "vCNV_BT_UART_CTS_B"),
PINCTRL_PIN(126, "vCNV_BT_UART_RTS_B"),
PINCTRL_PIN(127, "vCNV_MFUART1_TXD"),
PINCTRL_PIN(128, "vCNV_MFUART1_RXD"),
PINCTRL_PIN(129, "vCNV_MFUART1_CTS_B"),
PINCTRL_PIN(130, "vCNV_MFUART1_RTS_B"),
PINCTRL_PIN(131, "vCNV_GNSS_UART_TXD"),
PINCTRL_PIN(132, "vCNV_GNSS_UART_RXD"),
PINCTRL_PIN(133, "vCNV_GNSS_UART_CTS_B"),
PINCTRL_PIN(134, "vCNV_GNSS_UART_RTS_B"),
PINCTRL_PIN(135, "vUART0_TXD"),
PINCTRL_PIN(136, "vUART0_RXD"),
PINCTRL_PIN(137, "vUART0_CTS_B"),
PINCTRL_PIN(138, "vUART0_RTSB"),
PINCTRL_PIN(139, "vISH_UART0_TXD"),
PINCTRL_PIN(140, "vISH_UART0_RXD"),
PINCTRL_PIN(141, "vISH_UART0_CTS_B"),
PINCTRL_PIN(142, "vISH_UART0_RTSB"),
PINCTRL_PIN(143, "vISH_UART1_TXD"),
PINCTRL_PIN(144, "vISH_UART1_RXD"),
PINCTRL_PIN(145, "vISH_UART1_CTS_B"),
PINCTRL_PIN(146, "vISH_UART1_RTS_B"),
PINCTRL_PIN(147, "vCNV_BT_I2S_BCLK"),
PINCTRL_PIN(148, "vCNV_BT_I2S_WS_SYNC"),
PINCTRL_PIN(149, "vCNV_BT_I2S_SDO"),
PINCTRL_PIN(150, "vCNV_BT_I2S_SDI"),
PINCTRL_PIN(151, "vSSP2_SCLK"),
PINCTRL_PIN(152, "vSSP2_SFRM"),
PINCTRL_PIN(153, "vSSP2_TXD"),
PINCTRL_PIN(154, "vSSP2_RXD"),
/* GPP_K */
PINCTRL_PIN(155, "FAN_TACH_0"),
PINCTRL_PIN(156, "FAN_TACH_1"),
PINCTRL_PIN(157, "FAN_TACH_2"),
PINCTRL_PIN(158, "FAN_TACH_3"),
PINCTRL_PIN(159, "FAN_TACH_4"),
PINCTRL_PIN(160, "FAN_TACH_5"),
PINCTRL_PIN(161, "FAN_TACH_6"),
PINCTRL_PIN(162, "FAN_TACH_7"),
PINCTRL_PIN(163, "FAN_PWM_0"),
PINCTRL_PIN(164, "FAN_PWM_1"),
PINCTRL_PIN(165, "FAN_PWM_2"),
PINCTRL_PIN(166, "FAN_PWM_3"),
PINCTRL_PIN(167, "GSXDOUT"),
PINCTRL_PIN(168, "GSXSLOAD"),
PINCTRL_PIN(169, "GSXDIN"),
PINCTRL_PIN(170, "GSXSRESETB"),
PINCTRL_PIN(171, "GSXCLK"),
PINCTRL_PIN(172, "ADR_COMPLETE"),
PINCTRL_PIN(173, "NMIB"),
PINCTRL_PIN(174, "SMIB"),
PINCTRL_PIN(175, "CORE_VID_0"),
PINCTRL_PIN(176, "CORE_VID_1"),
PINCTRL_PIN(177, "IMGCLKOUT_0"),
PINCTRL_PIN(178, "IMGCLKOUT_1"),
/* GPP_H */
PINCTRL_PIN(179, "SRCCLKREQB_6"),
PINCTRL_PIN(180, "SRCCLKREQB_7"),
PINCTRL_PIN(181, "SRCCLKREQB_8"),
PINCTRL_PIN(182, "SRCCLKREQB_9"),
PINCTRL_PIN(183, "SRCCLKREQB_10"),
PINCTRL_PIN(184, "SRCCLKREQB_11"),
PINCTRL_PIN(185, "SRCCLKREQB_12"),
PINCTRL_PIN(186, "SRCCLKREQB_13"),
PINCTRL_PIN(187, "SRCCLKREQB_14"),
PINCTRL_PIN(188, "SRCCLKREQB_15"),
PINCTRL_PIN(189, "SML2CLK"),
PINCTRL_PIN(190, "SML2DATA"),
PINCTRL_PIN(191, "SML2ALERTB"),
PINCTRL_PIN(192, "SML3CLK"),
PINCTRL_PIN(193, "SML3DATA"),
PINCTRL_PIN(194, "SML3ALERTB"),
PINCTRL_PIN(195, "SML4CLK"),
PINCTRL_PIN(196, "SML4DATA"),
PINCTRL_PIN(197, "SML4ALERTB"),
PINCTRL_PIN(198, "ISH_I2C0_SDA"),
PINCTRL_PIN(199, "ISH_I2C0_SCL"),
PINCTRL_PIN(200, "ISH_I2C1_SDA"),
PINCTRL_PIN(201, "ISH_I2C1_SCL"),
PINCTRL_PIN(202, "TIME_SYNC_0"),
/* GPP_E */
PINCTRL_PIN(203, "SATAXPCIE_0"),
PINCTRL_PIN(204, "SATAXPCIE_1"),
PINCTRL_PIN(205, "SATAXPCIE_2"),
PINCTRL_PIN(206, "CPU_GP_0"),
PINCTRL_PIN(207, "SATA_DEVSLP_0"),
PINCTRL_PIN(208, "SATA_DEVSLP_1"),
PINCTRL_PIN(209, "SATA_DEVSLP_2"),
PINCTRL_PIN(210, "CPU_GP_1"),
PINCTRL_PIN(211, "SATA_LEDB"),
PINCTRL_PIN(212, "USB2_OCB_0"),
PINCTRL_PIN(213, "USB2_OCB_1"),
PINCTRL_PIN(214, "USB2_OCB_2"),
PINCTRL_PIN(215, "USB2_OCB_3"),
/* GPP_F */
PINCTRL_PIN(216, "SATAXPCIE_3"),
PINCTRL_PIN(217, "SATAXPCIE_4"),
PINCTRL_PIN(218, "SATAXPCIE_5"),
PINCTRL_PIN(219, "SATAXPCIE_6"),
PINCTRL_PIN(220, "SATAXPCIE_7"),
PINCTRL_PIN(221, "SATA_DEVSLP_3"),
PINCTRL_PIN(222, "SATA_DEVSLP_4"),
PINCTRL_PIN(223, "SATA_DEVSLP_5"),
PINCTRL_PIN(224, "SATA_DEVSLP_6"),
PINCTRL_PIN(225, "SATA_DEVSLP_7"),
PINCTRL_PIN(226, "SATA_SCLOCK"),
PINCTRL_PIN(227, "SATA_SLOAD"),
PINCTRL_PIN(228, "SATA_SDATAOUT1"),
PINCTRL_PIN(229, "SATA_SDATAOUT0"),
PINCTRL_PIN(230, "EXT_PWR_GATEB"),
PINCTRL_PIN(231, "USB2_OCB_4"),
PINCTRL_PIN(232, "USB2_OCB_5"),
PINCTRL_PIN(233, "USB2_OCB_6"),
PINCTRL_PIN(234, "USB2_OCB_7"),
PINCTRL_PIN(235, "L_VDDEN"),
PINCTRL_PIN(236, "L_BKLTEN"),
PINCTRL_PIN(237, "L_BKLTCTL"),
PINCTRL_PIN(238, "DDPF_CTRLCLK"),
PINCTRL_PIN(239, "DDPF_CTRLDATA"),
/* SPI */
PINCTRL_PIN(240, "SPI0_IO_2"),
PINCTRL_PIN(241, "SPI0_IO_3"),
PINCTRL_PIN(242, "SPI0_MOSI_IO_0"),
PINCTRL_PIN(243, "SPI0_MISO_IO_1"),
PINCTRL_PIN(244, "SPI0_TPM_CSB"),
PINCTRL_PIN(245, "SPI0_FLASH_0_CSB"),
PINCTRL_PIN(246, "SPI0_FLASH_1_CSB"),
PINCTRL_PIN(247, "SPI0_CLK"),
PINCTRL_PIN(248, "SPI0_CLK_LOOPBK"),
/* CPU */
PINCTRL_PIN(249, "HDACPU_SDI"),
PINCTRL_PIN(250, "HDACPU_SDO"),
PINCTRL_PIN(251, "HDACPU_SCLK"),
PINCTRL_PIN(252, "PM_SYNC"),
PINCTRL_PIN(253, "PECI"),
PINCTRL_PIN(254, "CPUPWRGD"),
PINCTRL_PIN(255, "THRMTRIPB"),
PINCTRL_PIN(256, "PLTRST_CPUB"),
PINCTRL_PIN(257, "PM_DOWN"),
PINCTRL_PIN(258, "TRIGGER_IN"),
PINCTRL_PIN(259, "TRIGGER_OUT"),
/* JTAG */
PINCTRL_PIN(260, "JTAG_TDO"),
PINCTRL_PIN(261, "JTAGX"),
PINCTRL_PIN(262, "PRDYB"),
PINCTRL_PIN(263, "PREQB"),
PINCTRL_PIN(264, "CPU_TRSTB"),
PINCTRL_PIN(265, "JTAG_TDI"),
PINCTRL_PIN(266, "JTAG_TMS"),
PINCTRL_PIN(267, "JTAG_TCK"),
PINCTRL_PIN(268, "ITP_PMODE"),
/* GPP_I */
PINCTRL_PIN(269, "DDSP_HPD_0"),
PINCTRL_PIN(270, "DDSP_HPD_1"),
PINCTRL_PIN(271, "DDSP_HPD_2"),
PINCTRL_PIN(272, "DDSP_HPD_3"),
PINCTRL_PIN(273, "EDP_HPD"),
PINCTRL_PIN(274, "DDPB_CTRLCLK"),
PINCTRL_PIN(275, "DDPB_CTRLDATA"),
PINCTRL_PIN(276, "DDPC_CTRLCLK"),
PINCTRL_PIN(277, "DDPC_CTRLDATA"),
PINCTRL_PIN(278, "DDPD_CTRLCLK"),
PINCTRL_PIN(279, "DDPD_CTRLDATA"),
PINCTRL_PIN(280, "M2_SKT2_CFG_0"),
PINCTRL_PIN(281, "M2_SKT2_CFG_1"),
PINCTRL_PIN(282, "M2_SKT2_CFG_2"),
PINCTRL_PIN(283, "M2_SKT2_CFG_3"),
PINCTRL_PIN(284, "SYS_PWROK"),
PINCTRL_PIN(285, "SYS_RESETB"),
PINCTRL_PIN(286, "MLK_RSTB"),
/* GPP_J */
PINCTRL_PIN(287, "CNV_PA_BLANKING"),
PINCTRL_PIN(288, "CNV_GNSS_FTA"),
PINCTRL_PIN(289, "CNV_GNSS_SYSCK"),
PINCTRL_PIN(290, "CNV_RF_RESET_B"),
PINCTRL_PIN(291, "CNV_BRI_DT"),
PINCTRL_PIN(292, "CNV_BRI_RSP"),
PINCTRL_PIN(293, "CNV_RGI_DT"),
PINCTRL_PIN(294, "CNV_RGI_RSP"),
PINCTRL_PIN(295, "CNV_MFUART2_RXD"),
PINCTRL_PIN(296, "CNV_MFUART2_TXD"),
PINCTRL_PIN(297, "CNV_MODEM_CLKREQ"),
PINCTRL_PIN(298, "A4WP_PRESENT"),
};
static const struct intel_padgroup cnlh_community0_gpps[] = {
CNL_GPP(0, 0, 24), /* GPP_A */
CNL_GPP(1, 25, 50), /* GPP_B */
};
static const struct intel_padgroup cnlh_community1_gpps[] = {
CNL_GPP(0, 51, 74), /* GPP_C */
CNL_GPP(1, 75, 98), /* GPP_D */
CNL_GPP(2, 99, 106), /* GPP_G */
CNL_GPP(3, 107, 114), /* AZA */
CNL_GPP(4, 115, 146), /* vGPIO_0 */
CNL_GPP(5, 147, 154), /* vGPIO_1 */
};
static const struct intel_padgroup cnlh_community3_gpps[] = {
CNL_GPP(0, 155, 178), /* GPP_K */
CNL_GPP(1, 179, 202), /* GPP_H */
CNL_GPP(2, 203, 215), /* GPP_E */
CNL_GPP(3, 216, 239), /* GPP_F */
CNL_GPP(4, 240, 248), /* SPI */
};
static const struct intel_padgroup cnlh_community4_gpps[] = {
CNL_GPP(0, 249, 259), /* CPU */
CNL_GPP(1, 260, 268), /* JTAG */
CNL_GPP(2, 269, 286), /* GPP_I */
CNL_GPP(3, 287, 298), /* GPP_J */
};
static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 };
static const unsigned int cnlh_spi1_pins[] = { 44, 45, 46, 47 };
static const unsigned int cnlh_spi2_pins[] = { 84, 85, 86, 87 };
static const unsigned int cnlh_uart0_pins[] = { 59, 60, 61, 62 };
static const unsigned int cnlh_uart1_pins[] = { 63, 64, 65, 66 };
static const unsigned int cnlh_uart2_pins[] = { 71, 72, 73, 74 };
static const unsigned int cnlh_i2c0_pins[] = { 67, 68 };
static const unsigned int cnlh_i2c1_pins[] = { 69, 70 };
static const unsigned int cnlh_i2c2_pins[] = { 88, 89 };
static const unsigned int cnlh_i2c3_pins[] = { 79, 98 };
static const struct intel_pingroup cnlh_groups[] = {
PIN_GROUP("spi0_grp", cnlh_spi0_pins, 1),
PIN_GROUP("spi1_grp", cnlh_spi1_pins, 1),
PIN_GROUP("spi2_grp", cnlh_spi2_pins, 3),
PIN_GROUP("uart0_grp", cnlh_uart0_pins, 1),
PIN_GROUP("uart1_grp", cnlh_uart1_pins, 1),
PIN_GROUP("uart2_grp", cnlh_uart2_pins, 1),
PIN_GROUP("i2c0_grp", cnlh_i2c0_pins, 1),
PIN_GROUP("i2c1_grp", cnlh_i2c1_pins, 1),
PIN_GROUP("i2c2_grp", cnlh_i2c2_pins, 3),
PIN_GROUP("i2c3_grp", cnlh_i2c3_pins, 2),
};
static const char * const cnlh_spi0_groups[] = { "spi0_grp" };
static const char * const cnlh_spi1_groups[] = { "spi1_grp" };
static const char * const cnlh_spi2_groups[] = { "spi2_grp" };
static const char * const cnlh_uart0_groups[] = { "uart0_grp" };
static const char * const cnlh_uart1_groups[] = { "uart1_grp" };
static const char * const cnlh_uart2_groups[] = { "uart2_grp" };
static const char * const cnlh_i2c0_groups[] = { "i2c0_grp" };
static const char * const cnlh_i2c1_groups[] = { "i2c1_grp" };
static const char * const cnlh_i2c2_groups[] = { "i2c2_grp" };
static const char * const cnlh_i2c3_groups[] = { "i2c3_grp" };
static const struct intel_function cnlh_functions[] = {
FUNCTION("spi0", cnlh_spi0_groups),
FUNCTION("spi1", cnlh_spi1_groups),
FUNCTION("spi2", cnlh_spi2_groups),
FUNCTION("uart0", cnlh_uart0_groups),
FUNCTION("uart1", cnlh_uart1_groups),
FUNCTION("uart2", cnlh_uart2_groups),
FUNCTION("i2c0", cnlh_i2c0_groups),
FUNCTION("i2c1", cnlh_i2c1_groups),
FUNCTION("i2c2", cnlh_i2c2_groups),
FUNCTION("i2c3", cnlh_i2c3_groups),
};
static const struct intel_community cnlh_communities[] = {
CNL_COMMUNITY(0, 0, 50, cnlh_community0_gpps),
CNL_COMMUNITY(1, 51, 154, cnlh_community1_gpps),
/*
* ACPI MMIO resources are returned in reverse order for
* communities 3 and 4.
*/
CNL_COMMUNITY(3, 155, 248, cnlh_community3_gpps),
CNL_COMMUNITY(2, 249, 298, cnlh_community4_gpps),
};
static const struct intel_pinctrl_soc_data cnlh_soc_data = {
.pins = cnlh_pins,
.npins = ARRAY_SIZE(cnlh_pins),
.groups = cnlh_groups,
.ngroups = ARRAY_SIZE(cnlh_groups),
.functions = cnlh_functions,
.nfunctions = ARRAY_SIZE(cnlh_functions),
.communities = cnlh_communities,
.ncommunities = ARRAY_SIZE(cnlh_communities),
};
/* Cannon Lake-LP */
static const struct pinctrl_pin_desc cnllp_pins[] = {
/* GPP_A */
@ -403,6 +824,7 @@ static const struct intel_pinctrl_soc_data cnllp_soc_data = {
};
static const struct acpi_device_id cnl_pinctrl_acpi_match[] = {
{ "INT3450", (kernel_ulong_t)&cnlh_soc_data },
{ "INT34BB", (kernel_ulong_t)&cnllp_soc_data },
{ },
};

302
drivers/pinctrl/intel/pinctrl-denverton.c Normal file
View file

@ -0,0 +1,302 @@
/*
* Intel Denverton SoC pinctrl/GPIO driver
*
* Copyright (C) 2017, Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#define DNV_PAD_OWN 0x020
#define DNV_HOSTSW_OWN 0x0C0
#define DNV_PADCFGLOCK 0x090
#define DNV_GPI_IE 0x120
#define DNV_GPP(n, s, e) \
{ \
.reg_num = (n), \
.base = (s), \
.size = ((e) - (s) + 1), \
}
#define DNV_COMMUNITY(b, s, e, g) \
{ \
.barno = (b), \
.padown_offset = DNV_PAD_OWN, \
.padcfglock_offset = DNV_PADCFGLOCK, \
.hostown_offset = DNV_HOSTSW_OWN, \
.ie_offset = DNV_GPI_IE, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
.gpps = (g), \
.ngpps = ARRAY_SIZE(g), \
}
static const struct pinctrl_pin_desc dnv_pins[] = {
/* North ALL */
PINCTRL_PIN(0, "GBE0_SDP0"),
PINCTRL_PIN(1, "GBE1_SDP0"),
PINCTRL_PIN(2, "GBE0_SDP1"),
PINCTRL_PIN(3, "GBE1_SDP1"),
PINCTRL_PIN(4, "GBE0_SDP2"),
PINCTRL_PIN(5, "GBE1_SDP2"),
PINCTRL_PIN(6, "GBE0_SDP3"),
PINCTRL_PIN(7, "GBE1_SDP3"),
PINCTRL_PIN(8, "GBE2_LED0"),
PINCTRL_PIN(9, "GBE2_LED1"),
PINCTRL_PIN(10, "GBE0_I2C_CLK"),
PINCTRL_PIN(11, "GBE0_I2C_DATA"),
PINCTRL_PIN(12, "GBE1_I2C_CLK"),
PINCTRL_PIN(13, "GBE1_I2C_DATA"),
PINCTRL_PIN(14, "NCSI_RXD0"),
PINCTRL_PIN(15, "NCSI_CLK_IN"),
PINCTRL_PIN(16, "NCSI_RXD1"),
PINCTRL_PIN(17, "NCSI_CRS_DV"),
PINCTRL_PIN(18, "NCSI_ARB_IN"),
PINCTRL_PIN(19, "NCSI_TX_EN"),
PINCTRL_PIN(20, "NCSI_TXD0"),
PINCTRL_PIN(21, "NCSI_TXD1"),
PINCTRL_PIN(22, "NCSI_ARB_OUT"),
PINCTRL_PIN(23, "GBE0_LED0"),
PINCTRL_PIN(24, "GBE0_LED1"),
PINCTRL_PIN(25, "GBE1_LED0"),
PINCTRL_PIN(26, "GBE1_LED1"),
PINCTRL_PIN(27, "GPIO_0"),
PINCTRL_PIN(28, "PCIE_CLKREQ0_N"),
PINCTRL_PIN(29, "PCIE_CLKREQ1_N"),
PINCTRL_PIN(30, "PCIE_CLKREQ2_N"),
PINCTRL_PIN(31, "PCIE_CLKREQ3_N"),
PINCTRL_PIN(32, "PCIE_CLKREQ4_N"),
PINCTRL_PIN(33, "GPIO_1"),
PINCTRL_PIN(34, "GPIO_2"),
PINCTRL_PIN(35, "SVID_ALERT_N"),
PINCTRL_PIN(36, "SVID_DATA"),
PINCTRL_PIN(37, "SVID_CLK"),
PINCTRL_PIN(38, "THERMTRIP_N"),
PINCTRL_PIN(39, "PROCHOT_N"),
PINCTRL_PIN(40, "MEMHOT_N"),
/* South DFX */
PINCTRL_PIN(41, "DFX_PORT_CLK0"),
PINCTRL_PIN(42, "DFX_PORT_CLK1"),
PINCTRL_PIN(43, "DFX_PORT0"),
PINCTRL_PIN(44, "DFX_PORT1"),
PINCTRL_PIN(45, "DFX_PORT2"),
PINCTRL_PIN(46, "DFX_PORT3"),
PINCTRL_PIN(47, "DFX_PORT4"),
PINCTRL_PIN(48, "DFX_PORT5"),
PINCTRL_PIN(49, "DFX_PORT6"),
PINCTRL_PIN(50, "DFX_PORT7"),
PINCTRL_PIN(51, "DFX_PORT8"),
PINCTRL_PIN(52, "DFX_PORT9"),
PINCTRL_PIN(53, "DFX_PORT10"),
PINCTRL_PIN(54, "DFX_PORT11"),
PINCTRL_PIN(55, "DFX_PORT12"),
PINCTRL_PIN(56, "DFX_PORT13"),
PINCTRL_PIN(57, "DFX_PORT14"),
PINCTRL_PIN(58, "DFX_PORT15"),
/* South GPP0 */
PINCTRL_PIN(59, "GPIO_12"),
PINCTRL_PIN(60, "SMB5_GBE_ALRT_N"),
PINCTRL_PIN(61, "PCIE_CLKREQ5_N"),
PINCTRL_PIN(62, "PCIE_CLKREQ6_N"),
PINCTRL_PIN(63, "PCIE_CLKREQ7_N"),
PINCTRL_PIN(64, "UART0_RXD"),
PINCTRL_PIN(65, "UART0_TXD"),
PINCTRL_PIN(66, "SMB5_GBE_CLK"),
PINCTRL_PIN(67, "SMB5_GBE_DATA"),
PINCTRL_PIN(68, "ERROR2_N"),
PINCTRL_PIN(69, "ERROR1_N"),
PINCTRL_PIN(70, "ERROR0_N"),
PINCTRL_PIN(71, "IERR_N"),
PINCTRL_PIN(72, "MCERR_N"),
PINCTRL_PIN(73, "SMB0_LEG_CLK"),
PINCTRL_PIN(74, "SMB0_LEG_DATA"),
PINCTRL_PIN(75, "SMB0_LEG_ALRT_N"),
PINCTRL_PIN(76, "SMB1_HOST_DATA"),
PINCTRL_PIN(77, "SMB1_HOST_CLK"),
PINCTRL_PIN(78, "SMB2_PECI_DATA"),
PINCTRL_PIN(79, "SMB2_PECI_CLK"),
PINCTRL_PIN(80, "SMB4_CSME0_DATA"),
PINCTRL_PIN(81, "SMB4_CSME0_CLK"),
PINCTRL_PIN(82, "SMB4_CSME0_ALRT_N"),
PINCTRL_PIN(83, "USB_OC0_N"),
PINCTRL_PIN(84, "FLEX_CLK_SE0"),
PINCTRL_PIN(85, "FLEX_CLK_SE1"),
PINCTRL_PIN(86, "GPIO_4"),
PINCTRL_PIN(87, "GPIO_5"),
PINCTRL_PIN(88, "GPIO_6"),
PINCTRL_PIN(89, "GPIO_7"),
PINCTRL_PIN(90, "SATA0_LED_N"),
PINCTRL_PIN(91, "SATA1_LED_N"),
PINCTRL_PIN(92, "SATA_PDETECT0"),
PINCTRL_PIN(93, "SATA_PDETECT1"),
PINCTRL_PIN(94, "SATA0_SDOUT"),
PINCTRL_PIN(95, "SATA1_SDOUT"),
PINCTRL_PIN(96, "UART1_RXD"),
PINCTRL_PIN(97, "UART1_TXD"),
PINCTRL_PIN(98, "GPIO_8"),
PINCTRL_PIN(99, "GPIO_9"),
PINCTRL_PIN(100, "TCK"),
PINCTRL_PIN(101, "TRST_N"),
PINCTRL_PIN(102, "TMS"),
PINCTRL_PIN(103, "TDI"),
PINCTRL_PIN(104, "TDO"),
PINCTRL_PIN(105, "CX_PRDY_N"),
PINCTRL_PIN(106, "CX_PREQ_N"),
PINCTRL_PIN(107, "CTBTRIGINOUT"),
PINCTRL_PIN(108, "CTBTRIGOUT"),
PINCTRL_PIN(109, "DFX_SPARE2"),
PINCTRL_PIN(110, "DFX_SPARE3"),
PINCTRL_PIN(111, "DFX_SPARE4"),
/* South GPP1 */
PINCTRL_PIN(112, "SUSPWRDNACK"),
PINCTRL_PIN(113, "PMU_SUSCLK"),
PINCTRL_PIN(114, "ADR_TRIGGER"),
PINCTRL_PIN(115, "PMU_SLP_S45_N"),
PINCTRL_PIN(116, "PMU_SLP_S3_N"),
PINCTRL_PIN(117, "PMU_WAKE_N"),
PINCTRL_PIN(118, "PMU_PWRBTN_N"),
PINCTRL_PIN(119, "PMU_RESETBUTTON_N"),
PINCTRL_PIN(120, "PMU_PLTRST_N"),
PINCTRL_PIN(121, "SUS_STAT_N"),
PINCTRL_PIN(122, "SLP_S0IX_N"),
PINCTRL_PIN(123, "SPI_CS0_N"),
PINCTRL_PIN(124, "SPI_CS1_N"),
PINCTRL_PIN(125, "SPI_MOSI_IO0"),
PINCTRL_PIN(126, "SPI_MISO_IO1"),
PINCTRL_PIN(127, "SPI_IO2"),
PINCTRL_PIN(128, "SPI_IO3"),
PINCTRL_PIN(129, "SPI_CLK"),
PINCTRL_PIN(130, "SPI_CLK_LOOPBK"),
PINCTRL_PIN(131, "ESPI_IO0"),
PINCTRL_PIN(132, "ESPI_IO1"),
PINCTRL_PIN(133, "ESPI_IO2"),
PINCTRL_PIN(134, "ESPI_IO3"),
PINCTRL_PIN(135, "ESPI_CS0_N"),
PINCTRL_PIN(136, "ESPI_CLK"),
PINCTRL_PIN(137, "ESPI_RST_N"),
PINCTRL_PIN(138, "ESPI_ALRT0_N"),
PINCTRL_PIN(139, "GPIO_10"),
PINCTRL_PIN(140, "GPIO_11"),
PINCTRL_PIN(141, "ESPI_CLK_LOOPBK"),
PINCTRL_PIN(142, "EMMC_CMD"),
PINCTRL_PIN(143, "EMMC_STROBE"),
PINCTRL_PIN(144, "EMMC_CLK"),
PINCTRL_PIN(145, "EMMC_D0"),
PINCTRL_PIN(146, "EMMC_D1"),
PINCTRL_PIN(147, "EMMC_D2"),
PINCTRL_PIN(148, "EMMC_D3"),
PINCTRL_PIN(149, "EMMC_D4"),
PINCTRL_PIN(150, "EMMC_D5"),
PINCTRL_PIN(151, "EMMC_D6"),
PINCTRL_PIN(152, "EMMC_D7"),
PINCTRL_PIN(153, "GPIO_3"),
};
static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 };
static const unsigned int dnv_uart0_modes[] = { 2, 3, 1, 1 };
static const unsigned int dnv_uart1_pins[] = { 94, 95, 96, 97 };
static const unsigned int dnv_uart2_pins[] = { 60, 61, 62, 63 };
static const unsigned int dnv_uart2_modes[] = { 1, 1, 2, 2 };
static const unsigned int dnv_emmc_pins[] = {
142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152,
};
static const struct intel_pingroup dnv_groups[] = {
PIN_GROUP("uart0_grp", dnv_uart0_pins, dnv_uart0_modes),
PIN_GROUP("uart1_grp", dnv_uart1_pins, 1),
PIN_GROUP("uart2_grp", dnv_uart2_pins, dnv_uart2_modes),
PIN_GROUP("emmc_grp", dnv_emmc_pins, 1),
};
static const char * const dnv_uart0_groups[] = { "uart0_grp" };
static const char * const dnv_uart1_groups[] = { "uart1_grp" };
static const char * const dnv_uart2_groups[] = { "uart2_grp" };
static const char * const dnv_emmc_groups[] = { "emmc_grp" };
static const struct intel_function dnv_functions[] = {
FUNCTION("uart0", dnv_uart0_groups),
FUNCTION("uart1", dnv_uart1_groups),
FUNCTION("uart2", dnv_uart2_groups),
FUNCTION("emmc", dnv_emmc_groups),
};
static const struct intel_padgroup dnv_north_gpps[] = {
DNV_GPP(0, 0, 31), /* North ALL_0 */
DNV_GPP(1, 32, 40), /* North ALL_1 */
};
static const struct intel_padgroup dnv_south_gpps[] = {
DNV_GPP(0, 41, 58), /* South DFX */
DNV_GPP(1, 59, 90), /* South GPP0_0 */
DNV_GPP(2, 91, 111), /* South GPP0_1 */
DNV_GPP(3, 112, 143), /* South GPP1_0 */
DNV_GPP(4, 144, 153), /* South GPP1_1 */
};
static const struct intel_community dnv_communities[] = {
DNV_COMMUNITY(0, 0, 40, dnv_north_gpps),
DNV_COMMUNITY(1, 41, 153, dnv_south_gpps),
};
static const struct intel_pinctrl_soc_data dnv_soc_data = {
.pins = dnv_pins,
.npins = ARRAY_SIZE(dnv_pins),
.groups = dnv_groups,
.ngroups = ARRAY_SIZE(dnv_groups),
.functions = dnv_functions,
.nfunctions = ARRAY_SIZE(dnv_functions),
.communities = dnv_communities,
.ncommunities = ARRAY_SIZE(dnv_communities),
};
static int dnv_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe(pdev, &dnv_soc_data);
}
static const struct dev_pm_ops dnv_pinctrl_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
intel_pinctrl_resume)
};
static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {
{ "INTC3000" },
{ }
};
MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match);
static struct platform_driver dnv_pinctrl_driver = {
.probe = dnv_pinctrl_probe,
.driver = {
.name = "denverton-pinctrl",
.acpi_match_table = dnv_pinctrl_acpi_match,
.pm = &dnv_pinctrl_pm_ops,
},
};
static int __init dnv_pinctrl_init(void)
{
return platform_driver_register(&dnv_pinctrl_driver);
}
subsys_initcall(dnv_pinctrl_init);
static void __exit dnv_pinctrl_exit(void)
{
platform_driver_unregister(&dnv_pinctrl_driver);
}
module_exit(dnv_pinctrl_exit);
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_DESCRIPTION("Intel Denverton SoC pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");

16
drivers/pinctrl/intel/pinctrl-intel.c
View file

@ -751,23 +751,29 @@ static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
void __iomem *reg;
u32 padcfg0;
reg = intel_get_padcfg(pctrl, offset, PADCFG0);
if (!reg)
return -EINVAL;
return !!(readl(reg) & PADCFG0_GPIORXSTATE);
padcfg0 = readl(reg);
if (!(padcfg0 & PADCFG0_GPIOTXDIS))
return !!(padcfg0 & PADCFG0_GPIOTXSTATE);
return !!(padcfg0 & PADCFG0_GPIORXSTATE);
}
static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
unsigned long flags;
void __iomem *reg;
u32 padcfg0;
reg = intel_get_padcfg(pctrl, offset, PADCFG0);
if (reg) {
unsigned long flags;
u32 padcfg0;
if (!reg)
return;
raw_spin_lock_irqsave(&pctrl->lock, flags);
padcfg0 = readl(reg);
@ -777,7 +783,6 @@ static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
padcfg0 &= ~PADCFG0_GPIOTXSTATE;
writel(padcfg0, reg);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
}
}
static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
@ -1035,6 +1040,7 @@ static struct irq_chip intel_gpio_irqchip = {
.irq_unmask = intel_gpio_irq_unmask,
.irq_set_type = intel_gpio_irq_type,
.irq_set_wake = intel_gpio_irq_wake,
.flags = IRQCHIP_MASK_ON_SUSPEND,
};
static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)

343
drivers/pinctrl/intel/pinctrl-lewisburg.c Normal file
View file

@ -0,0 +1,343 @@
/*
* Intel Lewisburg pinctrl/GPIO driver
*
* Copyright (C) 2017, Intel Corporation
* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/acpi.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-intel.h"
#define LBG_PAD_OWN 0x020
#define LBG_PADCFGLOCK 0x060
#define LBG_HOSTSW_OWN 0x080
#define LBG_GPI_IE 0x110
#define LBG_COMMUNITY(b, s, e) \
{ \
.barno = (b), \
.padown_offset = LBG_PAD_OWN, \
.padcfglock_offset = LBG_PADCFGLOCK, \
.hostown_offset = LBG_HOSTSW_OWN, \
.ie_offset = LBG_GPI_IE, \
.gpp_size = 24, \
.pin_base = (s), \
.npins = ((e) - (s) + 1), \
}
static const struct pinctrl_pin_desc lbg_pins[] = {
/* GPP_A */
PINCTRL_PIN(0, "RCINB"),
PINCTRL_PIN(1, "LAD_0"),
PINCTRL_PIN(2, "LAD_1"),
PINCTRL_PIN(3, "LAD_2"),
PINCTRL_PIN(4, "LAD_3"),
PINCTRL_PIN(5, "LFRAMEB"),
PINCTRL_PIN(6, "SERIRQ"),
PINCTRL_PIN(7, "PIRQAB"),
PINCTRL_PIN(8, "CLKRUNB"),
PINCTRL_PIN(9, "CLKOUT_LPC_0"),
PINCTRL_PIN(10, "CLKOUT_LPC_1"),
PINCTRL_PIN(11, "PMEB"),
PINCTRL_PIN(12, "BM_BUSYB"),
PINCTRL_PIN(13, "SUSWARNB_SUSPWRDNACK"),
PINCTRL_PIN(14, "ESPI_RESETB"),
PINCTRL_PIN(15, "SUSACKB"),
PINCTRL_PIN(16, "CLKOUT_LPC_2"),
PINCTRL_PIN(17, "GPP_A_17"),
PINCTRL_PIN(18, "GPP_A_18"),
PINCTRL_PIN(19, "GPP_A_19"),
PINCTRL_PIN(20, "GPP_A_20"),
PINCTRL_PIN(21, "GPP_A_21"),
PINCTRL_PIN(22, "GPP_A_22"),
PINCTRL_PIN(23, "GPP_A_23"),
/* GPP_B */
PINCTRL_PIN(24, "CORE_VID_0"),
PINCTRL_PIN(25, "CORE_VID_1"),
PINCTRL_PIN(26, "VRALERTB"),
PINCTRL_PIN(27, "CPU_GP_2"),
PINCTRL_PIN(28, "CPU_GP_3"),
PINCTRL_PIN(29, "SRCCLKREQB_0"),
PINCTRL_PIN(30, "SRCCLKREQB_1"),
PINCTRL_PIN(31, "SRCCLKREQB_2"),
PINCTRL_PIN(32, "SRCCLKREQB_3"),
PINCTRL_PIN(33, "SRCCLKREQB_4"),
PINCTRL_PIN(34, "SRCCLKREQB_5"),
PINCTRL_PIN(35, "GPP_B_11"),
PINCTRL_PIN(36, "GLB_RST_WARN_N"),
PINCTRL_PIN(37, "PLTRSTB"),
PINCTRL_PIN(38, "SPKR"),
PINCTRL_PIN(39, "GPP_B_15"),
PINCTRL_PIN(40, "GPP_B_16"),
PINCTRL_PIN(41, "GPP_B_17"),
PINCTRL_PIN(42, "GPP_B_18"),
PINCTRL_PIN(43, "GPP_B_19"),
PINCTRL_PIN(44, "GPP_B_20"),
PINCTRL_PIN(45, "GPP_B_21"),
PINCTRL_PIN(46, "GPP_B_22"),
PINCTRL_PIN(47, "SML1ALERTB"),
/* GPP_F */
PINCTRL_PIN(48, "SATAXPCIE_3"),
PINCTRL_PIN(49, "SATAXPCIE_4"),
PINCTRL_PIN(50, "SATAXPCIE_5"),
PINCTRL_PIN(51, "SATAXPCIE_6"),
PINCTRL_PIN(52, "SATAXPCIE_7"),
PINCTRL_PIN(53, "SATA_DEVSLP_3"),
PINCTRL_PIN(54, "SATA_DEVSLP_4"),
PINCTRL_PIN(55, "SATA_DEVSLP_5"),
PINCTRL_PIN(56, "SATA_DEVSLP_6"),
PINCTRL_PIN(57, "SATA_DEVSLP_7"),
PINCTRL_PIN(58, "SATA_SCLOCK"),
PINCTRL_PIN(59, "SATA_SLOAD"),
PINCTRL_PIN(60, "SATA_SDATAOUT1"),
PINCTRL_PIN(61, "SATA_SDATAOUT0"),
PINCTRL_PIN(62, "SSATA_LEDB"),
PINCTRL_PIN(63, "USB2_OCB_4"),
PINCTRL_PIN(64, "USB2_OCB_5"),
PINCTRL_PIN(65, "USB2_OCB_6"),
PINCTRL_PIN(66, "USB2_OCB_7"),
PINCTRL_PIN(67, "GBE_SMBUS_CLK"),
PINCTRL_PIN(68, "GBE_SMBDATA"),
PINCTRL_PIN(69, "GBE_SMBALRTN"),
PINCTRL_PIN(70, "SSATA_SCLOCK"),
PINCTRL_PIN(71, "SSATA_SLOAD"),
/* GPP_C */
PINCTRL_PIN(72, "SMBCLK"),
PINCTRL_PIN(73, "SMBDATA"),
PINCTRL_PIN(74, "SMBALERTB"),
PINCTRL_PIN(75, "SML0CLK"),
PINCTRL_PIN(76, "SML0DATA"),
PINCTRL_PIN(77, "SML0ALERTB"),
PINCTRL_PIN(78, "SML1CLK"),
PINCTRL_PIN(79, "SML1DATA"),
PINCTRL_PIN(80, "GPP_C_8"),
PINCTRL_PIN(81, "GPP_C_9"),
PINCTRL_PIN(82, "GPP_C_10"),
PINCTRL_PIN(83, "GPP_C_11"),
PINCTRL_PIN(84, "GPP_C_12"),
PINCTRL_PIN(85, "GPP_C_13"),
PINCTRL_PIN(86, "GPP_C_14"),
PINCTRL_PIN(87, "GPP_C_15"),
PINCTRL_PIN(88, "GPP_C_16"),
PINCTRL_PIN(89, "GPP_C_17"),
PINCTRL_PIN(90, "GPP_C_18"),
PINCTRL_PIN(91, "GPP_C_19"),
PINCTRL_PIN(92, "GPP_C_20"),
PINCTRL_PIN(93, "GPP_C_21"),
PINCTRL_PIN(94, "GPP_C_22"),
PINCTRL_PIN(95, "GPP_C_23"),
/* GPP_D */
PINCTRL_PIN(96, "GPP_D_0"),
PINCTRL_PIN(97, "GPP_D_1"),
PINCTRL_PIN(98, "GPP_D_2"),
PINCTRL_PIN(99, "GPP_D_3"),
PINCTRL_PIN(100, "GPP_D_4"),
PINCTRL_PIN(101, "SSP0_SFRM"),
PINCTRL_PIN(102, "SSP0_TXD"),
PINCTRL_PIN(103, "SSP0_RXD"),
PINCTRL_PIN(104, "SSP0_SCLK"),
PINCTRL_PIN(105, "SSATA_DEVSLP_3"),
PINCTRL_PIN(106, "SSATA_DEVSLP_4"),
PINCTRL_PIN(107, "SSATA_DEVSLP_5"),
PINCTRL_PIN(108, "SSATA_SDATAOUT1"),
PINCTRL_PIN(109, "SML0BCLK_SML0BCLKIE"),
PINCTRL_PIN(110, "SML0BDATA_SML0BDATAIE"),
PINCTRL_PIN(111, "SSATA_SDATAOUT0"),
PINCTRL_PIN(112, "SML0BALERTB_SML0BALERTBIE"),
PINCTRL_PIN(113, "DMIC_CLK_1"),
PINCTRL_PIN(114, "DMIC_DATA_1"),
PINCTRL_PIN(115, "DMIC_CLK_0"),
PINCTRL_PIN(116, "DMIC_DATA_0"),
PINCTRL_PIN(117, "IE_UART_RXD"),
PINCTRL_PIN(118, "IE_UART_TXD"),
PINCTRL_PIN(119, "GPP_D_23"),
/* GPP_E */
PINCTRL_PIN(120, "SATAXPCIE_0"),
PINCTRL_PIN(121, "SATAXPCIE_1"),
PINCTRL_PIN(122, "SATAXPCIE_2"),
PINCTRL_PIN(123, "CPU_GP_0"),
PINCTRL_PIN(124, "SATA_DEVSLP_0"),
PINCTRL_PIN(125, "SATA_DEVSLP_1"),
PINCTRL_PIN(126, "SATA_DEVSLP_2"),
PINCTRL_PIN(127, "CPU_GP_1"),
PINCTRL_PIN(128, "SATA_LEDB"),
PINCTRL_PIN(129, "USB2_OCB_0"),
PINCTRL_PIN(130, "USB2_OCB_1"),
PINCTRL_PIN(131, "USB2_OCB_2"),
PINCTRL_PIN(132, "USB2_OCB_3"),
/* GPP_I */
PINCTRL_PIN(133, "GBE_TDO"),
PINCTRL_PIN(134, "GBE_TCK"),
PINCTRL_PIN(135, "GBE_TMS"),
PINCTRL_PIN(136, "GBE_TDI"),
PINCTRL_PIN(137, "DO_RESET_INB"),
PINCTRL_PIN(138, "DO_RESET_OUTB"),
PINCTRL_PIN(139, "RESET_DONE"),
PINCTRL_PIN(140, "GBE_TRST_N"),
PINCTRL_PIN(141, "GBE_PCI_DIS"),
PINCTRL_PIN(142, "GBE_LAN_DIS"),
PINCTRL_PIN(143, "GPP_I_10"),
PINCTRL_PIN(144, "GPIO_RCOMP_3P3"),
/* GPP_J */
PINCTRL_PIN(145, "GBE_LED_0_0"),
PINCTRL_PIN(146, "GBE_LED_0_1"),
PINCTRL_PIN(147, "GBE_LED_1_0"),
PINCTRL_PIN(148, "GBE_LED_1_1"),
PINCTRL_PIN(149, "GBE_LED_2_0"),
PINCTRL_PIN(150, "GBE_LED_2_1"),
PINCTRL_PIN(151, "GBE_LED_3_0"),
PINCTRL_PIN(152, "GBE_LED_3_1"),
PINCTRL_PIN(153, "GBE_SCL_0"),
PINCTRL_PIN(154, "GBE_SDA_0"),
PINCTRL_PIN(155, "GBE_SCL_1"),
PINCTRL_PIN(156, "GBE_SDA_1"),
PINCTRL_PIN(157, "GBE_SCL_2"),
PINCTRL_PIN(158, "GBE_SDA_2"),
PINCTRL_PIN(159, "GBE_SCL_3"),
PINCTRL_PIN(160, "GBE_SDA_3"),
PINCTRL_PIN(161, "GBE_SDP_0_0"),
PINCTRL_PIN(162, "GBE_SDP_0_1"),
PINCTRL_PIN(163, "GBE_SDP_1_0"),
PINCTRL_PIN(164, "GBE_SDP_1_1"),
PINCTRL_PIN(165, "GBE_SDP_2_0"),
PINCTRL_PIN(166, "GBE_SDP_2_1"),
PINCTRL_PIN(167, "GBE_SDP_3_0"),
PINCTRL_PIN(168, "GBE_SDP_3_1"),
/* GPP_K */
PINCTRL_PIN(169, "GBE_RMIICLK"),
PINCTRL_PIN(170, "GBE_RMII_TXD_0"),
PINCTRL_PIN(171, "GBE_RMII_TXD_1"),
PINCTRL_PIN(172, "GBE_RMII_TX_EN"),
PINCTRL_PIN(173, "GBE_RMII_CRS_DV"),
PINCTRL_PIN(174, "GBE_RMII_RXD_0"),
PINCTRL_PIN(175, "GBE_RMII_RXD_1"),
PINCTRL_PIN(176, "GBE_RMII_RX_ER"),
PINCTRL_PIN(177, "GBE_RMII_ARBIN"),
PINCTRL_PIN(178, "GBE_RMII_ARB_OUT"),
PINCTRL_PIN(179, "PE_RST_N"),
PINCTRL_PIN(180, "GPIO_RCOMP_1P8_3P3"),
/* GPP_G */
PINCTRL_PIN(181, "FAN_TACH_0"),
PINCTRL_PIN(182, "FAN_TACH_1"),
PINCTRL_PIN(183, "FAN_TACH_2"),
PINCTRL_PIN(184, "FAN_TACH_3"),
PINCTRL_PIN(185, "FAN_TACH_4"),
PINCTRL_PIN(186, "FAN_TACH_5"),
PINCTRL_PIN(187, "FAN_TACH_6"),
PINCTRL_PIN(188, "FAN_TACH_7"),
PINCTRL_PIN(189, "FAN_PWM_0"),
PINCTRL_PIN(190, "FAN_PWM_1"),
PINCTRL_PIN(191, "FAN_PWM_2"),
PINCTRL_PIN(192, "FAN_PWM_3"),
PINCTRL_PIN(193, "GSXDOUT"),
PINCTRL_PIN(194, "GSXSLOAD"),
PINCTRL_PIN(195, "GSXDIN"),
PINCTRL_PIN(196, "GSXSRESETB"),
PINCTRL_PIN(197, "GSXCLK"),
PINCTRL_PIN(198, "ADR_COMPLETE"),
PINCTRL_PIN(199, "NMIB"),
PINCTRL_PIN(200, "SMIB"),
PINCTRL_PIN(201, "SSATA_DEVSLP_0"),
PINCTRL_PIN(202, "SSATA_DEVSLP_1"),
PINCTRL_PIN(203, "SSATA_DEVSLP_2"),
PINCTRL_PIN(204, "SSATAXPCIE0_SSATAGP0"),
/* GPP_H */
PINCTRL_PIN(205, "SRCCLKREQB_6"),
PINCTRL_PIN(206, "SRCCLKREQB_7"),
PINCTRL_PIN(207, "SRCCLKREQB_8"),
PINCTRL_PIN(208, "SRCCLKREQB_9"),
PINCTRL_PIN(209, "SRCCLKREQB_10"),
PINCTRL_PIN(210, "SRCCLKREQB_11"),
PINCTRL_PIN(211, "SRCCLKREQB_12"),
PINCTRL_PIN(212, "SRCCLKREQB_13"),
PINCTRL_PIN(213, "SRCCLKREQB_14"),
PINCTRL_PIN(214, "SRCCLKREQB_15"),
PINCTRL_PIN(215, "SML2CLK"),
PINCTRL_PIN(216, "SML2DATA"),
PINCTRL_PIN(217, "SML2ALERTB"),
PINCTRL_PIN(218, "SML3CLK"),
PINCTRL_PIN(219, "SML3DATA"),
PINCTRL_PIN(220, "SML3ALERTB"),
PINCTRL_PIN(221, "SML4CLK"),
PINCTRL_PIN(222, "SML4DATA"),
PINCTRL_PIN(223, "SML4ALERTB"),
PINCTRL_PIN(224, "SSATAXPCIE1_SSATAGP1"),
PINCTRL_PIN(225, "SSATAXPCIE2_SSATAGP2"),
PINCTRL_PIN(226, "SSATAXPCIE3_SSATAGP3"),
PINCTRL_PIN(227, "SSATAXPCIE4_SSATAGP4"),
PINCTRL_PIN(228, "SSATAXPCIE5_SSATAGP5"),
/* GPP_L */
PINCTRL_PIN(229, "VISA2CH0_D0"),
PINCTRL_PIN(230, "VISA2CH0_D1"),
PINCTRL_PIN(231, "VISA2CH0_D2"),
PINCTRL_PIN(232, "VISA2CH0_D3"),
PINCTRL_PIN(233, "VISA2CH0_D4"),
PINCTRL_PIN(234, "VISA2CH0_D5"),
PINCTRL_PIN(235, "VISA2CH0_D6"),
PINCTRL_PIN(236, "VISA2CH0_D7"),
PINCTRL_PIN(237, "VISA2CH0_CLK"),
PINCTRL_PIN(238, "VISA2CH1_D0"),
PINCTRL_PIN(239, "VISA2CH1_D1"),
PINCTRL_PIN(240, "VISA2CH1_D2"),
PINCTRL_PIN(241, "VISA2CH1_D3"),
PINCTRL_PIN(242, "VISA2CH1_D4"),
PINCTRL_PIN(243, "VISA2CH1_D5"),
PINCTRL_PIN(244, "VISA2CH1_D6"),
PINCTRL_PIN(245, "VISA2CH1_D7"),
PINCTRL_PIN(246, "VISA2CH1_CLK"),
};
static const struct intel_community lbg_communities[] = {
LBG_COMMUNITY(0, 0, 71),
LBG_COMMUNITY(1, 72, 132),
LBG_COMMUNITY(3, 133, 144),
LBG_COMMUNITY(4, 145, 180),
LBG_COMMUNITY(5, 181, 246),
};
static const struct intel_pinctrl_soc_data lbg_soc_data = {
.pins = lbg_pins,
.npins = ARRAY_SIZE(lbg_pins),
.communities = lbg_communities,
.ncommunities = ARRAY_SIZE(lbg_communities),
};
static int lbg_pinctrl_probe(struct platform_device *pdev)
{
return intel_pinctrl_probe(pdev, &lbg_soc_data);
}
static const struct dev_pm_ops lbg_pinctrl_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
intel_pinctrl_resume)
};
static const struct acpi_device_id lbg_pinctrl_acpi_match[] = {
{ "INT3536" },
{ }
};
MODULE_DEVICE_TABLE(acpi, lbg_pinctrl_acpi_match);
static struct platform_driver lbg_pinctrl_driver = {
.probe = lbg_pinctrl_probe,
.driver = {
.name = "lewisburg-pinctrl",
.acpi_match_table = lbg_pinctrl_acpi_match,
.pm = &lbg_pinctrl_pm_ops,
},
};
module_platform_driver(lbg_pinctrl_driver);
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
MODULE_DESCRIPTION("Intel Lewisburg pinctrl/GPIO driver");
MODULE_LICENSE("GPL v2");

12
drivers/pinctrl/mediatek/pinctrl-mtk-mt2701.h
View file

@ -223,6 +223,8 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_EINT_FUNCTION(0, 0),
MTK_FUNCTION(0, "GPIO22"),
MTK_FUNCTION(1, "UCTS0"),
/* MT7623 take function 2 as PCIE0_PERST_N */
MTK_FUNCTION(2, "PCIE0_PERST_N"),
MTK_FUNCTION(3, "KCOL3"),
MTK_FUNCTION(4, "CONN_DSP_JDO"),
MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
@ -235,6 +237,8 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_EINT_FUNCTION(0, 1),
MTK_FUNCTION(0, "GPIO23"),
MTK_FUNCTION(1, "URTS0"),
/* MT7623 take function 2 as PCIE1_PERST_N */
MTK_FUNCTION(2, "PCIE1_PERST_N"),
MTK_FUNCTION(3, "KCOL2"),
MTK_FUNCTION(4, "CONN_MCU_TDO"),
MTK_FUNCTION(5, "EXT_FRAME_SYNC"),
@ -247,6 +251,8 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_EINT_FUNCTION(0, 2),
MTK_FUNCTION(0, "GPIO24"),
MTK_FUNCTION(1, "UCTS1"),
/* MT7623 take function 2 as PCIE2_PERST_N */
MTK_FUNCTION(2, "PCIE2_PERST_N"),
MTK_FUNCTION(3, "KCOL1"),
MTK_FUNCTION(4, "CONN_MCU_DBGACK_N"),
MTK_FUNCTION(7, "DBG_MON_A[28]"),
@ -308,6 +314,8 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(3, "KROW0"),
MTK_FUNCTION(4, "CONN_MCU_TMS"),
MTK_FUNCTION(5, "CONN_MCU_AICE_JMSC"),
/* MT7623 take function 6 as PCIE2_PERST_N */
MTK_FUNCTION(6, "PCIE2_PERST_N"),
MTK_FUNCTION(7, "DBG_MON_A[23]"),
MTK_FUNCTION(14, "PCIE2_PERST_N")
),
@ -1787,6 +1795,8 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(0, "GPIO208"),
MTK_FUNCTION(1, "AUD_EXT_CK1"),
MTK_FUNCTION(2, "PWM0"),
/* MT7623 take function 3 as PCIE0_PERST_N */
MTK_FUNCTION(3, "PCIE0_PERST_N"),
MTK_FUNCTION(4, "ANT_SEL5"),
MTK_FUNCTION(5, "DISP_PWM"),
MTK_FUNCTION(7, "DBG_MON_A[31]"),
@ -1799,6 +1809,8 @@ static const struct mtk_desc_pin mtk_pins_mt2701[] = {
MTK_FUNCTION(0, "GPIO209"),
MTK_FUNCTION(1, "AUD_EXT_CK2"),
MTK_FUNCTION(2, "MSDC1_WP"),
/* MT7623 take function 3 as PCIE1_PERST_N */
MTK_FUNCTION(3, "PCIE1_PERST_N"),
MTK_FUNCTION(5, "PWM1"),
MTK_FUNCTION(7, "DBG_MON_A[32]"),
MTK_FUNCTION(11, "PCIE1_PERST_N")

6
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
View file

@ -190,14 +190,14 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
"mii", "mii_err"),
};
const struct armada_37xx_pin_data armada_37xx_pin_nb = {
static const struct armada_37xx_pin_data armada_37xx_pin_nb = {
.nr_pins = 36,
.name = "GPIO1",
.groups = armada_37xx_nb_groups,
.ngroups = ARRAY_SIZE(armada_37xx_nb_groups),
};
const struct armada_37xx_pin_data armada_37xx_pin_sb = {
static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
.nr_pins = 30,
.name = "GPIO2",
.groups = armada_37xx_sb_groups,
@ -254,7 +254,7 @@ static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev,
return -ENOTSUPP;
}
static struct pinconf_ops armada_37xx_pinconf_ops = {
static const struct pinconf_ops armada_37xx_pinconf_ops = {
.is_generic = true,
.pin_config_group_get = armada_37xx_pin_config_group_get,
.pin_config_group_set = armada_37xx_pin_config_group_set,

2
drivers/pinctrl/nomadik/pinctrl-abx500.c
View file

@ -647,7 +647,7 @@ static inline void abx500_gpio_dbg_show_one(struct seq_file *s,
#define abx500_gpio_dbg_show NULL
#endif
static struct gpio_chip abx500gpio_chip = {
static const struct gpio_chip abx500gpio_chip = {
.label = "abx500-gpio",
.owner = THIS_MODULE,
.request = gpiochip_generic_request,

2
drivers/pinctrl/nomadik/pinctrl-nomadik.c
View file

@ -1078,7 +1078,7 @@ static struct nmk_gpio_chip *nmk_gpio_populate_chip(struct device_node *np,
res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(base))
return base;
return ERR_CAST(base);
nmk_chip->addr = base;
clk = clk_get(&gpio_pdev->dev, NULL);

9
drivers/pinctrl/pinconf-generic.c
View file

@ -47,6 +47,7 @@ static const struct pin_config_item conf_items[] = {
PCONFDUMP(PIN_CONFIG_OUTPUT_ENABLE, "output enabled", NULL, false),
PCONFDUMP(PIN_CONFIG_OUTPUT, "pin output", "level", true),
PCONFDUMP(PIN_CONFIG_POWER_SOURCE, "pin power source", "selector", true),
PCONFDUMP(PIN_CONFIG_SLEEP_HARDWARE_STATE, "sleep hardware state", NULL, false),
PCONFDUMP(PIN_CONFIG_SLEW_RATE, "slew rate", NULL, true),
};
@ -178,6 +179,7 @@ static const struct pinconf_generic_params dt_params[] = {
{ "output-high", PIN_CONFIG_OUTPUT, 1, },
{ "output-low", PIN_CONFIG_OUTPUT, 0, },
{ "power-source", PIN_CONFIG_POWER_SOURCE, 0 },
{ "sleep-hardware-state", PIN_CONFIG_SLEEP_HARDWARE_STATE, 0 },
{ "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
};
@ -316,16 +318,15 @@ int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev,
if (ret < 0) {
/* EINVAL=missing, which is fine since it's optional */
if (ret != -EINVAL)
dev_err(dev, "%s: could not parse property function\n",
of_node_full_name(np));
dev_err(dev, "%pOF: could not parse property function\n",
np);
function = NULL;
}
ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
&num_configs);
if (ret < 0) {
dev_err(dev, "%s: could not parse node property\n",
of_node_full_name(np));
dev_err(dev, "%pOF: could not parse node property\n", np);
return ret;
}

14
drivers/pinctrl/pinconf.c
View file

@ -37,7 +37,7 @@ int pinconf_check_ops(struct pinctrl_dev *pctldev)
return 0;
}
int pinconf_validate_map(struct pinctrl_map const *map, int i)
int pinconf_validate_map(const struct pinctrl_map *map, int i)
{
if (!map->data.configs.group_or_pin) {
pr_err("failed to register map %s (%d): no group/pin given\n",
@ -106,7 +106,7 @@ unlock:
return ret;
}
int pinconf_map_to_setting(struct pinctrl_map const *map,
int pinconf_map_to_setting(const struct pinctrl_map *map,
struct pinctrl_setting *setting)
{
struct pinctrl_dev *pctldev = setting->pctldev;
@ -143,11 +143,11 @@ int pinconf_map_to_setting(struct pinctrl_map const *map,
return 0;
}
void pinconf_free_setting(struct pinctrl_setting const *setting)
void pinconf_free_setting(const struct pinctrl_setting *setting)
{
}
int pinconf_apply_setting(struct pinctrl_setting const *setting)
int pinconf_apply_setting(const struct pinctrl_setting *setting)
{
struct pinctrl_dev *pctldev = setting->pctldev;
const struct pinconf_ops *ops = pctldev->desc->confops;
@ -205,7 +205,7 @@ int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned pin,
const struct pinconf_ops *ops;
ops = pctldev->desc->confops;
if (!ops)
if (!ops || !ops->pin_config_set)
return -ENOTSUPP;
return ops->pin_config_set(pctldev, pin, configs, nconfigs);
@ -235,7 +235,7 @@ static void pinconf_show_config(struct seq_file *s, struct pinctrl_dev *pctldev,
}
}
void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
void pinconf_show_map(struct seq_file *s, const struct pinctrl_map *map)
{
struct pinctrl_dev *pctldev;
@ -259,7 +259,7 @@ void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map)
}
void pinconf_show_setting(struct seq_file *s,
struct pinctrl_setting const *setting)
const struct pinctrl_setting *setting)
{
struct pinctrl_dev *pctldev = setting->pctldev;
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;

24
drivers/pinctrl/pinconf.h
View file

@ -14,11 +14,11 @@
#ifdef CONFIG_PINCONF
int pinconf_check_ops(struct pinctrl_dev *pctldev);
int pinconf_validate_map(struct pinctrl_map const *map, int i);
int pinconf_map_to_setting(struct pinctrl_map const *map,
int pinconf_validate_map(const struct pinctrl_map *map, int i);
int pinconf_map_to_setting(const struct pinctrl_map *map,
struct pinctrl_setting *setting);
void pinconf_free_setting(struct pinctrl_setting const *setting);
int pinconf_apply_setting(struct pinctrl_setting const *setting);
void pinconf_free_setting(const struct pinctrl_setting *setting);
int pinconf_apply_setting(const struct pinctrl_setting *setting);
int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned pin,
unsigned long *configs, size_t nconfigs);
@ -39,22 +39,22 @@ static inline int pinconf_check_ops(struct pinctrl_dev *pctldev)
return 0;
}
static inline int pinconf_validate_map(struct pinctrl_map const *map, int i)
static inline int pinconf_validate_map(const struct pinctrl_map *map, int i)
{
return 0;
}
static inline int pinconf_map_to_setting(struct pinctrl_map const *map,
static inline int pinconf_map_to_setting(const struct pinctrl_map *map,
struct pinctrl_setting *setting)
{
return 0;
}
static inline void pinconf_free_setting(struct pinctrl_setting const *setting)
static inline void pinconf_free_setting(const struct pinctrl_setting *setting)
{
}
static inline int pinconf_apply_setting(struct pinctrl_setting const *setting)
static inline int pinconf_apply_setting(const struct pinctrl_setting *setting)
{
return 0;
}
@ -69,21 +69,21 @@ static inline int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned pin,
#if defined(CONFIG_PINCONF) && defined(CONFIG_DEBUG_FS)
void pinconf_show_map(struct seq_file *s, struct pinctrl_map const *map);
void pinconf_show_map(struct seq_file *s, const struct pinctrl_map *map);
void pinconf_show_setting(struct seq_file *s,
struct pinctrl_setting const *setting);
const struct pinctrl_setting *setting);
void pinconf_init_device_debugfs(struct dentry *devroot,
struct pinctrl_dev *pctldev);
#else
static inline void pinconf_show_map(struct seq_file *s,
struct pinctrl_map const *map)
const struct pinctrl_map *map)
{
}
static inline void pinconf_show_setting(struct seq_file *s,
struct pinctrl_setting const *setting)
const struct pinctrl_setting *setting)
{
}

4
drivers/pinctrl/pinctrl-adi2.c
View file

@ -612,7 +612,7 @@ static int adi_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
return 0;
}
static struct pinctrl_ops adi_pctrl_ops = {
static const struct pinctrl_ops adi_pctrl_ops = {
.get_groups_count = adi_get_groups_count,
.get_group_name = adi_get_group_name,
.get_group_pins = adi_get_group_pins,
@ -696,7 +696,7 @@ static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev,
return 0;
}
static struct pinmux_ops adi_pinmux_ops = {
static const struct pinmux_ops adi_pinmux_ops = {
.set_mux = adi_pinmux_set,
.get_functions_count = adi_pinmux_get_funcs_count,
.get_function_name = adi_pinmux_get_func_name,

4
drivers/pinctrl/pinctrl-amd.c
View file

@ -760,8 +760,8 @@ static int amd_gpio_probe(struct platform_device *pdev)
irq_base = platform_get_irq(pdev, 0);
if (irq_base < 0) {
dev_err(&pdev->dev, "Failed to get gpio IRQ.\n");
return -EINVAL;
dev_err(&pdev->dev, "Failed to get gpio IRQ: %d\n", irq_base);
return irq_base;
}
gpio_dev->pdev = pdev;

2
drivers/pinctrl/pinctrl-artpec6.c
View file

@ -445,7 +445,7 @@ static unsigned int artpec6_pconf_drive_field_to_mA(int field)
}
}
static struct pinctrl_ops artpec6_pctrl_ops = {
static const struct pinctrl_ops artpec6_pctrl_ops = {
.get_group_pins = artpec6_get_group_pins,
.get_groups_count = artpec6_get_groups_count,
.get_group_name = artpec6_get_group_name,

11
drivers/pinctrl/pinctrl-at91-pio4.c
View file

@ -494,8 +494,8 @@ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
&num_configs);
if (ret < 0) {
dev_err(pctldev->dev, "%s: could not parse node property\n",
of_node_full_name(np));
dev_err(pctldev->dev, "%pOF: could not parse node property\n",
np);
return ret;
}
@ -504,8 +504,7 @@ static int atmel_pctl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
num_pins = pins->length / sizeof(u32);
if (!num_pins) {
dev_err(pctldev->dev, "no pins found in node %s\n",
of_node_full_name(np));
dev_err(pctldev->dev, "no pins found in node %pOF\n", np);
ret = -EINVAL;
goto exit;
}
@ -584,8 +583,8 @@ static int atmel_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
if (ret < 0) {
pinctrl_utils_free_map(pctldev, *map, *num_maps);
dev_err(pctldev->dev, "can't create maps for node %s\n",
np_config->full_name);
dev_err(pctldev->dev, "can't create maps for node %pOF\n",
np_config);
}
return ret;

2
drivers/pinctrl/pinctrl-coh901.c
View file

@ -387,7 +387,7 @@ int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
return 0;
}
static struct gpio_chip u300_gpio_chip = {
static const struct gpio_chip u300_gpio_chip = {
.label = "u300-gpio-chip",
.owner = THIS_MODULE,
.request = gpiochip_generic_request,

4
drivers/pinctrl/pinctrl-digicolor.c
View file

@ -79,7 +79,7 @@ static int dc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
return 0;
}
static struct pinctrl_ops dc_pinctrl_ops = {
static const struct pinctrl_ops dc_pinctrl_ops = {
.get_groups_count = dc_get_groups_count,
.get_group_name = dc_get_group_name,
.get_group_pins = dc_get_group_pins,
@ -161,7 +161,7 @@ static int dc_pmx_request_gpio(struct pinctrl_dev *pcdev,
return 0;
}
static struct pinmux_ops dc_pmxops = {
static const struct pinmux_ops dc_pmxops = {
.get_functions_count = dc_get_functions_count,
.get_function_name = dc_get_fname,
.get_function_groups = dc_get_groups,

2359
drivers/pinctrl/pinctrl-gemini.c Normal file
View file

File diff suppressed because it is too large Load diff

6
drivers/pinctrl/pinctrl-ingenic.c
View file

@ -460,7 +460,7 @@ static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
return val & BIT(idx);
}
static struct pinctrl_ops ingenic_pctlops = {
static const struct pinctrl_ops ingenic_pctlops = {
.get_groups_count = pinctrl_generic_get_group_count,
.get_group_name = pinctrl_generic_get_group_name,
.get_group_pins = pinctrl_generic_get_group_pins,
@ -543,7 +543,7 @@ static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
return 0;
}
static struct pinmux_ops ingenic_pmxops = {
static const struct pinmux_ops ingenic_pmxops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
@ -696,7 +696,7 @@ static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
return 0;
}
static struct pinconf_ops ingenic_confops = {
static const struct pinconf_ops ingenic_confops = {
.is_generic = true,
.pin_config_get = ingenic_pinconf_get,
.pin_config_set = ingenic_pinconf_set,

313
drivers/pinctrl/pinctrl-rockchip.c
View file

@ -62,6 +62,7 @@ enum rockchip_pinctrl_type {
RV1108,
RK2928,
RK3066B,
RK3128,
RK3188,
RK3288,
RK3368,
@ -76,7 +77,6 @@ enum rockchip_pinctrl_type {
#define IOMUX_SOURCE_PMU BIT(2)
#define IOMUX_UNROUTED BIT(3)
#define IOMUX_WIDTH_3BIT BIT(4)
#define IOMUX_RECALCED BIT(5)
/**
* @type: iomux variant using IOMUX_* constants
@ -166,6 +166,7 @@ struct rockchip_pin_bank {
struct pinctrl_gpio_range grange;
raw_spinlock_t slock;
u32 toggle_edge_mode;
u32 recalced_mask;
u32 route_mask;
};
@ -289,6 +290,22 @@ struct rockchip_pin_bank {
.pull_type[3] = pull3, \
}
/**
* struct rockchip_mux_recalced_data: represent a pin iomux data.
* @num: bank number.
* @pin: pin number.
* @bit: index at register.
* @reg: register offset.
* @mask: mask bit
*/
struct rockchip_mux_recalced_data {
u8 num;
u8 pin;
u32 reg;
u8 bit;
u8 mask;
};
/**
* struct rockchip_mux_recalced_data: represent a pin iomux data.
* @bank_num: bank number.
@ -317,6 +334,8 @@ struct rockchip_pin_ctrl {
int pmu_mux_offset;
int grf_drv_offset;
int pmu_drv_offset;
struct rockchip_mux_recalced_data *iomux_recalced;
u32 niomux_recalced;
struct rockchip_mux_route_data *iomux_routes;
u32 niomux_routes;
@ -326,8 +345,6 @@ struct rockchip_pin_ctrl {
void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
void (*iomux_recalc)(u8 bank_num, int pin, int *reg,
u8 *bit, int *mask);
int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit);
@ -382,22 +399,6 @@ struct rockchip_pinctrl {
unsigned int nfunctions;
};
/**
* struct rockchip_mux_recalced_data: represent a pin iomux data.
* @num: bank number.
* @pin: pin number.
* @bit: index at register.
* @reg: register offset.
* @mask: mask bit
*/
struct rockchip_mux_recalced_data {
u8 num;
u8 pin;
u8 reg;
u8 bit;
u8 mask;
};
static struct regmap_config rockchip_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
@ -557,7 +558,105 @@ static const struct pinctrl_ops rockchip_pctrl_ops = {
* Hardware access
*/
static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
{
.num = 1,
.pin = 0,
.reg = 0x418,
.bit = 0,
.mask = 0x3
}, {
.num = 1,
.pin = 1,
.reg = 0x418,
.bit = 2,
.mask = 0x3
}, {
.num = 1,
.pin = 2,
.reg = 0x418,
.bit = 4,
.mask = 0x3
}, {
.num = 1,
.pin = 3,
.reg = 0x418,
.bit = 6,
.mask = 0x3
}, {
.num = 1,
.pin = 4,
.reg = 0x418,
.bit = 8,
.mask = 0x3
}, {
.num = 1,
.pin = 5,
.reg = 0x418,
.bit = 10,
.mask = 0x3
}, {
.num = 1,
.pin = 6,
.reg = 0x418,
.bit = 12,
.mask = 0x3
}, {
.num = 1,
.pin = 7,
.reg = 0x418,
.bit = 14,
.mask = 0x3
}, {
.num = 1,
.pin = 8,
.reg = 0x41c,
.bit = 0,
.mask = 0x3
}, {
.num = 1,
.pin = 9,
.reg = 0x41c,
.bit = 2,
.mask = 0x3
},
};
static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
{
.num = 2,
.pin = 20,
.reg = 0xe8,
.bit = 0,
.mask = 0x7
}, {
.num = 2,
.pin = 21,
.reg = 0xe8,
.bit = 4,
.mask = 0x7
}, {
.num = 2,
.pin = 22,
.reg = 0xe8,
.bit = 8,
.mask = 0x7
}, {
.num = 2,
.pin = 23,
.reg = 0xe8,
.bit = 12,
.mask = 0x7
}, {
.num = 2,
.pin = 24,
.reg = 0xd4,
.bit = 12,
.mask = 0x7
},
};
static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
{
.num = 2,
.pin = 12,
@ -579,20 +678,22 @@ static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
},
};
static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg,
u8 *bit, int *mask)
static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
int *reg, u8 *bit, int *mask)
{
const struct rockchip_mux_recalced_data *data = NULL;
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
struct rockchip_mux_recalced_data *data;
int i;
for (i = 0; i < ARRAY_SIZE(rk3328_mux_recalced_data); i++)
if (rk3328_mux_recalced_data[i].num == bank_num &&
rk3328_mux_recalced_data[i].pin == pin) {
data = &rk3328_mux_recalced_data[i];
for (i = 0; i < ctrl->niomux_recalced; i++) {
data = &ctrl->iomux_recalced[i];
if (data->num == bank->bank_num &&
data->pin == pin)
break;
}
if (!data)
if (i >= ctrl->niomux_recalced)
return;
*reg = data->reg;
@ -600,6 +701,59 @@ static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg,
*bit = data->bit;
}
static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
{
/* spi-0 */
.bank_num = 1,
.pin = 10,
.func = 1,
.route_offset = 0x144,
.route_val = BIT(16 + 3) | BIT(16 + 4),
}, {
/* spi-1 */
.bank_num = 1,
.pin = 27,
.func = 3,
.route_offset = 0x144,
.route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
}, {
/* spi-2 */
.bank_num = 0,
.pin = 13,
.func = 2,
.route_offset = 0x144,
.route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
}, {
/* i2s-0 */
.bank_num = 1,
.pin = 5,
.func = 1,
.route_offset = 0x144,
.route_val = BIT(16 + 5),
}, {
/* i2s-1 */
.bank_num = 0,
.pin = 14,
.func = 1,
.route_offset = 0x144,
.route_val = BIT(16 + 5) | BIT(5),
}, {
/* emmc-0 */
.bank_num = 1,
.pin = 22,
.func = 2,
.route_offset = 0x144,
.route_val = BIT(16 + 6),
}, {
/* emmc-1 */
.bank_num = 2,
.pin = 4,
.func = 2,
.route_offset = 0x144,
.route_val = BIT(16 + 6) | BIT(6),
},
};
static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
{
/* pwm0-0 */
@ -877,7 +1031,6 @@ static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
int iomux_num = (pin / 8);
struct regmap *regmap;
unsigned int val;
@ -916,8 +1069,8 @@ static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
mask = 0x3;
}
if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
ctrl->iomux_recalc(bank->bank_num, pin, &reg, &bit, &mask);
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
ret = regmap_read(regmap, reg, &val);
if (ret)
@ -967,7 +1120,6 @@ static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
{
struct rockchip_pinctrl *info = bank->drvdata;
struct rockchip_pin_ctrl *ctrl = info->ctrl;
int iomux_num = (pin / 8);
struct regmap *regmap;
int reg, ret, mask, mux_type;
@ -1005,8 +1157,8 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
mask = 0x3;
}
if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
ctrl->iomux_recalc(bank->bank_num, pin, &reg, &bit, &mask);
if (bank->recalced_mask & BIT(pin))
rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
if (bank->route_mask & BIT(pin)) {
if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
@ -1084,6 +1236,36 @@ static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
*bit *= RV1108_DRV_BITS_PER_PIN;
}
#define RV1108_SCHMITT_PMU_OFFSET 0x30
#define RV1108_SCHMITT_GRF_OFFSET 0x388
#define RV1108_SCHMITT_BANK_STRIDE 8
#define RV1108_SCHMITT_PINS_PER_GRF_REG 16
#define RV1108_SCHMITT_PINS_PER_PMU_REG 8
static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num,
struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
int pins_per_reg;
if (bank->bank_num == 0) {
*regmap = info->regmap_pmu;
*reg = RV1108_SCHMITT_PMU_OFFSET;
pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
} else {
*regmap = info->regmap_base;
*reg = RV1108_SCHMITT_GRF_OFFSET;
pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
*reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
}
*reg += ((pin_num / pins_per_reg) * 4);
*bit = pin_num % pins_per_reg;
return 0;
}
#define RK2928_PULL_OFFSET 0x118
#define RK2928_PULL_PINS_PER_REG 16
#define RK2928_PULL_BANK_STRIDE 8
@ -1102,6 +1284,22 @@ static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
*bit = pin_num % RK2928_PULL_PINS_PER_REG;
};
#define RK3128_PULL_OFFSET 0x118
static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
int pin_num, struct regmap **regmap,
int *reg, u8 *bit)
{
struct rockchip_pinctrl *info = bank->drvdata;
*regmap = info->regmap_base;
*reg = RK3128_PULL_OFFSET;
*reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
*reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
*bit = pin_num % RK2928_PULL_PINS_PER_REG;
}
#define RK3188_PULL_OFFSET 0x164
#define RK3188_PULL_BITS_PER_PIN 2
#define RK3188_PULL_PINS_PER_REG 8
@ -1571,6 +1769,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
switch (ctrl->type) {
case RK2928:
case RK3128:
return !(data & BIT(bit))
? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
: PIN_CONFIG_BIAS_DISABLE;
@ -1611,6 +1810,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
switch (ctrl->type) {
case RK2928:
case RK3128:
data = BIT(bit + 16);
if (pull == PIN_CONFIG_BIAS_DISABLE)
data |= BIT(bit);
@ -1865,6 +2065,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
{
switch (ctrl->type) {
case RK2928:
case RK3128:
return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
pull == PIN_CONFIG_BIAS_DISABLE);
case RK3066B:
@ -2853,6 +3054,16 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
bank_pins += 8;
}
/* calculate the per-bank recalced_mask */
for (j = 0; j < ctrl->niomux_recalced; j++) {
int pin = 0;
if (ctrl->iomux_recalced[j].num == bank->bank_num) {
pin = ctrl->iomux_recalced[j].pin;
bank->recalced_mask |= BIT(pin);
}
}
/* calculate the per-bank route_mask */
for (j = 0; j < ctrl->niomux_routes; j++) {
int pin = 0;
@ -3015,8 +3226,11 @@ static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
.type = RV1108,
.grf_mux_offset = 0x10,
.pmu_mux_offset = 0x0,
.iomux_recalced = rv1108_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
.pull_calc_reg = rv1108_calc_pull_reg_and_bit,
.drv_calc_reg = rv1108_calc_drv_reg_and_bit,
.schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
};
static struct rockchip_pin_bank rk2928_pin_banks[] = {
@ -3083,6 +3297,26 @@ static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
.grf_mux_offset = 0x60,
};
static struct rockchip_pin_bank rk3128_pin_banks[] = {
PIN_BANK(0, 32, "gpio0"),
PIN_BANK(1, 32, "gpio1"),
PIN_BANK(2, 32, "gpio2"),
PIN_BANK(3, 32, "gpio3"),
};
static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
.pin_banks = rk3128_pin_banks,
.nr_banks = ARRAY_SIZE(rk3128_pin_banks),
.label = "RK3128-GPIO",
.type = RK3128,
.grf_mux_offset = 0xa8,
.iomux_recalced = rk3128_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
.iomux_routes = rk3128_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
.pull_calc_reg = rk3128_calc_pull_reg_and_bit,
};
static struct rockchip_pin_bank rk3188_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
PIN_BANK(1, 32, "gpio1"),
@ -3165,12 +3399,12 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
IOMUX_WIDTH_3BIT,
IOMUX_WIDTH_3BIT,
0),
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
IOMUX_WIDTH_3BIT,
IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
IOMUX_WIDTH_3BIT,
0,
0),
};
@ -3181,11 +3415,12 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
.label = "RK3328-GPIO",
.type = RK3288,
.grf_mux_offset = 0x0,
.iomux_recalced = rk3328_mux_recalced_data,
.niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
.iomux_routes = rk3328_mux_route_data,
.niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
.pull_calc_reg = rk3228_calc_pull_reg_and_bit,
.drv_calc_reg = rk3228_calc_drv_reg_and_bit,
.iomux_recalc = rk3328_recalc_mux,
.schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
};
@ -3290,6 +3525,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = &rk3066a_pin_ctrl },
{ .compatible = "rockchip,rk3066b-pinctrl",
.data = &rk3066b_pin_ctrl },
{ .compatible = "rockchip,rk3128-pinctrl",
.data = (void *)&rk3128_pin_ctrl },
{ .compatible = "rockchip,rk3188-pinctrl",
.data = &rk3188_pin_ctrl },
{ .compatible = "rockchip,rk3228-pinctrl",

10
drivers/pinctrl/pinctrl-rza1.c
View file

@ -723,7 +723,7 @@ static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio,
rza1_pin_set(port, gpio, value);
}
static struct gpio_chip rza1_gpiochip_template = {
static const struct gpio_chip rza1_gpiochip_template = {
.request = rza1_gpio_request,
.free = rza1_gpio_free,
.get_direction = rza1_gpio_get_direction,
@ -1026,7 +1026,7 @@ static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
return 0;
}
static struct pinmux_ops rza1_pinmux_ops = {
static const struct pinmux_ops rza1_pinmux_ops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
@ -1088,7 +1088,7 @@ static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
*/
pinctrl_base = of_args.args[1];
gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base);
if (gpioport > RZA1_NPORTS) {
if (gpioport >= RZA1_NPORTS) {
dev_err(rza1_pctl->dev,
"Invalid values in property %s\n", list_name);
return -EINVAL;
@ -1096,8 +1096,8 @@ static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
*chip = rza1_gpiochip_template;
chip->base = -1;
chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%s-%u",
np->name, gpioport);
chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%s",
np->name);
chip->ngpio = of_args.args[2];
chip->of_node = np;
chip->parent = rza1_pctl->dev;

12
drivers/pinctrl/pinctrl-st.c
View file

@ -861,7 +861,7 @@ static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev,
{
}
static struct pinctrl_ops st_pctlops = {
static const struct pinctrl_ops st_pctlops = {
.get_groups_count = st_pctl_get_groups_count,
.get_group_pins = st_pctl_get_group_pins,
.get_group_name = st_pctl_get_group_name,
@ -928,7 +928,7 @@ static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
return 0;
}
static struct pinmux_ops st_pmxops = {
static const struct pinmux_ops st_pmxops = {
.get_functions_count = st_pmx_get_funcs_count,
.get_function_name = st_pmx_get_fname,
.get_function_groups = st_pmx_get_groups,
@ -1025,7 +1025,7 @@ static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,
ST_PINCONF_UNPACK_RT_DELAY(config));
}
static struct pinconf_ops st_confops = {
static const struct pinconf_ops st_confops = {
.pin_config_get = st_pinconf_get,
.pin_config_set = st_pinconf_set,
.pin_config_dbg_show = st_pinconf_dbg_show,
@ -1442,7 +1442,7 @@ static void st_gpio_irqmux_handler(struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
static struct gpio_chip st_gpio_template = {
static const struct gpio_chip st_gpio_template = {
.request = gpiochip_generic_request,
.free = gpiochip_generic_free,
.get = st_gpio_get,
@ -1521,7 +1521,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
* [irqN]----> [gpio-bank (n)]
*/
if (of_irq_to_resource(np, 0, &irq_res)) {
if (of_irq_to_resource(np, 0, &irq_res) > 0) {
gpio_irq = irq_res.start;
gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip,
gpio_irq, st_gpio_irq_handler);
@ -1537,7 +1537,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
return err;
}
} else {
dev_info(dev, "No IRQ support for %s bank\n", np->full_name);
dev_info(dev, "No IRQ support for %pOF bank\n", np);
}
return 0;

8
drivers/pinctrl/pinctrl-tb10x.c
View file

@ -557,8 +557,8 @@ static int tb10x_dt_node_to_map(struct pinctrl_dev *pctl,
int ret = 0;
if (of_property_read_string(np_config, "abilis,function", &string)) {
pr_err("%s: No abilis,function property in device tree.\n",
np_config->full_name);
pr_err("%pOF: No abilis,function property in device tree.\n",
np_config);
return -EINVAL;
}
@ -577,7 +577,7 @@ out:
return ret;
}
static struct pinctrl_ops tb10x_pinctrl_ops = {
static const struct pinctrl_ops tb10x_pinctrl_ops = {
.get_groups_count = tb10x_get_groups_count,
.get_group_name = tb10x_get_group_name,
.get_group_pins = tb10x_get_group_pins,
@ -738,7 +738,7 @@ static int tb10x_pctl_set_mux(struct pinctrl_dev *pctl,
return 0;
}
static struct pinmux_ops tb10x_pinmux_ops = {
static const struct pinmux_ops tb10x_pinmux_ops = {
.get_functions_count = tb10x_get_functions_count,
.get_function_name = tb10x_get_function_name,
.get_function_groups = tb10x_get_function_groups,

6
drivers/pinctrl/pinctrl-tz1090-pdc.c
View file

@ -486,7 +486,7 @@ static int tz1090_pdc_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
return 0;
}
static struct pinctrl_ops tz1090_pdc_pinctrl_ops = {
static const struct pinctrl_ops tz1090_pdc_pinctrl_ops = {
.get_groups_count = tz1090_pdc_pinctrl_get_groups_count,
.get_group_name = tz1090_pdc_pinctrl_get_group_name,
.get_group_pins = tz1090_pdc_pinctrl_get_group_pins,
@ -631,7 +631,7 @@ static void tz1090_pdc_pinctrl_gpio_disable_free(
}
}
static struct pinmux_ops tz1090_pdc_pinmux_ops = {
static const struct pinmux_ops tz1090_pdc_pinmux_ops = {
.get_functions_count = tz1090_pdc_pinctrl_get_funcs_count,
.get_function_name = tz1090_pdc_pinctrl_get_func_name,
.get_function_groups = tz1090_pdc_pinctrl_get_func_groups,
@ -905,7 +905,7 @@ next_config:
return 0;
}
static struct pinconf_ops tz1090_pdc_pinconf_ops = {
static const struct pinconf_ops tz1090_pdc_pinconf_ops = {
.is_generic = true,
.pin_config_get = tz1090_pdc_pinconf_get,
.pin_config_set = tz1090_pdc_pinconf_set,

6
drivers/pinctrl/pinctrl-tz1090.c
View file

@ -1201,7 +1201,7 @@ static int tz1090_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
return 0;
}
static struct pinctrl_ops tz1090_pinctrl_ops = {
static const struct pinctrl_ops tz1090_pinctrl_ops = {
.get_groups_count = tz1090_pinctrl_get_groups_count,
.get_group_name = tz1090_pinctrl_get_group_name,
.get_group_pins = tz1090_pinctrl_get_group_pins,
@ -1513,7 +1513,7 @@ static void tz1090_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev,
tz1090_pinctrl_gpio_select(pmx, pin, false);
}
static struct pinmux_ops tz1090_pinmux_ops = {
static const struct pinmux_ops tz1090_pinmux_ops = {
.get_functions_count = tz1090_pinctrl_get_funcs_count,
.get_function_name = tz1090_pinctrl_get_func_name,
.get_function_groups = tz1090_pinctrl_get_func_groups,
@ -1920,7 +1920,7 @@ next_config:
return 0;
}
static struct pinconf_ops tz1090_pinconf_ops = {
static const struct pinconf_ops tz1090_pinconf_ops = {
.is_generic = true,
.pin_config_get = tz1090_pinconf_get,
.pin_config_set = tz1090_pinconf_set,

34
drivers/pinctrl/pinctrl-zynq.c
View file

@ -45,7 +45,7 @@
* @syscon: Syscon regmap
* @pctrl_offset: Offset for pinctrl into the @syscon space
* @groups: Pingroups
* @ngroupos: Number of @groups
* @ngroups: Number of @groups
* @funcs: Pinmux functions
* @nfuncs: Number of @funcs
*/
@ -62,7 +62,7 @@ struct zynq_pinctrl {
struct zynq_pctrl_group {
const char *name;
const unsigned int *pins;
const unsigned npins;
const unsigned int npins;
};
/**
@ -841,7 +841,7 @@ static int zynq_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
}
static const char *zynq_pctrl_get_group_name(struct pinctrl_dev *pctldev,
unsigned selector)
unsigned int selector)
{
struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
@ -849,9 +849,9 @@ static const char *zynq_pctrl_get_group_name(struct pinctrl_dev *pctldev,
}
static int zynq_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
unsigned selector,
const unsigned **pins,
unsigned *num_pins)
unsigned int selector,
const unsigned int **pins,
unsigned int *num_pins)
{
struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
@ -878,7 +878,7 @@ static int zynq_pmux_get_functions_count(struct pinctrl_dev *pctldev)
}
static const char *zynq_pmux_get_function_name(struct pinctrl_dev *pctldev,
unsigned selector)
unsigned int selector)
{
struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
@ -886,7 +886,7 @@ static const char *zynq_pmux_get_function_name(struct pinctrl_dev *pctldev,
}
static int zynq_pmux_get_function_groups(struct pinctrl_dev *pctldev,
unsigned selector,
unsigned int selector,
const char * const **groups,
unsigned * const num_groups)
{
@ -898,8 +898,8 @@ static int zynq_pmux_get_function_groups(struct pinctrl_dev *pctldev,
}
static int zynq_pinmux_set_mux(struct pinctrl_dev *pctldev,
unsigned function,
unsigned group)
unsigned int function,
unsigned int group)
{
int i, ret;
struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
@ -986,8 +986,8 @@ static const struct pinconf_generic_params zynq_dt_params[] = {
};
#ifdef CONFIG_DEBUG_FS
static const struct pin_config_item zynq_conf_items[ARRAY_SIZE(zynq_dt_params)] = {
PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true),
static const struct pin_config_item zynq_conf_items[ARRAY_SIZE(zynq_dt_params)]
= { PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true),
};
#endif
@ -997,7 +997,7 @@ static unsigned int zynq_pinconf_iostd_get(u32 reg)
}
static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned int pin,
unsigned long *config)
{
u32 reg;
@ -1054,9 +1054,9 @@ static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
}
static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev,
unsigned pin,
unsigned int pin,
unsigned long *configs,
unsigned num_configs)
unsigned int num_configs)
{
int i, ret;
u32 reg;
@ -1130,9 +1130,9 @@ static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev,
}
static int zynq_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned selector,
unsigned int selector,
unsigned long *configs,
unsigned num_configs)
unsigned int num_configs)
{
int i, ret;
struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);

16
drivers/pinctrl/pinmux.c
View file

@ -61,7 +61,7 @@ int pinmux_check_ops(struct pinctrl_dev *pctldev)
return 0;
}
int pinmux_validate_map(struct pinctrl_map const *map, int i)
int pinmux_validate_map(const struct pinctrl_map *map, int i)
{
if (!map->data.mux.function) {
pr_err("failed to register map %s (%d): no function given\n",
@ -312,7 +312,7 @@ static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev,
return -EINVAL;
}
int pinmux_map_to_setting(struct pinctrl_map const *map,
int pinmux_map_to_setting(const struct pinctrl_map *map,
struct pinctrl_setting *setting)
{
struct pinctrl_dev *pctldev = setting->pctldev;
@ -372,12 +372,12 @@ int pinmux_map_to_setting(struct pinctrl_map const *map,
return 0;
}
void pinmux_free_setting(struct pinctrl_setting const *setting)
void pinmux_free_setting(const struct pinctrl_setting *setting)
{
/* This function is currently unused */
}
int pinmux_enable_setting(struct pinctrl_setting const *setting)
int pinmux_enable_setting(const struct pinctrl_setting *setting)
{
struct pinctrl_dev *pctldev = setting->pctldev;
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
@ -458,7 +458,7 @@ err_pin_request:
return ret;
}
void pinmux_disable_setting(struct pinctrl_setting const *setting)
void pinmux_disable_setting(const struct pinctrl_setting *setting)
{
struct pinctrl_dev *pctldev = setting->pctldev;
const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
@ -627,7 +627,7 @@ static int pinmux_pins_show(struct seq_file *s, void *what)
return 0;
}
void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map)
void pinmux_show_map(struct seq_file *s, const struct pinctrl_map *map)
{
seq_printf(s, "group %s\nfunction %s\n",
map->data.mux.group ? map->data.mux.group : "(default)",
@ -635,7 +635,7 @@ void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map)
}
void pinmux_show_setting(struct seq_file *s,
struct pinctrl_setting const *setting)
const struct pinctrl_setting *setting)
{
struct pinctrl_dev *pctldev = setting->pctldev;
const struct pinmux_ops *pmxops = pctldev->desc->pmxops;
@ -833,7 +833,7 @@ EXPORT_SYMBOL_GPL(pinmux_generic_remove_function);
void pinmux_generic_free_functions(struct pinctrl_dev *pctldev)
{
struct radix_tree_iter iter;
void **slot;
void __rcu **slot;
radix_tree_for_each_slot(slot, &pctldev->pin_function_tree, &iter, 0)
radix_tree_delete(&pctldev->pin_function_tree, iter.index);

29
drivers/pinctrl/pinmux.h
View file

@ -14,7 +14,7 @@
int pinmux_check_ops(struct pinctrl_dev *pctldev);
int pinmux_validate_map(struct pinctrl_map const *map, int i);
int pinmux_validate_map(const struct pinctrl_map *map, int i);
int pinmux_request_gpio(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
@ -25,11 +25,11 @@ int pinmux_gpio_direction(struct pinctrl_dev *pctldev,
struct pinctrl_gpio_range *range,
unsigned pin, bool input);
int pinmux_map_to_setting(struct pinctrl_map const *map,
int pinmux_map_to_setting(const struct pinctrl_map *map,
struct pinctrl_setting *setting);
void pinmux_free_setting(struct pinctrl_setting const *setting);
int pinmux_enable_setting(struct pinctrl_setting const *setting);
void pinmux_disable_setting(struct pinctrl_setting const *setting);
void pinmux_free_setting(const struct pinctrl_setting *setting);
int pinmux_enable_setting(const struct pinctrl_setting *setting);
void pinmux_disable_setting(const struct pinctrl_setting *setting);
#else
@ -38,7 +38,7 @@ static inline int pinmux_check_ops(struct pinctrl_dev *pctldev)
return 0;
}
static inline int pinmux_validate_map(struct pinctrl_map const *map, int i)
static inline int pinmux_validate_map(const struct pinctrl_map *map, int i)
{
return 0;
}
@ -63,23 +63,22 @@ static inline int pinmux_gpio_direction(struct pinctrl_dev *pctldev,
return 0;
}
static inline int pinmux_map_to_setting(struct pinctrl_map const *map,
static inline int pinmux_map_to_setting(const struct pinctrl_map *map,
struct pinctrl_setting *setting)
{
return 0;
}
static inline void pinmux_free_setting(struct pinctrl_setting const *setting)
static inline void pinmux_free_setting(const struct pinctrl_setting *setting)
{
}
static inline int pinmux_enable_setting(struct pinctrl_setting const *setting)
static inline int pinmux_enable_setting(const struct pinctrl_setting *setting)
{
return 0;
}
static inline void pinmux_disable_setting(
struct pinctrl_setting const *setting)
static inline void pinmux_disable_setting(const struct pinctrl_setting *setting)
{
}
@ -87,21 +86,21 @@ static inline void pinmux_disable_setting(
#if defined(CONFIG_PINMUX) && defined(CONFIG_DEBUG_FS)
void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map);
void pinmux_show_map(struct seq_file *s, const struct pinctrl_map *map);
void pinmux_show_setting(struct seq_file *s,
struct pinctrl_setting const *setting);
const struct pinctrl_setting *setting);
void pinmux_init_device_debugfs(struct dentry *devroot,
struct pinctrl_dev *pctldev);
#else
static inline void pinmux_show_map(struct seq_file *s,
struct pinctrl_map const *map)
const struct pinctrl_map *map)
{
}
static inline void pinmux_show_setting(struct seq_file *s,
struct pinctrl_setting const *setting)
const struct pinctrl_setting *setting)
{
}

42
drivers/pinctrl/qcom/pinctrl-apq8064.c
View file

@ -295,6 +295,12 @@ enum apq8064_functions {
APQ_MUX_cam_mclk,
APQ_MUX_codec_mic_i2s,
APQ_MUX_codec_spkr_i2s,
APQ_MUX_gp_clk_0a,
APQ_MUX_gp_clk_0b,
APQ_MUX_gp_clk_1a,
APQ_MUX_gp_clk_1b,
APQ_MUX_gp_clk_2a,
APQ_MUX_gp_clk_2b,
APQ_MUX_gpio,
APQ_MUX_gsbi1,
APQ_MUX_gsbi2,
@ -354,6 +360,24 @@ static const char * const gpio_groups[] = {
"gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
"gpio85", "gpio86", "gpio87", "gpio88", "gpio89"
};
static const char * const gp_clk_0a_groups[] = {
"gpio3"
};
static const char * const gp_clk_0b_groups[] = {
"gpio34"
};
static const char * const gp_clk_1a_groups[] = {
"gpio4"
};
static const char * const gp_clk_1b_groups[] = {
"gpio50"
};
static const char * const gp_clk_2a_groups[] = {
"gpio32"
};
static const char * const gp_clk_2b_groups[] = {
"gpio25"
};
static const char * const ps_hold_groups[] = {
"gpio78"
};
@ -452,6 +476,12 @@ static const struct msm_function apq8064_functions[] = {
FUNCTION(cam_mclk),
FUNCTION(codec_mic_i2s),
FUNCTION(codec_spkr_i2s),
FUNCTION(gp_clk_0a),
FUNCTION(gp_clk_0b),
FUNCTION(gp_clk_1a),
FUNCTION(gp_clk_1b),
FUNCTION(gp_clk_2a),
FUNCTION(gp_clk_2b),
FUNCTION(gpio),
FUNCTION(gsbi1),
FUNCTION(gsbi2),
@ -490,8 +520,8 @@ static const struct msm_pingroup apq8064_groups[] = {
PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(4, NA, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(3, NA, gp_clk_0a, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(4, NA, NA, cam_mclk, gp_clk_1a, NA, NA, NA, NA, NA, NA),
PINGROUP(5, NA, cam_mclk, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(6, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(7, gsbi3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
@ -512,16 +542,16 @@ static const struct msm_pingroup apq8064_groups[] = {
PINGROUP(22, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(25, gsbi2, gp_clk_2b, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(27, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(28, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(29, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(30, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(31, mi2s, NA, gsbi5_spi_cs2, gsbi6_spi_cs2, gsbi7_spi_cs2, NA, NA, NA, NA, NA),
PINGROUP(32, mi2s, NA, NA, NA, NA, gsbi5_spi_cs3, gsbi6_spi_cs3, gsbi7_spi_cs3, NA, NA),
PINGROUP(32, mi2s, gp_clk_2a, NA, NA, NA, gsbi5_spi_cs3, gsbi6_spi_cs3, gsbi7_spi_cs3, NA, NA),
PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(34, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(34, codec_mic_i2s, gp_clk_0b, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(35, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(36, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(37, codec_mic_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
@ -537,7 +567,7 @@ static const struct msm_pingroup apq8064_groups[] = {
PINGROUP(47, spkr_i2s, gsbi5_spi_cs1, gsbi6_spi_cs1, gsbi7_spi_cs1, NA, NA, NA, NA, NA, NA),
PINGROUP(48, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(49, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(50, spkr_i2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(50, spkr_i2s, gp_clk_1b, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(51, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(52, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(53, NA, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA),

432
drivers/pinctrl/qcom/pinctrl-ipq4019.c
View file

@ -277,12 +277,49 @@ DECLARE_QCA_GPIO_PINS(99);
enum ipq4019_functions {
qca_mux_gpio,
qca_mux_blsp_uart1,
qca_mux_aud_pin,
qca_mux_audio_pwm,
qca_mux_blsp_i2c0,
qca_mux_blsp_i2c1,
qca_mux_blsp_uart0,
qca_mux_blsp_spi1,
qca_mux_blsp_spi0,
qca_mux_blsp_spi1,
qca_mux_blsp_uart0,
qca_mux_blsp_uart1,
qca_mux_chip_rst,
qca_mux_i2s_rx,
qca_mux_i2s_spdif_in,
qca_mux_i2s_spdif_out,
qca_mux_i2s_td,
qca_mux_i2s_tx,
qca_mux_jtag,
qca_mux_led0,
qca_mux_led1,
qca_mux_led2,
qca_mux_led3,
qca_mux_led4,
qca_mux_led5,
qca_mux_led6,
qca_mux_led7,
qca_mux_led8,
qca_mux_led9,
qca_mux_led10,
qca_mux_led11,
qca_mux_mdc,
qca_mux_mdio,
qca_mux_pcie,
qca_mux_pmu,
qca_mux_prng_rosc,
qca_mux_qpic,
qca_mux_rgmii,
qca_mux_rmii,
qca_mux_sdio,
qca_mux_smart0,
qca_mux_smart1,
qca_mux_smart2,
qca_mux_smart3,
qca_mux_tm,
qca_mux_wifi0,
qca_mux_wifi1,
qca_mux_NA,
};
@ -303,108 +340,331 @@ static const char * const gpio_groups[] = {
"gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
"gpio99",
};
static const char * const blsp_uart1_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio11",
static const char * const aud_pin_groups[] = {
"gpio48", "gpio49", "gpio50", "gpio51",
};
static const char * const audio_pwm_groups[] = {
"gpio30", "gpio31", "gpio32", "gpio33", "gpio64", "gpio65", "gpio66",
"gpio67",
};
static const char * const blsp_i2c0_groups[] = {
"gpio10", "gpio11", "gpio20", "gpio21", "gpio58", "gpio59",
};
static const char * const blsp_spi0_groups[] = {
"gpio12", "gpio13", "gpio14", "gpio15", "gpio45",
"gpio54", "gpio55", "gpio56", "gpio57",
};
static const char * const blsp_i2c1_groups[] = {
"gpio12", "gpio13", "gpio34", "gpio35",
};
static const char * const blsp_uart0_groups[] = {
"gpio16", "gpio17", "gpio60", "gpio61",
static const char * const blsp_spi0_groups[] = {
"gpio12", "gpio13", "gpio14", "gpio15", "gpio45", "gpio54", "gpio55",
"gpio56", "gpio57",
};
static const char * const blsp_spi1_groups[] = {
"gpio44", "gpio45", "gpio46", "gpio47",
};
static const char * const blsp_uart0_groups[] = {
"gpio16", "gpio17", "gpio60", "gpio61",
};
static const char * const blsp_uart1_groups[] = {
"gpio8", "gpio9", "gpio10", "gpio11",
};
static const char * const chip_rst_groups[] = {
"gpio62",
};
static const char * const i2s_rx_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio20", "gpio21", "gpio22", "gpio23",
"gpio58", "gpio60", "gpio61", "gpio63",
};
static const char * const i2s_spdif_in_groups[] = {
"gpio34", "gpio59", "gpio63",
};
static const char * const i2s_spdif_out_groups[] = {
"gpio35", "gpio62", "gpio63",
};
static const char * const i2s_td_groups[] = {
"gpio27", "gpio28", "gpio29", "gpio54", "gpio55", "gpio56", "gpio63",
};
static const char * const i2s_tx_groups[] = {
"gpio24", "gpio25", "gpio26", "gpio52", "gpio53", "gpio57", "gpio60",
"gpio61",
};
static const char * const jtag_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5",
};
static const char * const led0_groups[] = {
"gpio16", "gpio36", "gpio60",
};
static const char * const led1_groups[] = {
"gpio17", "gpio37", "gpio61",
};
static const char * const led2_groups[] = {
"gpio36", "gpio38", "gpio58",
};
static const char * const led3_groups[] = {
"gpio39",
};
static const char * const led4_groups[] = {
"gpio40",
};
static const char * const led5_groups[] = {
"gpio44",
};
static const char * const led6_groups[] = {
"gpio45",
};
static const char * const led7_groups[] = {
"gpio46",
};
static const char * const led8_groups[] = {
"gpio47",
};
static const char * const led9_groups[] = {
"gpio48",
};
static const char * const led10_groups[] = {
"gpio49",
};
static const char * const led11_groups[] = {
"gpio50",
};
static const char * const mdc_groups[] = {
"gpio7", "gpio52",
};
static const char * const mdio_groups[] = {
"gpio6", "gpio53",
};
static const char * const pcie_groups[] = {
"gpio39", "gpio52",
};
static const char * const pmu_groups[] = {
"gpio54", "gpio55",
};
static const char * const prng_rosc_groups[] = {
"gpio53",
};
static const char * const qpic_groups[] = {
"gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58",
"gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio64", "gpio65",
"gpio66", "gpio67", "gpio68", "gpio69",
};
static const char * const rgmii_groups[] = {
"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
"gpio29", "gpio30", "gpio31", "gpio32", "gpio33",
};
static const char * const rmii_groups[] = {
"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
"gpio50", "gpio51",
};
static const char * const sdio_groups[] = {
"gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
"gpio30", "gpio31", "gpio32",
};
static const char * const smart0_groups[] = {
"gpio0", "gpio1", "gpio2", "gpio5", "gpio44", "gpio45", "gpio46",
"gpio47",
};
static const char * const smart1_groups[] = {
"gpio8", "gpio9", "gpio16", "gpio17", "gpio58", "gpio59", "gpio60",
"gpio61",
};
static const char * const smart2_groups[] = {
"gpio40", "gpio41", "gpio48", "gpio49",
};
static const char * const smart3_groups[] = {
"gpio58", "gpio59", "gpio60", "gpio61",
};
static const char * const tm_groups[] = {
"gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58",
"gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
};
static const char * const wifi0_groups[] = {
"gpio37", "gpio40", "gpio41", "gpio42", "gpio50", "gpio51", "gpio52",
"gpio53", "gpio56", "gpio57", "gpio58", "gpio98",
};
static const char * const wifi1_groups[] = {
"gpio37", "gpio40", "gpio41", "gpio43", "gpio50", "gpio51", "gpio52",
"gpio53", "gpio56", "gpio57", "gpio58", "gpio98",
};
static const struct msm_function ipq4019_functions[] = {
FUNCTION(gpio),
FUNCTION(blsp_uart1),
FUNCTION(aud_pin),
FUNCTION(audio_pwm),
FUNCTION(blsp_i2c0),
FUNCTION(blsp_i2c1),
FUNCTION(blsp_uart0),
FUNCTION(blsp_spi1),
FUNCTION(blsp_spi0),
FUNCTION(blsp_spi1),
FUNCTION(blsp_uart0),
FUNCTION(blsp_uart1),
FUNCTION(chip_rst),
FUNCTION(gpio),
FUNCTION(i2s_rx),
FUNCTION(i2s_spdif_in),
FUNCTION(i2s_spdif_out),
FUNCTION(i2s_td),
FUNCTION(i2s_tx),
FUNCTION(jtag),
FUNCTION(led0),
FUNCTION(led1),
FUNCTION(led2),
FUNCTION(led3),
FUNCTION(led4),
FUNCTION(led5),
FUNCTION(led6),
FUNCTION(led7),
FUNCTION(led8),
FUNCTION(led9),
FUNCTION(led10),
FUNCTION(led11),
FUNCTION(mdc),
FUNCTION(mdio),
FUNCTION(pcie),
FUNCTION(pmu),
FUNCTION(prng_rosc),
FUNCTION(qpic),
FUNCTION(rgmii),
FUNCTION(rmii),
FUNCTION(sdio),
FUNCTION(smart0),
FUNCTION(smart1),
FUNCTION(smart2),
FUNCTION(smart3),
FUNCTION(tm),
FUNCTION(wifi0),
FUNCTION(wifi1),
};
static const struct msm_pingroup ipq4019_groups[] = {
PINGROUP(0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(4, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(5, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(6, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(7, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(8, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(9, blsp_uart1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(16, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(17, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(0, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(1, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(2, jtag, smart0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(3, jtag, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(4, jtag, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(5, jtag, smart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA),
PINGROUP(6, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(7, mdc, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(8, blsp_uart1, NA, NA, smart1, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(9, blsp_uart1, NA, NA, smart1, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(10, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(11, blsp_uart1, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(12, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(13, blsp_spi0, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(14, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA),
PINGROUP(15, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA),
PINGROUP(16, blsp_uart0, led0, smart1, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(17, blsp_uart0, led1, smart1, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(18, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(19, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(20, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(21, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(22, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(23, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(24, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(25, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(26, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(27, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(28, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(29, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(30, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(31, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(32, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(33, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(34, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(35, blsp_i2c1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(36, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(37, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(38, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(39, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(40, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(41, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(42, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(43, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(44, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(45, NA, blsp_spi1, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(46, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(47, NA, blsp_spi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(48, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(49, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(50, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(51, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(52, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(53, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(54, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(55, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(56, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(57, NA, blsp_spi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(58, NA, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(59, NA, blsp_i2c0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(60, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(61, NA, blsp_uart0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(62, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(63, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(65, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(67, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(68, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(69, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(20, blsp_i2c0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(21, blsp_i2c0, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(22, rgmii, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA),
PINGROUP(23, sdio, rgmii, i2s_rx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(24, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(25, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(26, sdio, rgmii, i2s_tx, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(27, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(28, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(29, sdio, rgmii, i2s_td, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(30, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(31, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(32, sdio, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(33, rgmii, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(34, blsp_i2c1, i2s_spdif_in, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA, NA),
PINGROUP(35, blsp_i2c1, i2s_spdif_out, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA, NA),
PINGROUP(36, rmii, led2, led0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA),
PINGROUP(37, rmii, wifi0, wifi1, led1, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(38, rmii, led2, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA),
PINGROUP(39, rmii, pcie, led3, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA),
PINGROUP(40, rmii, wifi0, wifi1, smart2, led4, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(41, rmii, wifi0, wifi1, smart2, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(42, rmii, wifi0, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA),
PINGROUP(43, rmii, wifi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA),
PINGROUP(44, rmii, blsp_spi1, smart0, led5, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(45, rmii, blsp_spi1, blsp_spi0, smart0, led6, NA, NA, NA, NA,
NA, NA, NA, NA, NA),
PINGROUP(46, rmii, blsp_spi1, smart0, led7, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(47, rmii, blsp_spi1, smart0, led8, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(48, rmii, aud_pin, smart2, led9, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(49, rmii, aud_pin, smart2, led10, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(50, rmii, aud_pin, wifi0, wifi1, led11, NA, NA, NA, NA, NA,
NA, NA, NA, NA),
PINGROUP(51, rmii, aud_pin, wifi0, wifi1, NA, NA, NA, NA, NA, NA, NA,
NA, NA, NA),
PINGROUP(52, qpic, mdc, pcie, i2s_tx, NA, NA, NA, tm, wifi0, wifi1, NA,
NA, NA, NA),
PINGROUP(53, qpic, mdio, i2s_tx, prng_rosc, NA, tm, wifi0, wifi1, NA,
NA, NA, NA, NA, NA),
PINGROUP(54, qpic, blsp_spi0, i2s_td, NA, pmu, NA, NA, NA, tm, NA, NA,
NA, NA, NA),
PINGROUP(55, qpic, blsp_spi0, i2s_td, NA, pmu, NA, NA, NA, tm, NA, NA,
NA, NA, NA),
PINGROUP(56, qpic, blsp_spi0, i2s_td, NA, NA, tm, wifi0, wifi1, NA, NA,
NA, NA, NA, NA),
PINGROUP(57, qpic, blsp_spi0, i2s_tx, NA, NA, tm, wifi0, wifi1, NA, NA,
NA, NA, NA, NA),
PINGROUP(58, qpic, led2, blsp_i2c0, smart3, smart1, i2s_rx, NA, NA, tm,
wifi0, wifi1, NA, NA, NA),
PINGROUP(59, qpic, blsp_i2c0, smart3, smart1, i2s_spdif_in, NA, NA, NA,
NA, NA, tm, NA, NA, NA),
PINGROUP(60, qpic, blsp_uart0, smart1, smart3, led0, i2s_tx, i2s_rx,
NA, NA, NA, NA, NA, tm, NA),
PINGROUP(61, qpic, blsp_uart0, smart1, smart3, led1, i2s_tx, i2s_rx,
NA, NA, NA, NA, NA, tm, NA),
PINGROUP(62, qpic, chip_rst, NA, NA, i2s_spdif_out, NA, NA, NA, NA, NA,
tm, NA, NA, NA),
PINGROUP(63, qpic, NA, NA, NA, i2s_td, i2s_rx, i2s_spdif_out,
i2s_spdif_in, NA, NA, NA, NA, tm, NA),
PINGROUP(64, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(65, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(66, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(67, qpic, audio_pwm, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA, NA),
PINGROUP(68, qpic, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(69, qpic, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(70, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(71, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(72, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
@ -433,7 +693,8 @@ static const struct msm_pingroup ipq4019_groups[] = {
PINGROUP(95, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(96, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(97, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(98, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
PINGROUP(98, wifi0, wifi1, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA,
NA),
PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
};
@ -445,6 +706,7 @@ static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
.groups = ipq4019_groups,
.ngroups = ARRAY_SIZE(ipq4019_groups),
.ngpios = 100,
.pull_no_keeper = true,
};
static int ipq4019_pinctrl_probe(struct platform_device *pdev)

15
drivers/pinctrl/qcom/pinctrl-msm.c
View file

@ -205,6 +205,7 @@ static int msm_config_reg(struct msm_pinctrl *pctrl,
#define MSM_NO_PULL 0
#define MSM_PULL_DOWN 1
#define MSM_KEEPER 2
#define MSM_PULL_UP_NO_KEEPER 2
#define MSM_PULL_UP 3
static unsigned msm_regval_to_drive(u32 val)
@ -243,9 +244,15 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev,
arg = arg == MSM_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_BUS_HOLD:
if (pctrl->soc->pull_no_keeper)
return -ENOTSUPP;
arg = arg == MSM_KEEPER;
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (pctrl->soc->pull_no_keeper)
arg = arg == MSM_PULL_UP_NO_KEEPER;
else
arg = arg == MSM_PULL_UP;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
@ -309,9 +316,15 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
arg = MSM_PULL_DOWN;
break;
case PIN_CONFIG_BIAS_BUS_HOLD:
if (pctrl->soc->pull_no_keeper)
return -ENOTSUPP;
arg = MSM_KEEPER;
break;
case PIN_CONFIG_BIAS_PULL_UP:
if (pctrl->soc->pull_no_keeper)
arg = MSM_PULL_UP_NO_KEEPER;
else
arg = MSM_PULL_UP;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
@ -521,7 +534,7 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
#define msm_gpio_dbg_show NULL
#endif
static struct gpio_chip msm_gpio_template = {
static const struct gpio_chip msm_gpio_template = {
.direction_input = msm_gpio_direction_input,
.direction_output = msm_gpio_direction_output,
.get_direction = msm_gpio_get_direction,

2
drivers/pinctrl/qcom/pinctrl-msm.h
View file

@ -106,6 +106,7 @@ struct msm_pingroup {
* @groups: An array describing all pin groups the pin SoC supports.
* @ngroups: The numbmer of entries in @groups.
* @ngpio: The number of pingroups the driver should expose as GPIOs.
* @pull_no_keeper: The SoC does not support keeper bias.
*/
struct msm_pinctrl_soc_data {
const struct pinctrl_pin_desc *pins;
@ -115,6 +116,7 @@ struct msm_pinctrl_soc_data {
const struct msm_pingroup *groups;
unsigned ngroups;
unsigned ngpios;
bool pull_no_keeper;
};
int msm_pinctrl_probe(struct platform_device *pdev,

287
drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
View file

@ -40,6 +40,8 @@
#define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
#define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
#define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
#define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10
#define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11
#define PMIC_MPP_REG_RT_STS 0x10
#define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
@ -48,8 +50,11 @@
#define PMIC_GPIO_REG_MODE_CTL 0x40
#define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
#define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
#define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44
#define PMIC_GPIO_REG_DIG_IN_CTL 0x43
#define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
#define PMIC_GPIO_REG_EN_CTL 0x46
#define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A
/* PMIC_GPIO_REG_MODE_CTL */
#define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
@ -58,6 +63,12 @@
#define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
#define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
#define PMIC_GPIO_MODE_DIGITAL_INPUT 0
#define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1
#define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2
#define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3
#define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3
/* PMIC_GPIO_REG_DIG_VIN_CTL */
#define PMIC_GPIO_REG_VIN_SHIFT 0
#define PMIC_GPIO_REG_VIN_MASK 0x7
@ -69,6 +80,16 @@
#define PMIC_GPIO_PULL_DOWN 4
#define PMIC_GPIO_PULL_DISABLE 5
/* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
#define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80
#define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7
#define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF
/* PMIC_GPIO_REG_DIG_IN_CTL */
#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80
#define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7
#define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf
/* PMIC_GPIO_REG_DIG_OUT_CTL */
#define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
#define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
@ -88,9 +109,29 @@
#define PMIC_GPIO_PHYSICAL_OFFSET 1
/* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
#define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3
/* Qualcomm specific pin configurations */
#define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
#define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
#define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3)
#define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4)
#define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5)
/* The index of each function in pmic_gpio_functions[] array */
enum pmic_gpio_func_index {
PMIC_GPIO_FUNC_INDEX_NORMAL,
PMIC_GPIO_FUNC_INDEX_PAIRED,
PMIC_GPIO_FUNC_INDEX_FUNC1,
PMIC_GPIO_FUNC_INDEX_FUNC2,
PMIC_GPIO_FUNC_INDEX_FUNC3,
PMIC_GPIO_FUNC_INDEX_FUNC4,
PMIC_GPIO_FUNC_INDEX_DTEST1,
PMIC_GPIO_FUNC_INDEX_DTEST2,
PMIC_GPIO_FUNC_INDEX_DTEST3,
PMIC_GPIO_FUNC_INDEX_DTEST4,
};
/**
* struct pmic_gpio_pad - keep current GPIO settings
@ -102,12 +143,16 @@
* open-drain or open-source mode.
* @output_enabled: Set to true if GPIO output logic is enabled.
* @input_enabled: Set to true if GPIO input buffer logic is enabled.
* @analog_pass: Set to true if GPIO is in analog-pass-through mode.
* @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
* @num_sources: Number of power-sources supported by this GPIO.
* @power_source: Current power-source used.
* @buffer_type: Push-pull, open-drain or open-source.
* @pullup: Constant current which flow trough GPIO output buffer.
* @strength: No, Low, Medium, High
* @function: See pmic_gpio_functions[]
* @atest: the ATEST selection for GPIO analog-pass-through mode
* @dtest_buffer: the DTEST buffer selection for digital input mode.
*/
struct pmic_gpio_pad {
u16 base;
@ -117,12 +162,16 @@ struct pmic_gpio_pad {
bool have_buffer;
bool output_enabled;
bool input_enabled;
bool analog_pass;
bool lv_mv_type;
unsigned int num_sources;
unsigned int power_source;
unsigned int buffer_type;
unsigned int pullup;
unsigned int strength;
unsigned int function;
unsigned int atest;
unsigned int dtest_buffer;
};
struct pmic_gpio_state {
@ -135,12 +184,18 @@ struct pmic_gpio_state {
static const struct pinconf_generic_params pmic_gpio_bindings[] = {
{"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
{"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
{"qcom,atest", PMIC_GPIO_CONF_ATEST, 0},
{"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0},
{"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0},
};
#ifdef CONFIG_DEBUG_FS
static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
};
#endif
@ -153,10 +208,16 @@ static const char *const pmic_gpio_groups[] = {
};
static const char *const pmic_gpio_functions[] = {
PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
[PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL,
[PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED,
[PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1,
[PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2,
[PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3,
[PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4,
[PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1,
[PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2,
[PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3,
[PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4,
};
static int pmic_gpio_read(struct pmic_gpio_state *state,
@ -244,18 +305,59 @@ static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
unsigned int val;
int ret;
if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
pr_err("function: %d is not defined\n", function);
return -EINVAL;
}
pad = pctldev->desc->pins[pin].drv_data;
/*
* Non-LV/MV subtypes only support 2 special functions,
* offsetting the dtestx function values by 2
*/
if (!pad->lv_mv_type) {
if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
pr_err("LV/MV subtype doesn't have func3/func4\n");
return -EINVAL;
}
if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
PMIC_GPIO_FUNC_INDEX_FUNC3);
}
pad->function = function;
val = 0;
if (pad->output_enabled) {
if (pad->input_enabled)
val = 2;
if (pad->analog_pass)
val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
else if (pad->output_enabled && pad->input_enabled)
val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
else if (pad->output_enabled)
val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
else
val = 1;
}
val = PMIC_GPIO_MODE_DIGITAL_INPUT;
if (pad->lv_mv_type) {
ret = pmic_gpio_write(state, pad,
PMIC_GPIO_REG_MODE_CTL, val);
if (ret < 0)
return ret;
val = pad->atest - 1;
ret = pmic_gpio_write(state, pad,
PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
if (ret < 0)
return ret;
val = pad->out_value
<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
val |= pad->function
& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
ret = pmic_gpio_write(state, pad,
PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
if (ret < 0)
return ret;
} else {
val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
@ -263,6 +365,7 @@ static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
if (ret < 0)
return ret;
}
val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
@ -322,6 +425,15 @@ static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
case PMIC_GPIO_CONF_STRENGTH:
arg = pad->strength;
break;
case PMIC_GPIO_CONF_ATEST:
arg = pad->atest;
break;
case PMIC_GPIO_CONF_ANALOG_PASS:
arg = pad->analog_pass;
break;
case PMIC_GPIO_CONF_DTEST_BUFFER:
arg = pad->dtest_buffer;
break;
default:
return -EINVAL;
}
@ -375,7 +487,7 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
pad->is_enabled = false;
break;
case PIN_CONFIG_POWER_SOURCE:
if (arg > pad->num_sources)
if (arg >= pad->num_sources)
return -EINVAL;
pad->power_source = arg;
break;
@ -396,6 +508,21 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
return -EINVAL;
pad->strength = arg;
break;
case PMIC_GPIO_CONF_ATEST:
if (!pad->lv_mv_type || arg > 4)
return -EINVAL;
pad->atest = arg;
break;
case PMIC_GPIO_CONF_ANALOG_PASS:
if (!pad->lv_mv_type)
return -EINVAL;
pad->analog_pass = true;
break;
case PMIC_GPIO_CONF_DTEST_BUFFER:
if (arg > 4)
return -EINVAL;
pad->dtest_buffer = arg;
break;
default:
return -EINVAL;
}
@ -420,19 +547,60 @@ static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
if (ret < 0)
return ret;
if (pad->dtest_buffer == 0) {
val = 0;
if (pad->output_enabled) {
if (pad->input_enabled)
val = 2;
else
val = 1;
} else {
if (pad->lv_mv_type) {
val = pad->dtest_buffer - 1;
val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
} else {
val = BIT(pad->dtest_buffer - 1);
}
}
ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
if (ret < 0)
return ret;
if (pad->analog_pass)
val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
else if (pad->output_enabled && pad->input_enabled)
val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
else if (pad->output_enabled)
val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
else
val = PMIC_GPIO_MODE_DIGITAL_INPUT;
if (pad->lv_mv_type) {
ret = pmic_gpio_write(state, pad,
PMIC_GPIO_REG_MODE_CTL, val);
if (ret < 0)
return ret;
val = pad->atest - 1;
ret = pmic_gpio_write(state, pad,
PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
if (ret < 0)
return ret;
val = pad->out_value
<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
val |= pad->function
& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
ret = pmic_gpio_write(state, pad,
PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
if (ret < 0)
return ret;
} else {
val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
return pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
if (ret < 0)
return ret;
}
return ret;
}
static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
@ -440,7 +608,7 @@ static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
{
struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
struct pmic_gpio_pad *pad;
int ret, val;
int ret, val, function;
static const char *const biases[] = {
"pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
@ -462,7 +630,6 @@ static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
seq_puts(s, " ---");
} else {
if (pad->input_enabled) {
ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
if (ret < 0)
@ -471,14 +638,29 @@ static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
pad->out_value = ret;
}
/*
* For the non-LV/MV subtypes only 2 special functions are
* available, offsetting the dtest function values by 2.
*/
function = pad->function;
if (!pad->lv_mv_type &&
pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
PMIC_GPIO_FUNC_INDEX_FUNC3;
seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
seq_printf(s, " %-7s", pmic_gpio_functions[pad->function]);
if (pad->analog_pass)
seq_puts(s, " analog-pass");
else
seq_printf(s, " %-4s",
pad->output_enabled ? "out" : "in");
seq_printf(s, " %-7s", pmic_gpio_functions[function]);
seq_printf(s, " vin-%d", pad->power_source);
seq_printf(s, " %-27s", biases[pad->pullup]);
seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
seq_printf(s, " %-7s", strengths[pad->strength]);
seq_printf(s, " atest-%d", pad->atest);
seq_printf(s, " dtest-%d", pad->dtest_buffer);
}
}
@ -618,11 +800,36 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state,
case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
pad->num_sources = 8;
break;
case PMIC_GPIO_SUBTYPE_GPIO_LV:
pad->num_sources = 1;
pad->have_buffer = true;
pad->lv_mv_type = true;
break;
case PMIC_GPIO_SUBTYPE_GPIO_MV:
pad->num_sources = 2;
pad->have_buffer = true;
pad->lv_mv_type = true;
break;
default:
dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
return -ENODEV;
}
if (pad->lv_mv_type) {
val = pmic_gpio_read(state, pad,
PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
if (val < 0)
return val;
pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
if (val < 0)
return val;
dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
} else {
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
if (val < 0)
return val;
@ -631,27 +838,33 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state,
dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
}
switch (dir) {
case 0:
case PMIC_GPIO_MODE_DIGITAL_INPUT:
pad->input_enabled = true;
pad->output_enabled = false;
break;
case 1:
case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
pad->input_enabled = false;
pad->output_enabled = true;
break;
case 2:
case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
pad->input_enabled = true;
pad->output_enabled = true;
break;
case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
if (!pad->lv_mv_type)
return -ENODEV;
pad->analog_pass = true;
break;
default:
dev_err(state->dev, "unknown GPIO direction\n");
return -ENODEV;
}
pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
if (val < 0)
return val;
@ -666,6 +879,18 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state,
pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
if (val < 0)
return val;
if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
pad->dtest_buffer =
(val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
else if (!pad->lv_mv_type)
pad->dtest_buffer = ffs(val);
else
pad->dtest_buffer = 0;
val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
if (val < 0)
return val;
@ -676,6 +901,14 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state,
pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
if (pad->lv_mv_type) {
val = pmic_gpio_read(state, pad,
PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
if (val < 0)
return val;
pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
}
/* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
pad->is_enabled = true;
return 0;

2
drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c
View file

@ -588,7 +588,7 @@ static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
#define pm8xxx_gpio_dbg_show NULL
#endif
static struct gpio_chip pm8xxx_gpio_template = {
static const struct gpio_chip pm8xxx_gpio_template = {
.direction_input = pm8xxx_gpio_direction_input,
.direction_output = pm8xxx_gpio_direction_output,
.get = pm8xxx_gpio_get,

2
drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c
View file

@ -643,7 +643,7 @@ static void pm8xxx_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip)
#define pm8xxx_mpp_dbg_show NULL
#endif
static struct gpio_chip pm8xxx_mpp_template = {
static const struct gpio_chip pm8xxx_mpp_template = {
.direction_input = pm8xxx_mpp_direction_input,
.direction_output = pm8xxx_mpp_direction_output,
.get = pm8xxx_mpp_get,

32
drivers/pinctrl/samsung/pinctrl-exynos.c
View file

@ -31,6 +31,8 @@
#include <linux/err.h>
#include <linux/soc/samsung/exynos-pmu.h>
#include <dt-bindings/pinctrl/samsung.h>
#include "pinctrl-samsung.h"
#include "pinctrl-exynos.h"
@ -149,15 +151,10 @@ static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type)
static int exynos_irq_request_resources(struct irq_data *irqd)
{
struct irq_chip *chip = irq_data_get_irq_chip(irqd);
struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
const struct samsung_pin_bank_type *bank_type = bank->type;
unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
unsigned long flags;
unsigned int mask;
unsigned int con;
unsigned long reg_con, flags;
unsigned int shift, mask, con;
int ret;
ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq);
@ -174,10 +171,10 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
spin_lock_irqsave(&bank->slock, flags);
con = readl(bank->eint_base + reg_con);
con = readl(bank->pctl_base + reg_con);
con &= ~(mask << shift);
con |= EXYNOS_EINT_FUNC << shift;
writel(con, bank->eint_base + reg_con);
con |= EXYNOS_PIN_FUNC_EINT << shift;
writel(con, bank->pctl_base + reg_con);
spin_unlock_irqrestore(&bank->slock, flags);
@ -186,15 +183,10 @@ static int exynos_irq_request_resources(struct irq_data *irqd)
static void exynos_irq_release_resources(struct irq_data *irqd)
{
struct irq_chip *chip = irq_data_get_irq_chip(irqd);
struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip);
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
const struct samsung_pin_bank_type *bank_type = bank->type;
unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq;
unsigned long reg_con = our_chip->eint_con + bank->eint_offset;
unsigned long flags;
unsigned int mask;
unsigned int con;
unsigned long reg_con, flags;
unsigned int shift, mask, con;
reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC];
@ -202,10 +194,10 @@ static void exynos_irq_release_resources(struct irq_data *irqd)
spin_lock_irqsave(&bank->slock, flags);
con = readl(bank->eint_base + reg_con);
con = readl(bank->pctl_base + reg_con);
con &= ~(mask << shift);
con |= FUNC_INPUT << shift;
writel(con, bank->eint_base + reg_con);
con |= EXYNOS_PIN_FUNC_INPUT << shift;
writel(con, bank->pctl_base + reg_con);
spin_unlock_irqrestore(&bank->slock, flags);

1
drivers/pinctrl/samsung/pinctrl-exynos.h
View file

@ -32,7 +32,6 @@
#define EXYNOS7_WKUP_EMASK_OFFSET 0x900
#define EXYNOS7_WKUP_EPEND_OFFSET 0xA00
#define EXYNOS_SVC_OFFSET 0xB08
#define EXYNOS_EINT_FUNC 0xF
/* helpers to access interrupt service register */
#define EXYNOS_SVC_GROUP_SHIFT 3

37
drivers/pinctrl/samsung/pinctrl-s3c24xx.c
View file

@ -151,7 +151,7 @@ static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d,
u32 val;
/* Make sure that pin is configured as interrupt */
reg = bank->pctl_base + bank->pctl_offset;
reg = d->virt_base + bank->pctl_offset;
shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
@ -184,7 +184,7 @@ static int s3c24xx_eint_type(struct irq_data *data, unsigned int type)
s3c24xx_eint_set_handler(data, type);
/* Set up interrupt trigger */
reg = bank->eint_base + EINT_REG(index);
reg = d->virt_base + EINT_REG(index);
shift = EINT_OFFS(index);
val = readl(reg);
@ -259,29 +259,32 @@ static void s3c2410_demux_eint0_3(struct irq_desc *desc)
static void s3c2412_eint0_3_ack(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned long bitval = 1UL << data->hwirq;
writel(bitval, bank->eint_base + EINTPEND_REG);
writel(bitval, d->virt_base + EINTPEND_REG);
}
static void s3c2412_eint0_3_mask(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned long mask;
mask = readl(bank->eint_base + EINTMASK_REG);
mask = readl(d->virt_base + EINTMASK_REG);
mask |= (1UL << data->hwirq);
writel(mask, bank->eint_base + EINTMASK_REG);
writel(mask, d->virt_base + EINTMASK_REG);
}
static void s3c2412_eint0_3_unmask(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned long mask;
mask = readl(bank->eint_base + EINTMASK_REG);
mask = readl(d->virt_base + EINTMASK_REG);
mask &= ~(1UL << data->hwirq);
writel(mask, bank->eint_base + EINTMASK_REG);
writel(mask, d->virt_base + EINTMASK_REG);
}
static struct irq_chip s3c2412_eint0_3_chip = {
@ -316,31 +319,34 @@ static void s3c2412_demux_eint0_3(struct irq_desc *desc)
static void s3c24xx_eint_ack(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned char index = bank->eint_offset + data->hwirq;
writel(1UL << index, bank->eint_base + EINTPEND_REG);
writel(1UL << index, d->virt_base + EINTPEND_REG);
}
static void s3c24xx_eint_mask(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned char index = bank->eint_offset + data->hwirq;
unsigned long mask;
mask = readl(bank->eint_base + EINTMASK_REG);
mask = readl(d->virt_base + EINTMASK_REG);
mask |= (1UL << index);
writel(mask, bank->eint_base + EINTMASK_REG);
writel(mask, d->virt_base + EINTMASK_REG);
}
static void s3c24xx_eint_unmask(struct irq_data *data)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned char index = bank->eint_offset + data->hwirq;
unsigned long mask;
mask = readl(bank->eint_base + EINTMASK_REG);
mask = readl(d->virt_base + EINTMASK_REG);
mask &= ~(1UL << index);
writel(mask, bank->eint_base + EINTMASK_REG);
writel(mask, d->virt_base + EINTMASK_REG);
}
static struct irq_chip s3c24xx_eint_chip = {
@ -356,14 +362,13 @@ static inline void s3c24xx_demux_eint(struct irq_desc *desc,
{
struct s3c24xx_eint_data *data = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_data *irqd = irq_desc_get_irq_data(desc);
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
struct samsung_pinctrl_drv_data *d = data->drvdata;
unsigned int pend, mask;
chained_irq_enter(chip, desc);
pend = readl(bank->eint_base + EINTPEND_REG);
mask = readl(bank->eint_base + EINTMASK_REG);
pend = readl(d->virt_base + EINTPEND_REG);
mask = readl(d->virt_base + EINTMASK_REG);
pend &= ~mask;
pend &= range;

40
drivers/pinctrl/samsung/pinctrl-s3c64xx.c
View file

@ -280,7 +280,7 @@ static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d,
u32 val;
/* Make sure that pin is configured as interrupt */
reg = bank->pctl_base + bank->pctl_offset;
reg = d->virt_base + bank->pctl_offset;
shift = pin;
if (bank_type->fld_width[PINCFG_TYPE_FUNC] * shift >= 32) {
/* 4-bit bank type with 2 con regs */
@ -308,8 +308,9 @@ static void s3c64xx_irq_set_function(struct samsung_pinctrl_drv_data *d,
static inline void s3c64xx_gpio_irq_set_mask(struct irq_data *irqd, bool mask)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
void __iomem *reg = bank->eint_base + EINTMASK_REG(bank->eint_offset);
void __iomem *reg = d->virt_base + EINTMASK_REG(bank->eint_offset);
u32 val;
val = readl(reg);
@ -333,8 +334,9 @@ static void s3c64xx_gpio_irq_mask(struct irq_data *irqd)
static void s3c64xx_gpio_irq_ack(struct irq_data *irqd)
{
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
struct samsung_pinctrl_drv_data *d = bank->drvdata;
unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
void __iomem *reg = bank->eint_base + EINTPEND_REG(bank->eint_offset);
void __iomem *reg = d->virt_base + EINTPEND_REG(bank->eint_offset);
writel(1 << index, reg);
}
@ -357,7 +359,7 @@ static int s3c64xx_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
s3c64xx_irq_set_handler(irqd, type);
/* Set up interrupt trigger */
reg = bank->eint_base + EINTCON_REG(bank->eint_offset);
reg = d->virt_base + EINTCON_REG(bank->eint_offset);
shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq;
shift = 4 * (shift / 4); /* 4 EINTs per trigger selector */
@ -409,8 +411,7 @@ static void s3c64xx_eint_gpio_irq(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct s3c64xx_eint_gpio_data *data = irq_desc_get_handler_data(desc);
struct irq_data *irqd = irq_desc_get_irq_data(desc);
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
chained_irq_enter(chip, desc);
@ -420,7 +421,7 @@ static void s3c64xx_eint_gpio_irq(struct irq_desc *desc)
unsigned int pin;
unsigned int virq;
svc = readl(bank->eint_base + SERVICE_REG);
svc = readl(drvdata->virt_base + SERVICE_REG);
group = SVC_GROUP(svc);
pin = svc & SVC_NUM_MASK;
@ -515,15 +516,15 @@ static inline void s3c64xx_eint0_irq_set_mask(struct irq_data *irqd, bool mask)
{
struct s3c64xx_eint0_domain_data *ddata =
irq_data_get_irq_chip_data(irqd);
struct samsung_pin_bank *bank = ddata->bank;
struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
u32 val;
val = readl(bank->eint_base + EINT0MASK_REG);
val = readl(d->virt_base + EINT0MASK_REG);
if (mask)
val |= 1 << ddata->eints[irqd->hwirq];
else
val &= ~(1 << ddata->eints[irqd->hwirq]);
writel(val, bank->eint_base + EINT0MASK_REG);
writel(val, d->virt_base + EINT0MASK_REG);
}
static void s3c64xx_eint0_irq_unmask(struct irq_data *irqd)
@ -540,10 +541,10 @@ static void s3c64xx_eint0_irq_ack(struct irq_data *irqd)
{
struct s3c64xx_eint0_domain_data *ddata =
irq_data_get_irq_chip_data(irqd);
struct samsung_pin_bank *bank = ddata->bank;
struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
writel(1 << ddata->eints[irqd->hwirq],
bank->eint_base + EINT0PEND_REG);
d->virt_base + EINT0PEND_REG);
}
static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)
@ -551,7 +552,7 @@ static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)
struct s3c64xx_eint0_domain_data *ddata =
irq_data_get_irq_chip_data(irqd);
struct samsung_pin_bank *bank = ddata->bank;
struct samsung_pinctrl_drv_data *d = ddata->bank->drvdata;
struct samsung_pinctrl_drv_data *d = bank->drvdata;
void __iomem *reg;
int trigger;
u8 shift;
@ -566,7 +567,7 @@ static int s3c64xx_eint0_irq_set_type(struct irq_data *irqd, unsigned int type)
s3c64xx_irq_set_handler(irqd, type);
/* Set up interrupt trigger */
reg = bank->eint_base + EINT0CON0_REG;
reg = d->virt_base + EINT0CON0_REG;
shift = ddata->eints[irqd->hwirq];
if (shift >= EINT_MAX_PER_REG) {
reg += 4;
@ -598,19 +599,14 @@ static struct irq_chip s3c64xx_eint0_irq_chip = {
static inline void s3c64xx_irq_demux_eint(struct irq_desc *desc, u32 range)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_data *irqd = irq_desc_get_irq_data(desc);
struct s3c64xx_eint0_domain_data *ddata =
irq_data_get_irq_chip_data(irqd);
struct samsung_pin_bank *bank = ddata->bank;
struct s3c64xx_eint0_data *data = irq_desc_get_handler_data(desc);
struct samsung_pinctrl_drv_data *drvdata = data->drvdata;
unsigned int pend, mask;
chained_irq_enter(chip, desc);
pend = readl(bank->eint_base + EINT0PEND_REG);
mask = readl(bank->eint_base + EINT0MASK_REG);
pend = readl(drvdata->virt_base + EINT0PEND_REG);
mask = readl(drvdata->virt_base + EINT0MASK_REG);
pend = pend & range & ~mask;
pend &= range;

18
drivers/pinctrl/samsung/pinctrl-samsung.c
View file

@ -30,6 +30,8 @@
#include <linux/of_device.h>
#include <linux/spinlock.h>
#include <dt-bindings/pinctrl/samsung.h>
#include "../core.h"
#include "pinctrl-samsung.h"
@ -586,7 +588,7 @@ static int samsung_gpio_set_direction(struct gpio_chip *gc,
data = readl(reg);
data &= ~(mask << shift);
if (!input)
data |= FUNC_OUTPUT << shift;
data |= EXYNOS_PIN_FUNC_OUTPUT << shift;
writel(data, reg);
return 0;
@ -679,7 +681,7 @@ static int samsung_pinctrl_create_function(struct device *dev,
npins = of_property_count_strings(func_np, "samsung,pins");
if (npins < 1) {
dev_err(dev, "invalid pin list in %s node", func_np->name);
dev_err(dev, "invalid pin list in %pOFn node", func_np);
return -EINVAL;
}
@ -696,8 +698,8 @@ static int samsung_pinctrl_create_function(struct device *dev,
i, &gname);
if (ret) {
dev_err(dev,
"failed to read pin name %d from %s node\n",
i, func_np->name);
"failed to read pin name %d from %pOFn node\n",
i, func_np);
return ret;
}
@ -958,7 +960,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
struct samsung_pin_bank *bank;
struct resource *res;
void __iomem *virt_base[SAMSUNG_PINCTRL_NUM_RESOURCES];
int i;
unsigned int i;
id = of_alias_get_id(node, "pinctrl");
if (id < 0) {
@ -1013,6 +1015,12 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_drv_data *d,
bank->eint_base = virt_base[0];
bank->pctl_base = virt_base[bdata->pctl_res_idx];
}
/*
* Legacy platforms should provide only one resource with IO memory.
* Store it as virt_base because legacy driver needs to access it
* through samsung_pinctrl_drv_data.
*/
d->virt_base = virt_base[0];
for_each_child_of_node(node, np) {
if (!of_find_property(np, "gpio-controller", NULL))

15
drivers/pinctrl/samsung/pinctrl-samsung.h
View file

@ -25,10 +25,6 @@
#include <linux/gpio.h>
/* pinmux function number for pin as gpio output line */
#define FUNC_INPUT 0x0
#define FUNC_OUTPUT 0x1
/**
* enum pincfg_type - possible pin configuration types supported.
* @PINCFG_TYPE_FUNC: Function configuration.
@ -234,8 +230,8 @@ struct samsung_retention_data {
*/
struct samsung_pin_ctrl {
const struct samsung_pin_bank_data *pin_banks;
u32 nr_banks;
int nr_ext_resources;
unsigned int nr_banks;
unsigned int nr_ext_resources;
const struct samsung_retention_data *retention_data;
int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
@ -247,6 +243,10 @@ struct samsung_pin_ctrl {
/**
* struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
* @node: global list node
* @virt_base: register base address of the controller; this will be equal
* to each bank samsung_pin_bank->pctl_base and used on legacy
* platforms (like S3C24XX or S3C64XX) which has to access the base
* through samsung_pinctrl_drv_data, not samsung_pin_bank).
* @dev: device instance representing the controller.
* @irq: interrpt number used by the controller to notify gpio interrupts.
* @ctrl: pin controller instance managed by the driver.
@ -262,6 +262,7 @@ struct samsung_pin_ctrl {
*/
struct samsung_pinctrl_drv_data {
struct list_head node;
void __iomem *virt_base;
struct device *dev;
int irq;
@ -274,7 +275,7 @@ struct samsung_pinctrl_drv_data {
unsigned int nr_functions;
struct samsung_pin_bank *pin_banks;
u32 nr_banks;
unsigned int nr_banks;
unsigned int pin_base;
unsigned int nr_pins;

5
drivers/pinctrl/sh-pfc/Kconfig
View file

@ -89,6 +89,11 @@ config PINCTRL_PFC_R8A7796
depends on ARCH_R8A7796
select PINCTRL_SH_PFC
config PINCTRL_PFC_R8A77995
def_bool y
depends on ARCH_R8A77995
select PINCTRL_SH_PFC
config PINCTRL_PFC_SH7203
def_bool y
depends on CPU_SUBTYPE_SH7203

1
drivers/pinctrl/sh-pfc/Makefile
View file

@ -15,6 +15,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795-es1.o
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o

6
drivers/pinctrl/sh-pfc/core.c
View file

@ -551,6 +551,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
.data = &r8a7796_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77995
{
.compatible = "renesas,pfc-r8a77995",
.data = &r8a77995_pinmux_info,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_SH73A0
{
.compatible = "renesas,pfc-sh73a0",

15
drivers/pinctrl/sh-pfc/pfc-r8a7791.c
View file

@ -2589,6 +2589,17 @@ static const unsigned int mmc_data8_mux[] = {
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
};
static const unsigned int mmc_data8_b_pins[] = {
/* D[0:7] */
RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
};
static const unsigned int mmc_data8_b_mux[] = {
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
};
static const unsigned int mmc_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
@ -4420,7 +4431,7 @@ static const unsigned int vin2_clk_mux[] = {
};
static const struct {
struct sh_pfc_pin_group common[341];
struct sh_pfc_pin_group common[342];
struct sh_pfc_pin_group r8a779x[9];
} pinmux_groups = {
.common = {
@ -4523,6 +4534,7 @@ static const struct {
SH_PFC_PIN_GROUP(mmc_data1),
SH_PFC_PIN_GROUP(mmc_data4),
SH_PFC_PIN_GROUP(mmc_data8),
SH_PFC_PIN_GROUP(mmc_data8_b),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
@ -4955,6 +4967,7 @@ static const char * const mmc_groups[] = {
"mmc_data1",
"mmc_data4",
"mmc_data8",
"mmc_data8_b",
"mmc_ctrl",
};

1082
drivers/pinctrl/sh-pfc/pfc-r8a7795.c
View file

File diff suppressed because it is too large Load diff

146
drivers/pinctrl/sh-pfc/pfc-r8a7796.c
View file

@ -67,7 +67,7 @@
#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
#define GPSR1_23 F_(RD_N, IP4_27_24)
#define GPSR1_22 F_(BS_N, IP4_23_20)
#define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
#define GPSR1_21 F_(CS1_N, IP4_19_16)
#define GPSR1_20 F_(CS0_N, IP4_15_12)
#define GPSR1_19 F_(A19, IP4_11_8)
#define GPSR1_18 F_(A18, IP4_7_4)
@ -221,8 +221,8 @@
#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -253,7 +253,7 @@
#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -278,7 +278,6 @@
#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -291,24 +290,24 @@
#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_7_4 FM(SD2_CMD) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_27_24 FM(SD2_DS) F_(0, 0) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_31_28 FM(SD3_CLK) F_(0, 0) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_3_0 FM(SD3_CMD) F_(0, 0) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_7_4 FM(SD3_DS) F_(0, 0) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
@ -319,14 +318,14 @@
#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) FM(FSO_TOE_A) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
@ -366,9 +365,9 @@
#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) FM(FSO_CFE_0_A) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0)
#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) FM(FSO_CFE_1_A) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0)
#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
#define PINMUX_GPSR \
\
@ -419,7 +418,7 @@ FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_3
FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
@ -463,7 +462,6 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
#define MOD_SEL0_15 FM(SEL_FSO_0) FM(SEL_FSO_1)
#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
@ -472,7 +470,6 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
#define MOD_SEL0_2 FM(SEL_5LINE_0) FM(SEL_5LINE_1)
/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
@ -488,7 +485,7 @@ FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
@ -529,7 +526,7 @@ MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
MOD_SEL2_17 \
MOD_SEL0_16 MOD_SEL1_16 \
MOD_SEL0_15 MOD_SEL1_15_14 \
MOD_SEL1_15_14 \
MOD_SEL0_14_13 \
MOD_SEL1_13 \
MOD_SEL0_12 MOD_SEL1_12 \
@ -541,7 +538,7 @@ MOD_SEL0_7_6 \
MOD_SEL0_5 MOD_SEL1_5 \
MOD_SEL0_4_3 MOD_SEL1_4 \
MOD_SEL1_3 \
MOD_SEL0_2 MOD_SEL1_2 \
MOD_SEL1_2 \
MOD_SEL1_1 \
MOD_SEL1_0 MOD_SEL2_0
@ -645,7 +642,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS1_E, SEL_MSIOF3_4),
PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
/* IPSR1 */
PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
@ -837,7 +834,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
@ -990,8 +987,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
@ -1173,7 +1168,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
PINMUX_IPSR_MSEL(IP12_11_8, FSO_TOE_A, SEL_FSO_0),
PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
@ -1205,7 +1199,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF1_1),
PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
@ -1218,14 +1212,14 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
PINMUX_IPSR_MSEL(IP13_3_0, FSO_CFE_0_B, SEL_FSO_1),
PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
PINMUX_IPSR_MSEL(IP13_7_4, FSO_CFE_1_B, SEL_FSO_1),
PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
@ -1393,7 +1387,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU_0),
PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
@ -1410,14 +1404,14 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
PINMUX_IPSR_GPSR(IP16_31_28, SCK5_A),
PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
/* IPSR17 */
PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF1_0),
PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
@ -1461,10 +1455,10 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1),
PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
@ -1476,7 +1470,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
PINMUX_IPSR_MSEL(IP17_31_28, FSO_TOE_B, SEL_FSO_1),
PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
/* IPSR18 */
@ -1487,7 +1481,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
PINMUX_IPSR_MSEL(IP18_3_0, FSO_CFE_0_A, SEL_FSO_0),
PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
@ -1498,7 +1491,6 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
PINMUX_IPSR_MSEL(IP18_7_4, FSO_CFE_1_A, SEL_FSO_0),
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
@ -3082,7 +3074,7 @@ static const unsigned int msiof3_ss2_e_pins[] = {
RCAR_GP_PIN(2, 0),
};
static const unsigned int msiof3_ss2_e_mux[] = {
MSIOF3_SS1_E_MARK,
MSIOF3_SS2_E_MARK,
};
static const unsigned int msiof3_txd_e_pins[] = {
/* TXD */
@ -3796,6 +3788,32 @@ static const unsigned int ssi9_ctrl_b_mux[] = {
SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
};
/* - USB0 ------------------------------------------------------------------- */
static const unsigned int usb0_pins[] = {
/* PWEN, OVC */
RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
};
static const unsigned int usb0_mux[] = {
USB0_PWEN_MARK, USB0_OVC_MARK,
};
/* - USB1 ------------------------------------------------------------------- */
static const unsigned int usb1_pins[] = {
/* PWEN, OVC */
RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
};
static const unsigned int usb1_mux[] = {
USB1_PWEN_MARK, USB1_OVC_MARK,
};
/* - USB30 ------------------------------------------------------------------ */
static const unsigned int usb30_pins[] = {
/* PWEN, OVC */
RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
};
static const unsigned int usb30_mux[] = {
USB30_PWEN_MARK, USB30_OVC_MARK,
};
static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(audio_clk_a_a),
SH_PFC_PIN_GROUP(audio_clk_a_b),
@ -4096,6 +4114,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(ssi9_data_b),
SH_PFC_PIN_GROUP(ssi9_ctrl_a),
SH_PFC_PIN_GROUP(ssi9_ctrl_b),
SH_PFC_PIN_GROUP(usb0),
SH_PFC_PIN_GROUP(usb1),
SH_PFC_PIN_GROUP(usb30),
};
static const char * const audio_clk_groups[] = {
@ -4526,6 +4547,18 @@ static const char * const ssi_groups[] = {
"ssi9_ctrl_b",
};
static const char * const usb0_groups[] = {
"usb0",
};
static const char * const usb1_groups[] = {
"usb1",
};
static const char * const usb30_groups[] = {
"usb30",
};
static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(audio_clk),
SH_PFC_FUNCTION(avb),
@ -4570,6 +4603,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(sdhi2),
SH_PFC_FUNCTION(sdhi3),
SH_PFC_FUNCTION(ssi),
SH_PFC_FUNCTION(usb0),
SH_PFC_FUNCTION(usb1),
SH_PFC_FUNCTION(usb30),
};
static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@ -4927,7 +4963,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
IP7_27_24
IP7_23_20
IP7_19_16
IP7_15_12
/* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP7_11_8
IP7_7_4
IP7_3_0 }
@ -5060,7 +5096,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
MOD_SEL0_19
MOD_SEL0_18_17
MOD_SEL0_16
MOD_SEL0_15
0, 0, /* RESERVED 15 */
MOD_SEL0_14_13
MOD_SEL0_12
MOD_SEL0_11
@ -5502,7 +5538,7 @@ static const struct sh_pfc_bias_info bias_info[] = {
{ RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
{ RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
{ RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
{ RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
{ RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */
{ RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
{ RCAR_GP_PIN(1, 28), PU2, 0 }, /* CLKOUT */

1812
drivers/pinctrl/sh-pfc/pfc-r8a77995.c Normal file
View file

File diff suppressed because it is too large Load diff

11
drivers/pinctrl/sh-pfc/pinctrl.c
View file

@ -290,7 +290,7 @@ static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
if (*num_maps)
return 0;
dev_err(dev, "no mapping found in node %s\n", np->full_name);
dev_err(dev, "no mapping found in node %pOF\n", np);
ret = -EINVAL;
done:
@ -742,13 +742,16 @@ static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
const unsigned int *pins;
unsigned int num_pins;
unsigned int i;
unsigned int i, ret;
pins = pmx->pfc->info->groups[group].pins;
num_pins = pmx->pfc->info->groups[group].nr_pins;
for (i = 0; i < num_pins; ++i)
sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs);
for (i = 0; i < num_pins; ++i) {
ret = sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs);
if (ret)
return ret;
}
return 0;
}

23
drivers/pinctrl/sh-pfc/sh_pfc.h
View file

@ -271,6 +271,7 @@ extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info;
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
extern const struct sh_pfc_soc_info sh7203_pinmux_info;
extern const struct sh_pfc_soc_info sh7264_pinmux_info;
extern const struct sh_pfc_soc_info sh7269_pinmux_info;
@ -389,9 +390,13 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
#define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
PORT_GP_CFG_9(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
#define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
PORT_GP_CFG_10(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
@ -422,11 +427,19 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
PORT_GP_CFG_18(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
#define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
#define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
PORT_GP_CFG_20(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
PORT_GP_CFG_21(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)

13
drivers/pinctrl/sirf/pinctrl-atlas7.c
View file

@ -549,7 +549,7 @@ static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
PINCTRL_PIN(163, "jtag_trstn"),
};
struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
static struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
/* The Configuration of IOC_RTC Pads */
PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0),
PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0),
@ -1002,7 +1002,7 @@ static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 103, 104,
105, 106, 107, 102, 97, 98, };
/* definition of pin group table */
struct atlas7_pin_group altas7_pin_groups[] = {
static struct atlas7_pin_group altas7_pin_groups[] = {
GROUP("gnss_gpio_grp", gnss_gpio_pins),
GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins),
GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins),
@ -4764,7 +4764,7 @@ static struct atlas7_pmx_func atlas7_pmx_functions[] = {
&vi_vip1_high8bit_grp_mux),
};
struct atlas7_pinctrl_data atlas7_ioc_data = {
static struct atlas7_pinctrl_data atlas7_ioc_data = {
.pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads,
.pads_cnt = ARRAY_SIZE(atlas7_ioc_pads),
.grps = (struct atlas7_pin_group *)altas7_pin_groups,
@ -5261,7 +5261,7 @@ static int atlas7_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
return 0;
}
static struct pinmux_ops atlas7_pinmux_ops = {
static const struct pinmux_ops atlas7_pinmux_ops = {
.get_functions_count = atlas7_pmx_get_funcs_count,
.get_function_name = atlas7_pmx_get_func_name,
.get_function_groups = atlas7_pmx_get_func_groups,
@ -6078,12 +6078,15 @@ static int atlas7_gpio_probe(struct platform_device *pdev)
bank = &a7gc->banks[idx];
/* Set ctrl registers' base of this bank */
bank->base = ATLAS7_GPIO_BASE(a7gc, idx);
bank->gpio_offset = idx * NGPIO_OF_BANK;
/* Get interrupt number from DTS */
ret = of_irq_get(np, idx);
if (ret == -EPROBE_DEFER) {
if (ret <= 0) {
dev_err(&pdev->dev,
"Unable to find IRQ number. ret=%d\n", ret);
if (!ret)
ret = -ENXIO;
goto failed;
}
bank->irq = ret;

10
drivers/pinctrl/sirf/pinctrl-sirf.c
View file

@ -133,7 +133,7 @@ static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
kfree(map);
}
static struct pinctrl_ops sirfsoc_pctrl_ops = {
static const struct pinctrl_ops sirfsoc_pctrl_ops = {
.get_groups_count = sirfsoc_get_groups_count,
.get_group_name = sirfsoc_get_group_name,
.get_group_pins = sirfsoc_get_group_pins,
@ -229,7 +229,7 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
return 0;
}
static struct pinmux_ops sirfsoc_pinmux_ops = {
static const struct pinmux_ops sirfsoc_pinmux_ops = {
.set_mux = sirfsoc_pinmux_set_mux,
.get_functions_count = sirfsoc_pinmux_get_funcs_count,
.get_function_name = sirfsoc_pinmux_get_func_name,
@ -810,7 +810,7 @@ static int sirfsoc_gpio_probe(struct device_node *np)
sgpio->chip.gc.set = sirfsoc_gpio_set_value;
sgpio->chip.gc.base = 0;
sgpio->chip.gc.ngpio = SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS;
sgpio->chip.gc.label = kstrdup(np->full_name, GFP_KERNEL);
sgpio->chip.gc.label = kasprintf(GFP_KERNEL, "%pOF", np);
sgpio->chip.gc.of_node = np;
sgpio->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
sgpio->chip.gc.of_gpio_n_cells = 2;
@ -819,8 +819,8 @@ static int sirfsoc_gpio_probe(struct device_node *np)
err = gpiochip_add_data(&sgpio->chip.gc, sgpio);
if (err) {
dev_err(&pdev->dev, "%s: error in probe function with status %d\n",
np->full_name, err);
dev_err(&pdev->dev, "%pOF: error in probe function with status %d\n",
np, err);
goto out;
}

17
drivers/pinctrl/sprd/Kconfig Normal file
View file

@ -0,0 +1,17 @@
#
# Spreadtrum pin control drivers
#
config PINCTRL_SPRD
bool "Spreadtrum pinctrl driver"
select PINMUX
select PINCONF
select GENERIC_PINCONF
select GENERIC_PINMUX_FUNCTIONS
help
Say Y here to enable Spreadtrum pinctrl driver
config PINCTRL_SPRD_SC9860
bool "Spreadtrum SC9860 pinctrl driver"
help
Say Y here to enable Spreadtrum SC9860 pinctrl driver

2
drivers/pinctrl/sprd/Makefile Normal file
View file

@ -0,0 +1,2 @@
obj-$(CONFIG_PINCTRL_SPRD) += pinctrl-sprd.o
obj-$(CONFIG_PINCTRL_SPRD_SC9860) += pinctrl-sprd-sc9860.o

972
drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c Normal file
View file

@ -0,0 +1,972 @@
/*
* Spreadtrum pin controller driver
* Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
#include <linux/module.h>
#include <linux/platform_device.h>
#include "pinctrl-sprd.h"
enum sprd_sc9860_pins {
/* pin global control register 0 */
SC9860_VIO28_0_IRTE = SPRD_PIN_INFO(0, GLOBAL_CTRL_PIN, 11, 1, 0),
SC9860_VIO_SD2_IRTE = SPRD_PIN_INFO(1, GLOBAL_CTRL_PIN, 10, 1, 0),
SC9860_VIO_SD0_IRTE = SPRD_PIN_INFO(2, GLOBAL_CTRL_PIN, 9, 1, 0),
SC9860_VIO_SIM2_IRTE = SPRD_PIN_INFO(3, GLOBAL_CTRL_PIN, 8, 1, 0),
SC9860_VIO_SIM1_IRTE = SPRD_PIN_INFO(4, GLOBAL_CTRL_PIN, 7, 1, 0),
SC9860_VIO_SIM0_IRTE = SPRD_PIN_INFO(5, GLOBAL_CTRL_PIN, 6, 1, 0),
SC9860_VIO28_0_MS = SPRD_PIN_INFO(6, GLOBAL_CTRL_PIN, 5, 1, 0),
SC9860_VIO_SD2_MS = SPRD_PIN_INFO(7, GLOBAL_CTRL_PIN, 4, 1, 0),
SC9860_VIO_SD0_MS = SPRD_PIN_INFO(8, GLOBAL_CTRL_PIN, 3, 1, 0),
SC9860_VIO_SIM2_MS = SPRD_PIN_INFO(9, GLOBAL_CTRL_PIN, 2, 1, 0),
SC9860_VIO_SIM1_MS = SPRD_PIN_INFO(10, GLOBAL_CTRL_PIN, 1, 1, 0),
SC9860_VIO_SIM0_MS = SPRD_PIN_INFO(11, GLOBAL_CTRL_PIN, 0, 1, 0),
/* pin global control register 2 */
SC9860_SPSPI_PIN_IN_SEL = SPRD_PIN_INFO(12, GLOBAL_CTRL_PIN, 31, 1, 2),
SC9860_UART1_USB30_PHY_SEL = SPRD_PIN_INFO(13, GLOBAL_CTRL_PIN, 30, 1, 2),
SC9860_USB30_PHY_DM_OE = SPRD_PIN_INFO(14, GLOBAL_CTRL_PIN, 29, 1, 2),
SC9860_USB30_PHY_DP_OE = SPRD_PIN_INFO(15, GLOBAL_CTRL_PIN, 28, 1, 2),
SC9860_UART5_SYS_SEL = SPRD_PIN_INFO(16, GLOBAL_CTRL_PIN, 25, 3, 2),
SC9860_ORP_URXD_PIN_IN_SEL = SPRD_PIN_INFO(17, GLOBAL_CTRL_PIN, 24, 1, 2),
SC9860_SIM2_SYS_SEL = SPRD_PIN_INFO(18, GLOBAL_CTRL_PIN, 23, 1, 2),
SC9860_SIM1_SYS_SEL = SPRD_PIN_INFO(19, GLOBAL_CTRL_PIN, 22, 1, 2),
SC9860_SIM0_SYS_SEL = SPRD_PIN_INFO(20, GLOBAL_CTRL_PIN, 21, 1, 2),
SC9860_CLK26MHZ_BUF_OUT_SEL = SPRD_PIN_INFO(21, GLOBAL_CTRL_PIN, 20, 1, 2),
SC9860_UART4_SYS_SEL = SPRD_PIN_INFO(22, GLOBAL_CTRL_PIN, 16, 3, 2),
SC9860_UART3_SYS_SEL = SPRD_PIN_INFO(23, GLOBAL_CTRL_PIN, 13, 3, 2),
SC9860_UART2_SYS_SEL = SPRD_PIN_INFO(24, GLOBAL_CTRL_PIN, 10, 3, 2),
SC9860_UART1_SYS_SEL = SPRD_PIN_INFO(25, GLOBAL_CTRL_PIN, 7, 3, 2),
SC9860_UART0_SYS_SEL = SPRD_PIN_INFO(26, GLOBAL_CTRL_PIN, 4, 3, 2),
SC9860_UART24_LOOP_SEL = SPRD_PIN_INFO(27, GLOBAL_CTRL_PIN, 3, 1, 2),
SC9860_UART23_LOOP_SEL = SPRD_PIN_INFO(28, GLOBAL_CTRL_PIN, 2, 1, 2),
SC9860_UART14_LOOP_SEL = SPRD_PIN_INFO(29, GLOBAL_CTRL_PIN, 1, 1, 2),
SC9860_UART13_LOOP_SEL = SPRD_PIN_INFO(30, GLOBAL_CTRL_PIN, 0, 1, 2),
/* pin global control register 3 */
SC9860_IIS3_SYS_SEL = SPRD_PIN_INFO(31, GLOBAL_CTRL_PIN, 18, 4, 3),
SC9860_IIS2_SYS_SEL = SPRD_PIN_INFO(32, GLOBAL_CTRL_PIN, 14, 4, 3),
SC9860_IIS1_SYS_SEL = SPRD_PIN_INFO(33, GLOBAL_CTRL_PIN, 10, 4, 3),
SC9860_IIS0_SYS_SEL = SPRD_PIN_INFO(34, GLOBAL_CTRL_PIN, 6, 4, 3),
SC9860_IIS23_LOOP_SEL = SPRD_PIN_INFO(35, GLOBAL_CTRL_PIN, 5, 1, 3),
SC9860_IIS13_LOOP_SEL = SPRD_PIN_INFO(36, GLOBAL_CTRL_PIN, 4, 1, 3),
SC9860_IIS12_LOOP_SEL = SPRD_PIN_INFO(37, GLOBAL_CTRL_PIN, 3, 1, 3),
SC9860_IIS03_LOOP_SEL = SPRD_PIN_INFO(38, GLOBAL_CTRL_PIN, 2, 1, 3),
SC9860_IIS02_LOOP_SEL = SPRD_PIN_INFO(39, GLOBAL_CTRL_PIN, 1, 1, 3),
SC9860_IIS01_LOOP_SEL = SPRD_PIN_INFO(40, GLOBAL_CTRL_PIN, 0, 1, 3),
/* pin global control register 4 */
SC9860_IIS6_SYS_SEL = SPRD_PIN_INFO(41, GLOBAL_CTRL_PIN, 27, 4, 4),
SC9860_IIS5_SYS_SEL = SPRD_PIN_INFO(42, GLOBAL_CTRL_PIN, 23, 4, 4),
SC9860_IIS4_SYS_SEL = SPRD_PIN_INFO(43, GLOBAL_CTRL_PIN, 19, 4, 4),
SC9860_I2C_INF6_SYS_SEL = SPRD_PIN_INFO(44, GLOBAL_CTRL_PIN, 8, 2, 4),
SC9860_I2C_INF4_SYS_SEL = SPRD_PIN_INFO(45, GLOBAL_CTRL_PIN, 6, 2, 4),
SC9860_I2C_INF2_SYS_SEL = SPRD_PIN_INFO(46, GLOBAL_CTRL_PIN, 4, 2, 4),
SC9860_I2C_INF1_SYS_SEL = SPRD_PIN_INFO(47, GLOBAL_CTRL_PIN, 2, 2, 4),
SC9860_I2C_INF0_SYS_SEL = SPRD_PIN_INFO(48, GLOBAL_CTRL_PIN, 0, 2, 4),
/* pin global control register 5 */
SC9860_GPIO_INF7_SYS_SEL = SPRD_PIN_INFO(49, GLOBAL_CTRL_PIN, 27, 1, 5),
SC9860_GPIO_INF6_SYS_SEL = SPRD_PIN_INFO(50, GLOBAL_CTRL_PIN, 26, 1, 5),
SC9860_GPIO_INF5_SYS_SEL = SPRD_PIN_INFO(51, GLOBAL_CTRL_PIN, 25, 1, 5),
SC9860_GPIO_INF4_SYS_SEL = SPRD_PIN_INFO(52, GLOBAL_CTRL_PIN, 24, 1, 5),
SC9860_GPIO_INF3_SYS_SEL = SPRD_PIN_INFO(53, GLOBAL_CTRL_PIN, 23, 1, 5),
SC9860_GPIO_INF2_SYS_SEL = SPRD_PIN_INFO(54, GLOBAL_CTRL_PIN, 22, 1, 5),
SC9860_GPIO_INF1_SYS_SEL = SPRD_PIN_INFO(55, GLOBAL_CTRL_PIN, 21, 1, 5),
SC9860_GPIO_INF0_SYS_SEL = SPRD_PIN_INFO(56, GLOBAL_CTRL_PIN, 20, 1, 5),
SC9860_WDRST_OUT_SEL = SPRD_PIN_INFO(57, GLOBAL_CTRL_PIN, 16, 3, 5),
SC9860_ADI_SYNC_PIN_OUT_SEL = SPRD_PIN_INFO(58, GLOBAL_CTRL_PIN, 14, 1, 5),
SC9860_CMRST_SEL = SPRD_PIN_INFO(59, GLOBAL_CTRL_PIN, 13, 1, 5),
SC9860_CMPD_SEL = SPRD_PIN_INFO(60, GLOBAL_CTRL_PIN, 12, 1, 5),
SC9860_TEST_DBG_MODE11 = SPRD_PIN_INFO(61, GLOBAL_CTRL_PIN, 11, 1, 5),
SC9860_TEST_DBG_MODE10 = SPRD_PIN_INFO(62, GLOBAL_CTRL_PIN, 10, 1, 5),
SC9860_TEST_DBG_MODE9 = SPRD_PIN_INFO(63, GLOBAL_CTRL_PIN, 9, 1, 5),
SC9860_TEST_DBG_MODE8 = SPRD_PIN_INFO(64, GLOBAL_CTRL_PIN, 8, 1, 5),
SC9860_TEST_DBG_MODE7 = SPRD_PIN_INFO(65, GLOBAL_CTRL_PIN, 7, 1, 5),
SC9860_TEST_DBG_MODE6 = SPRD_PIN_INFO(66, GLOBAL_CTRL_PIN, 6, 1, 5),
SC9860_TEST_DBG_MODE5 = SPRD_PIN_INFO(67, GLOBAL_CTRL_PIN, 5, 1, 5),
SC9860_TEST_DBG_MODE4 = SPRD_PIN_INFO(68, GLOBAL_CTRL_PIN, 4, 1, 5),
SC9860_TEST_DBG_MODE3 = SPRD_PIN_INFO(69, GLOBAL_CTRL_PIN, 3, 1, 5),
SC9860_TEST_DBG_MODE2 = SPRD_PIN_INFO(70, GLOBAL_CTRL_PIN, 2, 1, 5),
SC9860_TEST_DBG_MODE1 = SPRD_PIN_INFO(71, GLOBAL_CTRL_PIN, 1, 1, 5),
SC9860_TEST_DBG_MODE0 = SPRD_PIN_INFO(72, GLOBAL_CTRL_PIN, 0, 1, 5),
/* pin global control register 6 */
SC9860_SP_EIC_DPAD3_SEL = SPRD_PIN_INFO(73, GLOBAL_CTRL_PIN, 24, 8, 6),
SC9860_SP_EIC_DPAD2_SEL = SPRD_PIN_INFO(74, GLOBAL_CTRL_PIN, 16, 8, 6),
SC9860_SP_EIC_DPAD1_SEL = SPRD_PIN_INFO(75, GLOBAL_CTRL_PIN, 8, 8, 6),
SC9860_SP_EIC_DPAD0_SEL = SPRD_PIN_INFO(76, GLOBAL_CTRL_PIN, 0, 8, 6),
/* pin global control register 7 */
SC9860_SP_EIC_DPAD7_SEL = SPRD_PIN_INFO(77, GLOBAL_CTRL_PIN, 24, 8, 7),
SC9860_SP_EIC_DPAD6_SEL = SPRD_PIN_INFO(78, GLOBAL_CTRL_PIN, 16, 8, 7),
SC9860_SP_EIC_DPAD5_SEL = SPRD_PIN_INFO(79, GLOBAL_CTRL_PIN, 8, 8, 7),
SC9860_SP_EIC_DPAD4_SEL = SPRD_PIN_INFO(80, GLOBAL_CTRL_PIN, 0, 8, 7),
/* common pin registers definitions */
SC9860_RFCTL20 = SPRD_PIN_INFO(81, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL21 = SPRD_PIN_INFO(83, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL30 = SPRD_PIN_INFO(85, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL31 = SPRD_PIN_INFO(87, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL32 = SPRD_PIN_INFO(89, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL33 = SPRD_PIN_INFO(91, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL34 = SPRD_PIN_INFO(93, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL35 = SPRD_PIN_INFO(95, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL36 = SPRD_PIN_INFO(97, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL37 = SPRD_PIN_INFO(99, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL22 = SPRD_PIN_INFO(101, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL23 = SPRD_PIN_INFO(103, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL24 = SPRD_PIN_INFO(105, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL25 = SPRD_PIN_INFO(107, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL26 = SPRD_PIN_INFO(109, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL27 = SPRD_PIN_INFO(111, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL28 = SPRD_PIN_INFO(113, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL29 = SPRD_PIN_INFO(115, COMMON_PIN, 0, 0, 0),
SC9860_SCL2 = SPRD_PIN_INFO(117, COMMON_PIN, 0, 0, 0),
SC9860_SDA2 = SPRD_PIN_INFO(119, COMMON_PIN, 0, 0, 0),
SC9860_MTCK_ARM = SPRD_PIN_INFO(121, COMMON_PIN, 0, 0, 0),
SC9860_MTMS_ARM = SPRD_PIN_INFO(123, COMMON_PIN, 0, 0, 0),
SC9860_XTL_EN0 = SPRD_PIN_INFO(125, COMMON_PIN, 0, 0, 0),
SC9860_PTEST = SPRD_PIN_INFO(127, COMMON_PIN, 0, 0, 0),
SC9860_AUD_DAD1 = SPRD_PIN_INFO(129, COMMON_PIN, 0, 0, 0),
SC9860_AUD_ADD0 = SPRD_PIN_INFO(131, COMMON_PIN, 0, 0, 0),
SC9860_AUD_ADSYNC = SPRD_PIN_INFO(133, COMMON_PIN, 0, 0, 0),
SC9860_AUD_SCLK = SPRD_PIN_INFO(135, COMMON_PIN, 0, 0, 0),
SC9860_CHIP_SLEEP = SPRD_PIN_INFO(137, COMMON_PIN, 0, 0, 0),
SC9860_CLK_32K = SPRD_PIN_INFO(139, COMMON_PIN, 0, 0, 0),
SC9860_DCDC_ARM_EN = SPRD_PIN_INFO(141, COMMON_PIN, 0, 0, 0),
SC9860_EXT_RST_B = SPRD_PIN_INFO(143, COMMON_PIN, 0, 0, 0),
SC9860_ADI_D = SPRD_PIN_INFO(145, COMMON_PIN, 0, 0, 0),
SC9860_ADI_SCLK = SPRD_PIN_INFO(147, COMMON_PIN, 0, 0, 0),
SC9860_XTL_EN1 = SPRD_PIN_INFO(149, COMMON_PIN, 0, 0, 0),
SC9860_ANA_INT = SPRD_PIN_INFO(151, COMMON_PIN, 0, 0, 0),
SC9860_AUD_DAD0 = SPRD_PIN_INFO(153, COMMON_PIN, 0, 0, 0),
SC9860_AUD_DASYNC = SPRD_PIN_INFO(155, COMMON_PIN, 0, 0, 0),
SC9860_LCM_RSTN = SPRD_PIN_INFO(157, COMMON_PIN, 0, 0, 0),
SC9860_DSI_TE = SPRD_PIN_INFO(159, COMMON_PIN, 0, 0, 0),
SC9860_PWMA = SPRD_PIN_INFO(161, COMMON_PIN, 0, 0, 0),
SC9860_EXTINT0 = SPRD_PIN_INFO(163, COMMON_PIN, 0, 0, 0),
SC9860_EXTINT1 = SPRD_PIN_INFO(165, COMMON_PIN, 0, 0, 0),
SC9860_SDA1 = SPRD_PIN_INFO(167, COMMON_PIN, 0, 0, 0),
SC9860_SCL1 = SPRD_PIN_INFO(169, COMMON_PIN, 0, 0, 0),
SC9860_SIMCLK2 = SPRD_PIN_INFO(171, COMMON_PIN, 0, 0, 0),
SC9860_SIMDA2 = SPRD_PIN_INFO(173, COMMON_PIN, 0, 0, 0),
SC9860_SIMRST2 = SPRD_PIN_INFO(175, COMMON_PIN, 0, 0, 0),
SC9860_SIMCLK1 = SPRD_PIN_INFO(177, COMMON_PIN, 0, 0, 0),
SC9860_SIMDA1 = SPRD_PIN_INFO(179, COMMON_PIN, 0, 0, 0),
SC9860_SIMRST1 = SPRD_PIN_INFO(181, COMMON_PIN, 0, 0, 0),
SC9860_SIMCLK0 = SPRD_PIN_INFO(183, COMMON_PIN, 0, 0, 0),
SC9860_SIMDA0 = SPRD_PIN_INFO(185, COMMON_PIN, 0, 0, 0),
SC9860_SIMRST0 = SPRD_PIN_INFO(187, COMMON_PIN, 0, 0, 0),
SC9860_SD2_CMD = SPRD_PIN_INFO(189, COMMON_PIN, 0, 0, 0),
SC9860_SD2_D0 = SPRD_PIN_INFO(191, COMMON_PIN, 0, 0, 0),
SC9860_SD2_D1 = SPRD_PIN_INFO(193, COMMON_PIN, 0, 0, 0),
SC9860_SD2_CLK = SPRD_PIN_INFO(195, COMMON_PIN, 0, 0, 0),
SC9860_SD2_D2 = SPRD_PIN_INFO(197, COMMON_PIN, 0, 0, 0),
SC9860_SD2_D3 = SPRD_PIN_INFO(199, COMMON_PIN, 0, 0, 0),
SC9860_SD0_D3 = SPRD_PIN_INFO(201, COMMON_PIN, 0, 0, 0),
SC9860_SD0_D2 = SPRD_PIN_INFO(203, COMMON_PIN, 0, 0, 0),
SC9860_SD0_CMD = SPRD_PIN_INFO(205, COMMON_PIN, 0, 0, 0),
SC9860_SD0_D0 = SPRD_PIN_INFO(207, COMMON_PIN, 0, 0, 0),
SC9860_SD0_D1 = SPRD_PIN_INFO(209, COMMON_PIN, 0, 0, 0),
SC9860_SD0_CLK = SPRD_PIN_INFO(211, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_CMD_reserved = SPRD_PIN_INFO(213, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_CMD = SPRD_PIN_INFO(215, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D6 = SPRD_PIN_INFO(217, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D7 = SPRD_PIN_INFO(219, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_CLK = SPRD_PIN_INFO(221, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D5 = SPRD_PIN_INFO(223, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D4 = SPRD_PIN_INFO(225, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_DS = SPRD_PIN_INFO(227, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D3_reserved = SPRD_PIN_INFO(229, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D3 = SPRD_PIN_INFO(231, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_RST = SPRD_PIN_INFO(233, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D1 = SPRD_PIN_INFO(235, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D2 = SPRD_PIN_INFO(237, COMMON_PIN, 0, 0, 0),
SC9860_EMMC_D0 = SPRD_PIN_INFO(239, COMMON_PIN, 0, 0, 0),
SC9860_IIS0DI = SPRD_PIN_INFO(241, COMMON_PIN, 0, 0, 0),
SC9860_IIS0DO = SPRD_PIN_INFO(243, COMMON_PIN, 0, 0, 0),
SC9860_IIS0CLK = SPRD_PIN_INFO(245, COMMON_PIN, 0, 0, 0),
SC9860_IIS0LRCK = SPRD_PIN_INFO(247, COMMON_PIN, 0, 0, 0),
SC9860_SD1_CLK = SPRD_PIN_INFO(249, COMMON_PIN, 0, 0, 0),
SC9860_SD1_CMD = SPRD_PIN_INFO(251, COMMON_PIN, 0, 0, 0),
SC9860_SD1_D0 = SPRD_PIN_INFO(253, COMMON_PIN, 0, 0, 0),
SC9860_SD1_D1 = SPRD_PIN_INFO(255, COMMON_PIN, 0, 0, 0),
SC9860_SD1_D2 = SPRD_PIN_INFO(257, COMMON_PIN, 0, 0, 0),
SC9860_SD1_D3 = SPRD_PIN_INFO(259, COMMON_PIN, 0, 0, 0),
SC9860_CLK_AUX0 = SPRD_PIN_INFO(261, COMMON_PIN, 0, 0, 0),
SC9860_WIFI_COEXIST = SPRD_PIN_INFO(263, COMMON_PIN, 0, 0, 0),
SC9860_BEIDOU_COEXIST = SPRD_PIN_INFO(265, COMMON_PIN, 0, 0, 0),
SC9860_U3TXD = SPRD_PIN_INFO(267, COMMON_PIN, 0, 0, 0),
SC9860_U3RXD = SPRD_PIN_INFO(269, COMMON_PIN, 0, 0, 0),
SC9860_U3CTS = SPRD_PIN_INFO(271, COMMON_PIN, 0, 0, 0),
SC9860_U3RTS = SPRD_PIN_INFO(273, COMMON_PIN, 0, 0, 0),
SC9860_U0TXD = SPRD_PIN_INFO(275, COMMON_PIN, 0, 0, 0),
SC9860_U0RXD = SPRD_PIN_INFO(277, COMMON_PIN, 0, 0, 0),
SC9860_U0CTS = SPRD_PIN_INFO(279, COMMON_PIN, 0, 0, 0),
SC9860_U0RTS = SPRD_PIN_INFO(281, COMMON_PIN, 0, 0, 0),
SC9860_IIS1DI = SPRD_PIN_INFO(283, COMMON_PIN, 0, 0, 0),
SC9860_IIS1DO = SPRD_PIN_INFO(285, COMMON_PIN, 0, 0, 0),
SC9860_IIS1CLK = SPRD_PIN_INFO(287, COMMON_PIN, 0, 0, 0),
SC9860_IIS1LRCK = SPRD_PIN_INFO(289, COMMON_PIN, 0, 0, 0),
SC9860_SPI0_CSN = SPRD_PIN_INFO(291, COMMON_PIN, 0, 0, 0),
SC9860_SPI0_DO = SPRD_PIN_INFO(293, COMMON_PIN, 0, 0, 0),
SC9860_SPI0_DI = SPRD_PIN_INFO(295, COMMON_PIN, 0, 0, 0),
SC9860_SPI0_CLK = SPRD_PIN_INFO(297, COMMON_PIN, 0, 0, 0),
SC9860_U2TXD = SPRD_PIN_INFO(299, COMMON_PIN, 0, 0, 0),
SC9860_U2RXD = SPRD_PIN_INFO(301, COMMON_PIN, 0, 0, 0),
SC9860_U4TXD = SPRD_PIN_INFO(303, COMMON_PIN, 0, 0, 0),
SC9860_U4RXD = SPRD_PIN_INFO(305, COMMON_PIN, 0, 0, 0),
SC9860_CMMCLK1 = SPRD_PIN_INFO(307, COMMON_PIN, 0, 0, 0),
SC9860_CMRST1 = SPRD_PIN_INFO(309, COMMON_PIN, 0, 0, 0),
SC9860_CMMCLK0 = SPRD_PIN_INFO(311, COMMON_PIN, 0, 0, 0),
SC9860_CMRST0 = SPRD_PIN_INFO(313, COMMON_PIN, 0, 0, 0),
SC9860_CMPD0 = SPRD_PIN_INFO(315, COMMON_PIN, 0, 0, 0),
SC9860_CMPD1 = SPRD_PIN_INFO(317, COMMON_PIN, 0, 0, 0),
SC9860_SCL0 = SPRD_PIN_INFO(319, COMMON_PIN, 0, 0, 0),
SC9860_SDA0 = SPRD_PIN_INFO(321, COMMON_PIN, 0, 0, 0),
SC9860_SDA6 = SPRD_PIN_INFO(323, COMMON_PIN, 0, 0, 0),
SC9860_SCL6 = SPRD_PIN_INFO(325, COMMON_PIN, 0, 0, 0),
SC9860_U1TXD = SPRD_PIN_INFO(327, COMMON_PIN, 0, 0, 0),
SC9860_U1RXD = SPRD_PIN_INFO(329, COMMON_PIN, 0, 0, 0),
SC9860_KEYOUT0 = SPRD_PIN_INFO(331, COMMON_PIN, 0, 0, 0),
SC9860_KEYOUT1 = SPRD_PIN_INFO(333, COMMON_PIN, 0, 0, 0),
SC9860_KEYOUT2 = SPRD_PIN_INFO(335, COMMON_PIN, 0, 0, 0),
SC9860_KEYIN0 = SPRD_PIN_INFO(337, COMMON_PIN, 0, 0, 0),
SC9860_KEYIN1 = SPRD_PIN_INFO(339, COMMON_PIN, 0, 0, 0),
SC9860_KEYIN2 = SPRD_PIN_INFO(341, COMMON_PIN, 0, 0, 0),
SC9860_IIS3DI = SPRD_PIN_INFO(343, COMMON_PIN, 0, 0, 0),
SC9860_IIS3DO = SPRD_PIN_INFO(345, COMMON_PIN, 0, 0, 0),
SC9860_IIS3CLK = SPRD_PIN_INFO(347, COMMON_PIN, 0, 0, 0),
SC9860_IIS3LRCK = SPRD_PIN_INFO(349, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL0 = SPRD_PIN_INFO(351, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL1 = SPRD_PIN_INFO(353, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL10 = SPRD_PIN_INFO(355, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL11 = SPRD_PIN_INFO(357, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL12 = SPRD_PIN_INFO(359, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL13 = SPRD_PIN_INFO(361, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL14 = SPRD_PIN_INFO(363, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL15 = SPRD_PIN_INFO(365, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL16 = SPRD_PIN_INFO(367, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL17 = SPRD_PIN_INFO(369, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL18 = SPRD_PIN_INFO(371, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL19 = SPRD_PIN_INFO(373, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL2 = SPRD_PIN_INFO(375, COMMON_PIN, 0, 0, 0),
SC9860_EXTINT5 = SPRD_PIN_INFO(377, COMMON_PIN, 0, 0, 0),
SC9860_EXTINT6 = SPRD_PIN_INFO(379, COMMON_PIN, 0, 0, 0),
SC9860_EXTINT7 = SPRD_PIN_INFO(381, COMMON_PIN, 0, 0, 0),
SC9860_GPIO30 = SPRD_PIN_INFO(383, COMMON_PIN, 0, 0, 0),
SC9860_GPIO31 = SPRD_PIN_INFO(385, COMMON_PIN, 0, 0, 0),
SC9860_GPIO32 = SPRD_PIN_INFO(387, COMMON_PIN, 0, 0, 0),
SC9860_GPIO33 = SPRD_PIN_INFO(389, COMMON_PIN, 0, 0, 0),
SC9860_GPIO34 = SPRD_PIN_INFO(391, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL3 = SPRD_PIN_INFO(393, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL4 = SPRD_PIN_INFO(395, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL5 = SPRD_PIN_INFO(397, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL6 = SPRD_PIN_INFO(399, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL7 = SPRD_PIN_INFO(401, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL8 = SPRD_PIN_INFO(403, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL9 = SPRD_PIN_INFO(405, COMMON_PIN, 0, 0, 0),
SC9860_RFFE0_SCK0 = SPRD_PIN_INFO(407, COMMON_PIN, 0, 0, 0),
SC9860_GPIO38 = SPRD_PIN_INFO(409, COMMON_PIN, 0, 0, 0),
SC9860_RFFE0_SDA0 = SPRD_PIN_INFO(411, COMMON_PIN, 0, 0, 0),
SC9860_GPIO39 = SPRD_PIN_INFO(413, COMMON_PIN, 0, 0, 0),
SC9860_RFFE1_SCK0 = SPRD_PIN_INFO(415, COMMON_PIN, 0, 0, 0),
SC9860_GPIO181 = SPRD_PIN_INFO(417, COMMON_PIN, 0, 0, 0),
SC9860_RFFE1_SDA0 = SPRD_PIN_INFO(419, COMMON_PIN, 0, 0, 0),
SC9860_GPIO182 = SPRD_PIN_INFO(421, COMMON_PIN, 0, 0, 0),
SC9860_RF_LVDS0_ADC_ON = SPRD_PIN_INFO(423, COMMON_PIN, 0, 0, 0),
SC9860_RF_LVDS0_DAC_ON = SPRD_PIN_INFO(425, COMMON_PIN, 0, 0, 0),
SC9860_RFSCK0 = SPRD_PIN_INFO(427, COMMON_PIN, 0, 0, 0),
SC9860_RFSDA0 = SPRD_PIN_INFO(429, COMMON_PIN, 0, 0, 0),
SC9860_RFSEN0 = SPRD_PIN_INFO(431, COMMON_PIN, 0, 0, 0),
SC9860_RF_LVDS1_ADC_ON = SPRD_PIN_INFO(433, COMMON_PIN, 0, 0, 0),
SC9860_RF_LVDS1_DAC_ON = SPRD_PIN_INFO(435, COMMON_PIN, 0, 0, 0),
SC9860_RFSCK1 = SPRD_PIN_INFO(437, COMMON_PIN, 0, 0, 0),
SC9860_RFSDA1 = SPRD_PIN_INFO(439, COMMON_PIN, 0, 0, 0),
SC9860_RFSEN1 = SPRD_PIN_INFO(441, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL38 = SPRD_PIN_INFO(443, COMMON_PIN, 0, 0, 0),
SC9860_RFCTL39 = SPRD_PIN_INFO(445, COMMON_PIN, 0, 0, 0),
/* MSIC pin registers definitions */
SC9860_RFCTL20_MISC = SPRD_PIN_INFO(82, MISC_PIN, 0, 0, 0),
SC9860_RFCTL21_MISC = SPRD_PIN_INFO(84, MISC_PIN, 0, 0, 0),
SC9860_RFCTL30_MISC = SPRD_PIN_INFO(86, MISC_PIN, 0, 0, 0),
SC9860_RFCTL31_MISC = SPRD_PIN_INFO(88, MISC_PIN, 0, 0, 0),
SC9860_RFCTL32_MISC = SPRD_PIN_INFO(90, MISC_PIN, 0, 0, 0),
SC9860_RFCTL33_MISC = SPRD_PIN_INFO(92, MISC_PIN, 0, 0, 0),
SC9860_RFCTL34_MISC = SPRD_PIN_INFO(94, MISC_PIN, 0, 0, 0),
SC9860_RFCTL35_MISC = SPRD_PIN_INFO(96, MISC_PIN, 0, 0, 0),
SC9860_RFCTL36_MISC = SPRD_PIN_INFO(98, MISC_PIN, 0, 0, 0),
SC9860_RFCTL37_MISC = SPRD_PIN_INFO(100, MISC_PIN, 0, 0, 0),
SC9860_RFCTL22_MISC = SPRD_PIN_INFO(102, MISC_PIN, 0, 0, 0),
SC9860_RFCTL23_MISC = SPRD_PIN_INFO(104, MISC_PIN, 0, 0, 0),
SC9860_RFCTL24_MISC = SPRD_PIN_INFO(106, MISC_PIN, 0, 0, 0),
SC9860_RFCTL25_MISC = SPRD_PIN_INFO(108, MISC_PIN, 0, 0, 0),
SC9860_RFCTL26_MISC = SPRD_PIN_INFO(110, MISC_PIN, 0, 0, 0),
SC9860_RFCTL27_MISC = SPRD_PIN_INFO(112, MISC_PIN, 0, 0, 0),
SC9860_RFCTL28_MISC = SPRD_PIN_INFO(114, MISC_PIN, 0, 0, 0),
SC9860_RFCTL29_MISC = SPRD_PIN_INFO(116, MISC_PIN, 0, 0, 0),
SC9860_SCL2_MISC = SPRD_PIN_INFO(118, MISC_PIN, 0, 0, 0),
SC9860_SDA2_MISC = SPRD_PIN_INFO(120, MISC_PIN, 0, 0, 0),
SC9860_MTCK_ARM_MISC = SPRD_PIN_INFO(122, MISC_PIN, 0, 0, 0),
SC9860_MTMS_ARM_MISC = SPRD_PIN_INFO(124, MISC_PIN, 0, 0, 0),
SC9860_XTL_EN0_MISC = SPRD_PIN_INFO(126, MISC_PIN, 0, 0, 0),
SC9860_PTEST_MISC = SPRD_PIN_INFO(128, MISC_PIN, 0, 0, 0),
SC9860_AUD_DAD1_MISC = SPRD_PIN_INFO(130, MISC_PIN, 0, 0, 0),
SC9860_AUD_ADD0_MISC = SPRD_PIN_INFO(132, MISC_PIN, 0, 0, 0),
SC9860_AUD_ADSYNC_MISC = SPRD_PIN_INFO(134, MISC_PIN, 0, 0, 0),
SC9860_AUD_SCLK_MISC = SPRD_PIN_INFO(136, MISC_PIN, 0, 0, 0),
SC9860_CHIP_SLEEP_MISC = SPRD_PIN_INFO(138, MISC_PIN, 0, 0, 0),
SC9860_CLK_32K_MISC = SPRD_PIN_INFO(140, MISC_PIN, 0, 0, 0),
SC9860_DCDC_ARM_EN_MISC = SPRD_PIN_INFO(142, MISC_PIN, 0, 0, 0),
SC9860_EXT_RST_B_MISC = SPRD_PIN_INFO(144, MISC_PIN, 0, 0, 0),
SC9860_ADI_D_MISC = SPRD_PIN_INFO(146, MISC_PIN, 0, 0, 0),
SC9860_ADI_SCLK_MISC = SPRD_PIN_INFO(148, MISC_PIN, 0, 0, 0),
SC9860_XTL_EN1_MISC = SPRD_PIN_INFO(150, MISC_PIN, 0, 0, 0),
SC9860_ANA_INT_MISC = SPRD_PIN_INFO(152, MISC_PIN, 0, 0, 0),
SC9860_AUD_DAD0_MISC = SPRD_PIN_INFO(154, MISC_PIN, 0, 0, 0),
SC9860_AUD_DASYNC_MISC = SPRD_PIN_INFO(156, MISC_PIN, 0, 0, 0),
SC9860_LCM_RSTN_MISC = SPRD_PIN_INFO(158, MISC_PIN, 0, 0, 0),
SC9860_DSI_TE_MISC = SPRD_PIN_INFO(160, MISC_PIN, 0, 0, 0),
SC9860_PWMA_MISC = SPRD_PIN_INFO(162, MISC_PIN, 0, 0, 0),
SC9860_EXTINT0_MISC = SPRD_PIN_INFO(164, MISC_PIN, 0, 0, 0),
SC9860_EXTINT1_MISC = SPRD_PIN_INFO(166, MISC_PIN, 0, 0, 0),
SC9860_SDA1_MISC = SPRD_PIN_INFO(168, MISC_PIN, 0, 0, 0),
SC9860_SCL1_MISC = SPRD_PIN_INFO(170, MISC_PIN, 0, 0, 0),
SC9860_SIMCLK2_MISC = SPRD_PIN_INFO(172, MISC_PIN, 0, 0, 0),
SC9860_SIMDA2_MISC = SPRD_PIN_INFO(174, MISC_PIN, 0, 0, 0),
SC9860_SIMRST2_MISC = SPRD_PIN_INFO(176, MISC_PIN, 0, 0, 0),
SC9860_SIMCLK1_MISC = SPRD_PIN_INFO(178, MISC_PIN, 0, 0, 0),
SC9860_SIMDA1_MISC = SPRD_PIN_INFO(180, MISC_PIN, 0, 0, 0),
SC9860_SIMRST1_MISC = SPRD_PIN_INFO(182, MISC_PIN, 0, 0, 0),
SC9860_SIMCLK0_MISC = SPRD_PIN_INFO(184, MISC_PIN, 0, 0, 0),
SC9860_SIMDA0_MISC = SPRD_PIN_INFO(186, MISC_PIN, 0, 0, 0),
SC9860_SIMRST0_MISC = SPRD_PIN_INFO(188, MISC_PIN, 0, 0, 0),
SC9860_SD2_CMD_MISC = SPRD_PIN_INFO(190, MISC_PIN, 0, 0, 0),
SC9860_SD2_D0_MISC = SPRD_PIN_INFO(192, MISC_PIN, 0, 0, 0),
SC9860_SD2_D1_MISC = SPRD_PIN_INFO(194, MISC_PIN, 0, 0, 0),
SC9860_SD2_CLK_MISC = SPRD_PIN_INFO(196, MISC_PIN, 0, 0, 0),
SC9860_SD2_D2_MISC = SPRD_PIN_INFO(198, MISC_PIN, 0, 0, 0),
SC9860_SD2_D3_MISC = SPRD_PIN_INFO(200, MISC_PIN, 0, 0, 0),
SC9860_SD0_D3_MISC = SPRD_PIN_INFO(202, MISC_PIN, 0, 0, 0),
SC9860_SD0_D2_MISC = SPRD_PIN_INFO(204, MISC_PIN, 0, 0, 0),
SC9860_SD0_CMD_MISC = SPRD_PIN_INFO(206, MISC_PIN, 0, 0, 0),
SC9860_SD0_D0_MISC = SPRD_PIN_INFO(208, MISC_PIN, 0, 0, 0),
SC9860_SD0_D1_MISC = SPRD_PIN_INFO(210, MISC_PIN, 0, 0, 0),
SC9860_SD0_CLK_MISC = SPRD_PIN_INFO(212, MISC_PIN, 0, 0, 0),
SC9860_EMMC_CMD_reserved_MISC = SPRD_PIN_INFO(214, MISC_PIN, 0, 0, 0),
SC9860_EMMC_CMD_MISC = SPRD_PIN_INFO(216, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D6_MISC = SPRD_PIN_INFO(218, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D7_MISC = SPRD_PIN_INFO(220, MISC_PIN, 0, 0, 0),
SC9860_EMMC_CLK_MISC = SPRD_PIN_INFO(222, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D5_MISC = SPRD_PIN_INFO(224, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D4_MISC = SPRD_PIN_INFO(226, MISC_PIN, 0, 0, 0),
SC9860_EMMC_DS_MISC = SPRD_PIN_INFO(228, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D3_reserved_MISC = SPRD_PIN_INFO(230, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D3_MISC = SPRD_PIN_INFO(232, MISC_PIN, 0, 0, 0),
SC9860_EMMC_RST_MISC = SPRD_PIN_INFO(234, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D1_MISC = SPRD_PIN_INFO(236, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D2_MISC = SPRD_PIN_INFO(238, MISC_PIN, 0, 0, 0),
SC9860_EMMC_D0_MISC = SPRD_PIN_INFO(240, MISC_PIN, 0, 0, 0),
SC9860_IIS0DI_MISC = SPRD_PIN_INFO(242, MISC_PIN, 0, 0, 0),
SC9860_IIS0DO_MISC = SPRD_PIN_INFO(244, MISC_PIN, 0, 0, 0),
SC9860_IIS0CLK_MISC = SPRD_PIN_INFO(246, MISC_PIN, 0, 0, 0),
SC9860_IIS0LRCK_MISC = SPRD_PIN_INFO(248, MISC_PIN, 0, 0, 0),
SC9860_SD1_CLK_MISC = SPRD_PIN_INFO(250, MISC_PIN, 0, 0, 0),
SC9860_SD1_CMD_MISC = SPRD_PIN_INFO(252, MISC_PIN, 0, 0, 0),
SC9860_SD1_D0_MISC = SPRD_PIN_INFO(254, MISC_PIN, 0, 0, 0),
SC9860_SD1_D1_MISC = SPRD_PIN_INFO(256, MISC_PIN, 0, 0, 0),
SC9860_SD1_D2_MISC = SPRD_PIN_INFO(258, MISC_PIN, 0, 0, 0),
SC9860_SD1_D3_MISC = SPRD_PIN_INFO(260, MISC_PIN, 0, 0, 0),
SC9860_CLK_AUX0_MISC = SPRD_PIN_INFO(262, MISC_PIN, 0, 0, 0),
SC9860_WIFI_COEXIST_MISC = SPRD_PIN_INFO(264, MISC_PIN, 0, 0, 0),
SC9860_BEIDOU_COEXIST_MISC = SPRD_PIN_INFO(266, MISC_PIN, 0, 0, 0),
SC9860_U3TXD_MISC = SPRD_PIN_INFO(268, MISC_PIN, 0, 0, 0),
SC9860_U3RXD_MISC = SPRD_PIN_INFO(270, MISC_PIN, 0, 0, 0),
SC9860_U3CTS_MISC = SPRD_PIN_INFO(272, MISC_PIN, 0, 0, 0),
SC9860_U3RTS_MISC = SPRD_PIN_INFO(274, MISC_PIN, 0, 0, 0),
SC9860_U0TXD_MISC = SPRD_PIN_INFO(276, MISC_PIN, 0, 0, 0),
SC9860_U0RXD_MISC = SPRD_PIN_INFO(278, MISC_PIN, 0, 0, 0),
SC9860_U0CTS_MISC = SPRD_PIN_INFO(280, MISC_PIN, 0, 0, 0),
SC9860_U0RTS_MISC = SPRD_PIN_INFO(282, MISC_PIN, 0, 0, 0),
SC9860_IIS1DI_MISC = SPRD_PIN_INFO(284, MISC_PIN, 0, 0, 0),
SC9860_IIS1DO_MISC = SPRD_PIN_INFO(286, MISC_PIN, 0, 0, 0),
SC9860_IIS1CLK_MISC = SPRD_PIN_INFO(288, MISC_PIN, 0, 0, 0),
SC9860_IIS1LRCK_MISC = SPRD_PIN_INFO(290, MISC_PIN, 0, 0, 0),
SC9860_SPI0_CSN_MISC = SPRD_PIN_INFO(292, MISC_PIN, 0, 0, 0),
SC9860_SPI0_DO_MISC = SPRD_PIN_INFO(294, MISC_PIN, 0, 0, 0),
SC9860_SPI0_DI_MISC = SPRD_PIN_INFO(296, MISC_PIN, 0, 0, 0),
SC9860_SPI0_CLK_MISC = SPRD_PIN_INFO(298, MISC_PIN, 0, 0, 0),
SC9860_U2TXD_MISC = SPRD_PIN_INFO(300, MISC_PIN, 0, 0, 0),
SC9860_U2RXD_MISC = SPRD_PIN_INFO(302, MISC_PIN, 0, 0, 0),
SC9860_U4TXD_MISC = SPRD_PIN_INFO(304, MISC_PIN, 0, 0, 0),
SC9860_U4RXD_MISC = SPRD_PIN_INFO(306, MISC_PIN, 0, 0, 0),
SC9860_CMMCLK1_MISC = SPRD_PIN_INFO(308, MISC_PIN, 0, 0, 0),
SC9860_CMRST1_MISC = SPRD_PIN_INFO(310, MISC_PIN, 0, 0, 0),
SC9860_CMMCLK0_MISC = SPRD_PIN_INFO(312, MISC_PIN, 0, 0, 0),
SC9860_CMRST0_MISC = SPRD_PIN_INFO(314, MISC_PIN, 0, 0, 0),
SC9860_CMPD0_MISC = SPRD_PIN_INFO(316, MISC_PIN, 0, 0, 0),
SC9860_CMPD1_MISC = SPRD_PIN_INFO(318, MISC_PIN, 0, 0, 0),
SC9860_SCL0_MISC = SPRD_PIN_INFO(320, MISC_PIN, 0, 0, 0),
SC9860_SDA0_MISC = SPRD_PIN_INFO(322, MISC_PIN, 0, 0, 0),
SC9860_SDA6_MISC = SPRD_PIN_INFO(324, MISC_PIN, 0, 0, 0),
SC9860_SCL6_MISC = SPRD_PIN_INFO(326, MISC_PIN, 0, 0, 0),
SC9860_U1TXD_MISC = SPRD_PIN_INFO(328, MISC_PIN, 0, 0, 0),
SC9860_U1RXD_MISC = SPRD_PIN_INFO(330, MISC_PIN, 0, 0, 0),
SC9860_KEYOUT0_MISC = SPRD_PIN_INFO(332, MISC_PIN, 0, 0, 0),
SC9860_KEYOUT1_MISC = SPRD_PIN_INFO(334, MISC_PIN, 0, 0, 0),
SC9860_KEYOUT2_MISC = SPRD_PIN_INFO(336, MISC_PIN, 0, 0, 0),
SC9860_KEYIN0_MISC = SPRD_PIN_INFO(338, MISC_PIN, 0, 0, 0),
SC9860_KEYIN1_MISC = SPRD_PIN_INFO(340, MISC_PIN, 0, 0, 0),
SC9860_KEYIN2_MISC = SPRD_PIN_INFO(342, MISC_PIN, 0, 0, 0),
SC9860_IIS3DI_MISC = SPRD_PIN_INFO(344, MISC_PIN, 0, 0, 0),
SC9860_IIS3DO_MISC = SPRD_PIN_INFO(346, MISC_PIN, 0, 0, 0),
SC9860_IIS3CLK_MISC = SPRD_PIN_INFO(348, MISC_PIN, 0, 0, 0),
SC9860_IIS3LRCK_MISC = SPRD_PIN_INFO(350, MISC_PIN, 0, 0, 0),
SC9860_RFCTL0_MISC = SPRD_PIN_INFO(352, MISC_PIN, 0, 0, 0),
SC9860_RFCTL1_MISC = SPRD_PIN_INFO(354, MISC_PIN, 0, 0, 0),
SC9860_RFCTL10_MISC = SPRD_PIN_INFO(356, MISC_PIN, 0, 0, 0),
SC9860_RFCTL11_MISC = SPRD_PIN_INFO(358, MISC_PIN, 0, 0, 0),
SC9860_RFCTL12_MISC = SPRD_PIN_INFO(360, MISC_PIN, 0, 0, 0),
SC9860_RFCTL13_MISC = SPRD_PIN_INFO(362, MISC_PIN, 0, 0, 0),
SC9860_RFCTL14_MISC = SPRD_PIN_INFO(364, MISC_PIN, 0, 0, 0),
SC9860_RFCTL15_MISC = SPRD_PIN_INFO(366, MISC_PIN, 0, 0, 0),
SC9860_RFCTL16_MISC = SPRD_PIN_INFO(368, MISC_PIN, 0, 0, 0),
SC9860_RFCTL17_MISC = SPRD_PIN_INFO(370, MISC_PIN, 0, 0, 0),
SC9860_RFCTL18_MISC = SPRD_PIN_INFO(372, MISC_PIN, 0, 0, 0),
SC9860_RFCTL19_MISC = SPRD_PIN_INFO(374, MISC_PIN, 0, 0, 0),
SC9860_RFCTL2_MISC = SPRD_PIN_INFO(376, MISC_PIN, 0, 0, 0),
SC9860_EXTINT5_MISC = SPRD_PIN_INFO(378, MISC_PIN, 0, 0, 0),
SC9860_EXTINT6_MISC = SPRD_PIN_INFO(380, MISC_PIN, 0, 0, 0),
SC9860_EXTINT7_MISC = SPRD_PIN_INFO(382, MISC_PIN, 0, 0, 0),
SC9860_GPIO30_MISC = SPRD_PIN_INFO(384, MISC_PIN, 0, 0, 0),
SC9860_GPIO31_MISC = SPRD_PIN_INFO(386, MISC_PIN, 0, 0, 0),
SC9860_GPIO32_MISC = SPRD_PIN_INFO(388, MISC_PIN, 0, 0, 0),
SC9860_GPIO33_MISC = SPRD_PIN_INFO(390, MISC_PIN, 0, 0, 0),
SC9860_GPIO34_MISC = SPRD_PIN_INFO(392, MISC_PIN, 0, 0, 0),
SC9860_RFCTL3_MISC = SPRD_PIN_INFO(394, MISC_PIN, 0, 0, 0),
SC9860_RFCTL4_MISC = SPRD_PIN_INFO(396, MISC_PIN, 0, 0, 0),
SC9860_RFCTL5_MISC = SPRD_PIN_INFO(398, MISC_PIN, 0, 0, 0),
SC9860_RFCTL6_MISC = SPRD_PIN_INFO(400, MISC_PIN, 0, 0, 0),
SC9860_RFCTL7_MISC = SPRD_PIN_INFO(402, MISC_PIN, 0, 0, 0),
SC9860_RFCTL8_MISC = SPRD_PIN_INFO(404, MISC_PIN, 0, 0, 0),
SC9860_RFCTL9_MISC = SPRD_PIN_INFO(406, MISC_PIN, 0, 0, 0),
SC9860_RFFE0_SCK0_MISC = SPRD_PIN_INFO(408, MISC_PIN, 0, 0, 0),
SC9860_GPIO38_MISC = SPRD_PIN_INFO(410, MISC_PIN, 0, 0, 0),
SC9860_RFFE0_SDA0_MISC = SPRD_PIN_INFO(412, MISC_PIN, 0, 0, 0),
SC9860_GPIO39_MISC = SPRD_PIN_INFO(414, MISC_PIN, 0, 0, 0),
SC9860_RFFE1_SCK0_MISC = SPRD_PIN_INFO(416, MISC_PIN, 0, 0, 0),
SC9860_GPIO181_MISC = SPRD_PIN_INFO(418, MISC_PIN, 0, 0, 0),
SC9860_RFFE1_SDA0_MISC = SPRD_PIN_INFO(420, MISC_PIN, 0, 0, 0),
SC9860_GPIO182_MISC = SPRD_PIN_INFO(422, MISC_PIN, 0, 0, 0),
SC9860_RF_LVDS0_ADC_ON_MISC = SPRD_PIN_INFO(424, MISC_PIN, 0, 0, 0),
SC9860_RF_LVDS0_DAC_ON_MISC = SPRD_PIN_INFO(426, MISC_PIN, 0, 0, 0),
SC9860_RFSCK0_MISC = SPRD_PIN_INFO(428, MISC_PIN, 0, 0, 0),
SC9860_RFSDA0_MISC = SPRD_PIN_INFO(430, MISC_PIN, 0, 0, 0),
SC9860_RFSEN0_MISC = SPRD_PIN_INFO(432, MISC_PIN, 0, 0, 0),
SC9860_RF_LVDS1_ADC_ON_MISC = SPRD_PIN_INFO(434, MISC_PIN, 0, 0, 0),
SC9860_RF_LVDS1_DAC_ON_MISC = SPRD_PIN_INFO(436, MISC_PIN, 0, 0, 0),
SC9860_RFSCK1_MISC = SPRD_PIN_INFO(438, MISC_PIN, 0, 0, 0),
SC9860_RFSDA1_MISC = SPRD_PIN_INFO(440, MISC_PIN, 0, 0, 0),
SC9860_RFSEN1_MISC = SPRD_PIN_INFO(442, MISC_PIN, 0, 0, 0),
SC9860_RFCTL38_MISC = SPRD_PIN_INFO(444, MISC_PIN, 0, 0, 0),
SC9860_RFCTL39_MISC = SPRD_PIN_INFO(446, MISC_PIN, 0, 0, 0),
};
static struct sprd_pins_info sprd_sc9860_pins_info[] = {
SPRD_PINCTRL_PIN(SC9860_VIO28_0_IRTE),
SPRD_PINCTRL_PIN(SC9860_VIO_SD2_IRTE),
SPRD_PINCTRL_PIN(SC9860_VIO_SD0_IRTE),
SPRD_PINCTRL_PIN(SC9860_VIO_SIM2_IRTE),
SPRD_PINCTRL_PIN(SC9860_VIO_SIM1_IRTE),
SPRD_PINCTRL_PIN(SC9860_VIO_SIM0_IRTE),
SPRD_PINCTRL_PIN(SC9860_VIO28_0_MS),
SPRD_PINCTRL_PIN(SC9860_VIO_SD2_MS),
SPRD_PINCTRL_PIN(SC9860_VIO_SD0_MS),
SPRD_PINCTRL_PIN(SC9860_VIO_SIM2_MS),
SPRD_PINCTRL_PIN(SC9860_VIO_SIM1_MS),
SPRD_PINCTRL_PIN(SC9860_VIO_SIM0_MS),
SPRD_PINCTRL_PIN(SC9860_SPSPI_PIN_IN_SEL),
SPRD_PINCTRL_PIN(SC9860_UART1_USB30_PHY_SEL),
SPRD_PINCTRL_PIN(SC9860_USB30_PHY_DM_OE),
SPRD_PINCTRL_PIN(SC9860_USB30_PHY_DP_OE),
SPRD_PINCTRL_PIN(SC9860_UART5_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_ORP_URXD_PIN_IN_SEL),
SPRD_PINCTRL_PIN(SC9860_SIM2_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_SIM1_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_SIM0_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_CLK26MHZ_BUF_OUT_SEL),
SPRD_PINCTRL_PIN(SC9860_UART4_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_UART3_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_UART2_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_UART1_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_UART0_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_UART24_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_UART23_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_UART14_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_UART13_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS3_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS2_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS1_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS0_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS23_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS13_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS12_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS03_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS02_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS01_LOOP_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS6_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS5_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_IIS4_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_I2C_INF6_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_I2C_INF4_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_I2C_INF2_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_I2C_INF1_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_I2C_INF0_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_GPIO_INF7_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_GPIO_INF6_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_GPIO_INF5_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_GPIO_INF4_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_GPIO_INF3_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_GPIO_INF2_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_GPIO_INF1_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_GPIO_INF0_SYS_SEL),
SPRD_PINCTRL_PIN(SC9860_WDRST_OUT_SEL),
SPRD_PINCTRL_PIN(SC9860_ADI_SYNC_PIN_OUT_SEL),
SPRD_PINCTRL_PIN(SC9860_CMRST_SEL),
SPRD_PINCTRL_PIN(SC9860_CMPD_SEL),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE11),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE10),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE9),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE8),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE7),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE6),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE5),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE4),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE3),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE2),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE1),
SPRD_PINCTRL_PIN(SC9860_TEST_DBG_MODE0),
SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD3_SEL),
SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD2_SEL),
SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD1_SEL),
SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD0_SEL),
SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD7_SEL),
SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD6_SEL),
SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD5_SEL),
SPRD_PINCTRL_PIN(SC9860_SP_EIC_DPAD4_SEL),
SPRD_PINCTRL_PIN(SC9860_RFCTL20),
SPRD_PINCTRL_PIN(SC9860_RFCTL21),
SPRD_PINCTRL_PIN(SC9860_RFCTL30),
SPRD_PINCTRL_PIN(SC9860_RFCTL31),
SPRD_PINCTRL_PIN(SC9860_RFCTL32),
SPRD_PINCTRL_PIN(SC9860_RFCTL33),
SPRD_PINCTRL_PIN(SC9860_RFCTL34),
SPRD_PINCTRL_PIN(SC9860_RFCTL35),
SPRD_PINCTRL_PIN(SC9860_RFCTL36),
SPRD_PINCTRL_PIN(SC9860_RFCTL37),
SPRD_PINCTRL_PIN(SC9860_RFCTL22),
SPRD_PINCTRL_PIN(SC9860_RFCTL23),
SPRD_PINCTRL_PIN(SC9860_RFCTL24),
SPRD_PINCTRL_PIN(SC9860_RFCTL25),
SPRD_PINCTRL_PIN(SC9860_RFCTL26),
SPRD_PINCTRL_PIN(SC9860_RFCTL27),
SPRD_PINCTRL_PIN(SC9860_RFCTL28),
SPRD_PINCTRL_PIN(SC9860_RFCTL29),
SPRD_PINCTRL_PIN(SC9860_SCL2),
SPRD_PINCTRL_PIN(SC9860_SDA2),
SPRD_PINCTRL_PIN(SC9860_MTCK_ARM),
SPRD_PINCTRL_PIN(SC9860_MTMS_ARM),
SPRD_PINCTRL_PIN(SC9860_XTL_EN0),
SPRD_PINCTRL_PIN(SC9860_PTEST),
SPRD_PINCTRL_PIN(SC9860_AUD_DAD1),
SPRD_PINCTRL_PIN(SC9860_AUD_ADD0),
SPRD_PINCTRL_PIN(SC9860_AUD_ADSYNC),
SPRD_PINCTRL_PIN(SC9860_AUD_SCLK),
SPRD_PINCTRL_PIN(SC9860_CHIP_SLEEP),
SPRD_PINCTRL_PIN(SC9860_CLK_32K),
SPRD_PINCTRL_PIN(SC9860_DCDC_ARM_EN),
SPRD_PINCTRL_PIN(SC9860_EXT_RST_B),
SPRD_PINCTRL_PIN(SC9860_ADI_D),
SPRD_PINCTRL_PIN(SC9860_ADI_SCLK),
SPRD_PINCTRL_PIN(SC9860_XTL_EN1),
SPRD_PINCTRL_PIN(SC9860_ANA_INT),
SPRD_PINCTRL_PIN(SC9860_AUD_DAD0),
SPRD_PINCTRL_PIN(SC9860_AUD_DASYNC),
SPRD_PINCTRL_PIN(SC9860_LCM_RSTN),
SPRD_PINCTRL_PIN(SC9860_DSI_TE),
SPRD_PINCTRL_PIN(SC9860_PWMA),
SPRD_PINCTRL_PIN(SC9860_EXTINT0),
SPRD_PINCTRL_PIN(SC9860_EXTINT1),
SPRD_PINCTRL_PIN(SC9860_SDA1),
SPRD_PINCTRL_PIN(SC9860_SCL1),
SPRD_PINCTRL_PIN(SC9860_SIMCLK2),
SPRD_PINCTRL_PIN(SC9860_SIMDA2),
SPRD_PINCTRL_PIN(SC9860_SIMRST2),
SPRD_PINCTRL_PIN(SC9860_SIMCLK1),
SPRD_PINCTRL_PIN(SC9860_SIMDA1),
SPRD_PINCTRL_PIN(SC9860_SIMRST1),
SPRD_PINCTRL_PIN(SC9860_SIMCLK0),
SPRD_PINCTRL_PIN(SC9860_SIMDA0),
SPRD_PINCTRL_PIN(SC9860_SIMRST0),
SPRD_PINCTRL_PIN(SC9860_SD2_CMD),
SPRD_PINCTRL_PIN(SC9860_SD2_D0),
SPRD_PINCTRL_PIN(SC9860_SD2_D1),
SPRD_PINCTRL_PIN(SC9860_SD2_CLK),
SPRD_PINCTRL_PIN(SC9860_SD2_D2),
SPRD_PINCTRL_PIN(SC9860_SD2_D3),
SPRD_PINCTRL_PIN(SC9860_SD0_D3),
SPRD_PINCTRL_PIN(SC9860_SD0_D2),
SPRD_PINCTRL_PIN(SC9860_SD0_CMD),
SPRD_PINCTRL_PIN(SC9860_SD0_D0),
SPRD_PINCTRL_PIN(SC9860_SD0_D1),
SPRD_PINCTRL_PIN(SC9860_SD0_CLK),
SPRD_PINCTRL_PIN(SC9860_EMMC_CMD),
SPRD_PINCTRL_PIN(SC9860_EMMC_D6),
SPRD_PINCTRL_PIN(SC9860_EMMC_D7),
SPRD_PINCTRL_PIN(SC9860_EMMC_CLK),
SPRD_PINCTRL_PIN(SC9860_EMMC_D5),
SPRD_PINCTRL_PIN(SC9860_EMMC_D4),
SPRD_PINCTRL_PIN(SC9860_EMMC_DS),
SPRD_PINCTRL_PIN(SC9860_EMMC_D3),
SPRD_PINCTRL_PIN(SC9860_EMMC_RST),
SPRD_PINCTRL_PIN(SC9860_EMMC_D1),
SPRD_PINCTRL_PIN(SC9860_EMMC_D2),
SPRD_PINCTRL_PIN(SC9860_EMMC_D0),
SPRD_PINCTRL_PIN(SC9860_IIS0DI),
SPRD_PINCTRL_PIN(SC9860_IIS0DO),
SPRD_PINCTRL_PIN(SC9860_IIS0CLK),
SPRD_PINCTRL_PIN(SC9860_IIS0LRCK),
SPRD_PINCTRL_PIN(SC9860_SD1_CLK),
SPRD_PINCTRL_PIN(SC9860_SD1_CMD),
SPRD_PINCTRL_PIN(SC9860_SD1_D0),
SPRD_PINCTRL_PIN(SC9860_SD1_D1),
SPRD_PINCTRL_PIN(SC9860_SD1_D2),
SPRD_PINCTRL_PIN(SC9860_SD1_D3),
SPRD_PINCTRL_PIN(SC9860_CLK_AUX0),
SPRD_PINCTRL_PIN(SC9860_WIFI_COEXIST),
SPRD_PINCTRL_PIN(SC9860_BEIDOU_COEXIST),
SPRD_PINCTRL_PIN(SC9860_U3TXD),
SPRD_PINCTRL_PIN(SC9860_U3RXD),
SPRD_PINCTRL_PIN(SC9860_U3CTS),
SPRD_PINCTRL_PIN(SC9860_U3RTS),
SPRD_PINCTRL_PIN(SC9860_U0TXD),
SPRD_PINCTRL_PIN(SC9860_U0RXD),
SPRD_PINCTRL_PIN(SC9860_U0CTS),
SPRD_PINCTRL_PIN(SC9860_U0RTS),
SPRD_PINCTRL_PIN(SC9860_IIS1DI),
SPRD_PINCTRL_PIN(SC9860_IIS1DO),
SPRD_PINCTRL_PIN(SC9860_IIS1CLK),
SPRD_PINCTRL_PIN(SC9860_IIS1LRCK),
SPRD_PINCTRL_PIN(SC9860_SPI0_CSN),
SPRD_PINCTRL_PIN(SC9860_SPI0_DO),
SPRD_PINCTRL_PIN(SC9860_SPI0_DI),
SPRD_PINCTRL_PIN(SC9860_SPI0_CLK),
SPRD_PINCTRL_PIN(SC9860_U2TXD),
SPRD_PINCTRL_PIN(SC9860_U2RXD),
SPRD_PINCTRL_PIN(SC9860_U4TXD),
SPRD_PINCTRL_PIN(SC9860_U4RXD),
SPRD_PINCTRL_PIN(SC9860_CMMCLK1),
SPRD_PINCTRL_PIN(SC9860_CMRST1),
SPRD_PINCTRL_PIN(SC9860_CMMCLK0),
SPRD_PINCTRL_PIN(SC9860_CMRST0),
SPRD_PINCTRL_PIN(SC9860_CMPD0),
SPRD_PINCTRL_PIN(SC9860_CMPD1),
SPRD_PINCTRL_PIN(SC9860_SCL0),
SPRD_PINCTRL_PIN(SC9860_SDA0),
SPRD_PINCTRL_PIN(SC9860_SDA6),
SPRD_PINCTRL_PIN(SC9860_SCL6),
SPRD_PINCTRL_PIN(SC9860_U1TXD),
SPRD_PINCTRL_PIN(SC9860_U1RXD),
SPRD_PINCTRL_PIN(SC9860_KEYOUT0),
SPRD_PINCTRL_PIN(SC9860_KEYOUT1),
SPRD_PINCTRL_PIN(SC9860_KEYOUT2),
SPRD_PINCTRL_PIN(SC9860_KEYIN0),
SPRD_PINCTRL_PIN(SC9860_KEYIN1),
SPRD_PINCTRL_PIN(SC9860_KEYIN2),
SPRD_PINCTRL_PIN(SC9860_IIS3DI),
SPRD_PINCTRL_PIN(SC9860_IIS3DO),
SPRD_PINCTRL_PIN(SC9860_IIS3CLK),
SPRD_PINCTRL_PIN(SC9860_IIS3LRCK),
SPRD_PINCTRL_PIN(SC9860_RFCTL0),
SPRD_PINCTRL_PIN(SC9860_RFCTL1),
SPRD_PINCTRL_PIN(SC9860_RFCTL10),
SPRD_PINCTRL_PIN(SC9860_RFCTL11),
SPRD_PINCTRL_PIN(SC9860_RFCTL12),
SPRD_PINCTRL_PIN(SC9860_RFCTL13),
SPRD_PINCTRL_PIN(SC9860_RFCTL14),
SPRD_PINCTRL_PIN(SC9860_RFCTL15),
SPRD_PINCTRL_PIN(SC9860_RFCTL16),
SPRD_PINCTRL_PIN(SC9860_RFCTL17),
SPRD_PINCTRL_PIN(SC9860_RFCTL18),
SPRD_PINCTRL_PIN(SC9860_RFCTL19),
SPRD_PINCTRL_PIN(SC9860_RFCTL2),
SPRD_PINCTRL_PIN(SC9860_EXTINT5),
SPRD_PINCTRL_PIN(SC9860_EXTINT6),
SPRD_PINCTRL_PIN(SC9860_EXTINT7),
SPRD_PINCTRL_PIN(SC9860_GPIO30),
SPRD_PINCTRL_PIN(SC9860_GPIO31),
SPRD_PINCTRL_PIN(SC9860_GPIO32),
SPRD_PINCTRL_PIN(SC9860_GPIO33),
SPRD_PINCTRL_PIN(SC9860_GPIO34),
SPRD_PINCTRL_PIN(SC9860_RFCTL3),
SPRD_PINCTRL_PIN(SC9860_RFCTL4),
SPRD_PINCTRL_PIN(SC9860_RFCTL5),
SPRD_PINCTRL_PIN(SC9860_RFCTL6),
SPRD_PINCTRL_PIN(SC9860_RFCTL7),
SPRD_PINCTRL_PIN(SC9860_RFCTL8),
SPRD_PINCTRL_PIN(SC9860_RFCTL9),
SPRD_PINCTRL_PIN(SC9860_RFFE0_SCK0),
SPRD_PINCTRL_PIN(SC9860_GPIO38),
SPRD_PINCTRL_PIN(SC9860_RFFE0_SDA0),
SPRD_PINCTRL_PIN(SC9860_GPIO39),
SPRD_PINCTRL_PIN(SC9860_RFFE1_SCK0),
SPRD_PINCTRL_PIN(SC9860_GPIO181),
SPRD_PINCTRL_PIN(SC9860_RFFE1_SDA0),
SPRD_PINCTRL_PIN(SC9860_GPIO182),
SPRD_PINCTRL_PIN(SC9860_RF_LVDS0_ADC_ON),
SPRD_PINCTRL_PIN(SC9860_RF_LVDS0_DAC_ON),
SPRD_PINCTRL_PIN(SC9860_RFSCK0),
SPRD_PINCTRL_PIN(SC9860_RFSDA0),
SPRD_PINCTRL_PIN(SC9860_RFSEN0),
SPRD_PINCTRL_PIN(SC9860_RF_LVDS1_ADC_ON),
SPRD_PINCTRL_PIN(SC9860_RF_LVDS1_DAC_ON),
SPRD_PINCTRL_PIN(SC9860_RFSCK1),
SPRD_PINCTRL_PIN(SC9860_RFSDA1),
SPRD_PINCTRL_PIN(SC9860_RFSEN1),
SPRD_PINCTRL_PIN(SC9860_RFCTL38),
SPRD_PINCTRL_PIN(SC9860_RFCTL39),
SPRD_PINCTRL_PIN(SC9860_RFCTL20_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL21_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL30_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL31_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL32_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL33_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL34_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL35_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL36_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL37_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL22_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL23_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL24_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL25_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL26_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL27_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL28_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL29_MISC),
SPRD_PINCTRL_PIN(SC9860_SCL2_MISC),
SPRD_PINCTRL_PIN(SC9860_SDA2_MISC),
SPRD_PINCTRL_PIN(SC9860_MTCK_ARM_MISC),
SPRD_PINCTRL_PIN(SC9860_MTMS_ARM_MISC),
SPRD_PINCTRL_PIN(SC9860_XTL_EN0_MISC),
SPRD_PINCTRL_PIN(SC9860_PTEST_MISC),
SPRD_PINCTRL_PIN(SC9860_AUD_DAD1_MISC),
SPRD_PINCTRL_PIN(SC9860_AUD_ADD0_MISC),
SPRD_PINCTRL_PIN(SC9860_AUD_ADSYNC_MISC),
SPRD_PINCTRL_PIN(SC9860_AUD_SCLK_MISC),
SPRD_PINCTRL_PIN(SC9860_CHIP_SLEEP_MISC),
SPRD_PINCTRL_PIN(SC9860_CLK_32K_MISC),
SPRD_PINCTRL_PIN(SC9860_DCDC_ARM_EN_MISC),
SPRD_PINCTRL_PIN(SC9860_EXT_RST_B_MISC),
SPRD_PINCTRL_PIN(SC9860_ADI_D_MISC),
SPRD_PINCTRL_PIN(SC9860_ADI_SCLK_MISC),
SPRD_PINCTRL_PIN(SC9860_XTL_EN1_MISC),
SPRD_PINCTRL_PIN(SC9860_ANA_INT_MISC),
SPRD_PINCTRL_PIN(SC9860_AUD_DAD0_MISC),
SPRD_PINCTRL_PIN(SC9860_AUD_DASYNC_MISC),
SPRD_PINCTRL_PIN(SC9860_LCM_RSTN_MISC),
SPRD_PINCTRL_PIN(SC9860_DSI_TE_MISC),
SPRD_PINCTRL_PIN(SC9860_PWMA_MISC),
SPRD_PINCTRL_PIN(SC9860_EXTINT0_MISC),
SPRD_PINCTRL_PIN(SC9860_EXTINT1_MISC),
SPRD_PINCTRL_PIN(SC9860_SDA1_MISC),
SPRD_PINCTRL_PIN(SC9860_SCL1_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMCLK2_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMDA2_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMRST2_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMCLK1_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMDA1_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMRST1_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMCLK0_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMDA0_MISC),
SPRD_PINCTRL_PIN(SC9860_SIMRST0_MISC),
SPRD_PINCTRL_PIN(SC9860_SD2_CMD_MISC),
SPRD_PINCTRL_PIN(SC9860_SD2_D0_MISC),
SPRD_PINCTRL_PIN(SC9860_SD2_D1_MISC),
SPRD_PINCTRL_PIN(SC9860_SD2_CLK_MISC),
SPRD_PINCTRL_PIN(SC9860_SD2_D2_MISC),
SPRD_PINCTRL_PIN(SC9860_SD2_D3_MISC),
SPRD_PINCTRL_PIN(SC9860_SD0_D3_MISC),
SPRD_PINCTRL_PIN(SC9860_SD0_D2_MISC),
SPRD_PINCTRL_PIN(SC9860_SD0_CMD_MISC),
SPRD_PINCTRL_PIN(SC9860_SD0_D0_MISC),
SPRD_PINCTRL_PIN(SC9860_SD0_D1_MISC),
SPRD_PINCTRL_PIN(SC9860_SD0_CLK_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_CMD_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_D6_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_D7_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_CLK_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_D5_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_D4_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_DS_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_D3_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_RST_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_D1_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_D2_MISC),
SPRD_PINCTRL_PIN(SC9860_EMMC_D0_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS0DI_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS0DO_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS0CLK_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS0LRCK_MISC),
SPRD_PINCTRL_PIN(SC9860_SD1_CLK_MISC),
SPRD_PINCTRL_PIN(SC9860_SD1_CMD_MISC),
SPRD_PINCTRL_PIN(SC9860_SD1_D0_MISC),
SPRD_PINCTRL_PIN(SC9860_SD1_D1_MISC),
SPRD_PINCTRL_PIN(SC9860_SD1_D2_MISC),
SPRD_PINCTRL_PIN(SC9860_SD1_D3_MISC),
SPRD_PINCTRL_PIN(SC9860_CLK_AUX0_MISC),
SPRD_PINCTRL_PIN(SC9860_WIFI_COEXIST_MISC),
SPRD_PINCTRL_PIN(SC9860_BEIDOU_COEXIST_MISC),
SPRD_PINCTRL_PIN(SC9860_U3TXD_MISC),
SPRD_PINCTRL_PIN(SC9860_U3RXD_MISC),
SPRD_PINCTRL_PIN(SC9860_U3CTS_MISC),
SPRD_PINCTRL_PIN(SC9860_U3RTS_MISC),
SPRD_PINCTRL_PIN(SC9860_U0TXD_MISC),
SPRD_PINCTRL_PIN(SC9860_U0RXD_MISC),
SPRD_PINCTRL_PIN(SC9860_U0CTS_MISC),
SPRD_PINCTRL_PIN(SC9860_U0RTS_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS1DI_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS1DO_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS1CLK_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS1LRCK_MISC),
SPRD_PINCTRL_PIN(SC9860_SPI0_CSN_MISC),
SPRD_PINCTRL_PIN(SC9860_SPI0_DO_MISC),
SPRD_PINCTRL_PIN(SC9860_SPI0_DI_MISC),
SPRD_PINCTRL_PIN(SC9860_SPI0_CLK_MISC),
SPRD_PINCTRL_PIN(SC9860_U2TXD_MISC),
SPRD_PINCTRL_PIN(SC9860_U2RXD_MISC),
SPRD_PINCTRL_PIN(SC9860_U4TXD_MISC),
SPRD_PINCTRL_PIN(SC9860_U4RXD_MISC),
SPRD_PINCTRL_PIN(SC9860_CMMCLK1_MISC),
SPRD_PINCTRL_PIN(SC9860_CMRST1_MISC),
SPRD_PINCTRL_PIN(SC9860_CMMCLK0_MISC),
SPRD_PINCTRL_PIN(SC9860_CMRST0_MISC),
SPRD_PINCTRL_PIN(SC9860_CMPD0_MISC),
SPRD_PINCTRL_PIN(SC9860_CMPD1_MISC),
SPRD_PINCTRL_PIN(SC9860_SCL0_MISC),
SPRD_PINCTRL_PIN(SC9860_SDA0_MISC),
SPRD_PINCTRL_PIN(SC9860_SDA6_MISC),
SPRD_PINCTRL_PIN(SC9860_SCL6_MISC),
SPRD_PINCTRL_PIN(SC9860_U1TXD_MISC),
SPRD_PINCTRL_PIN(SC9860_U1RXD_MISC),
SPRD_PINCTRL_PIN(SC9860_KEYOUT0_MISC),
SPRD_PINCTRL_PIN(SC9860_KEYOUT1_MISC),
SPRD_PINCTRL_PIN(SC9860_KEYOUT2_MISC),
SPRD_PINCTRL_PIN(SC9860_KEYIN0_MISC),
SPRD_PINCTRL_PIN(SC9860_KEYIN1_MISC),
SPRD_PINCTRL_PIN(SC9860_KEYIN2_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS3DI_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS3DO_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS3CLK_MISC),
SPRD_PINCTRL_PIN(SC9860_IIS3LRCK_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL0_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL1_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL10_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL11_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL12_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL13_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL14_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL15_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL16_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL17_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL18_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL19_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL2_MISC),
SPRD_PINCTRL_PIN(SC9860_EXTINT5_MISC),
SPRD_PINCTRL_PIN(SC9860_EXTINT6_MISC),
SPRD_PINCTRL_PIN(SC9860_EXTINT7_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO30_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO31_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO32_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO33_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO34_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL3_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL4_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL5_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL6_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL7_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL8_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL9_MISC),
SPRD_PINCTRL_PIN(SC9860_RFFE0_SCK0_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO38_MISC),
SPRD_PINCTRL_PIN(SC9860_RFFE0_SDA0_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO39_MISC),
SPRD_PINCTRL_PIN(SC9860_RFFE1_SCK0_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO181_MISC),
SPRD_PINCTRL_PIN(SC9860_RFFE1_SDA0_MISC),
SPRD_PINCTRL_PIN(SC9860_GPIO182_MISC),
SPRD_PINCTRL_PIN(SC9860_RF_LVDS0_ADC_ON_MISC),
SPRD_PINCTRL_PIN(SC9860_RF_LVDS0_DAC_ON_MISC),
SPRD_PINCTRL_PIN(SC9860_RFSCK0_MISC),
SPRD_PINCTRL_PIN(SC9860_RFSDA0_MISC),
SPRD_PINCTRL_PIN(SC9860_RFSEN0_MISC),
SPRD_PINCTRL_PIN(SC9860_RF_LVDS1_ADC_ON_MISC),
SPRD_PINCTRL_PIN(SC9860_RF_LVDS1_DAC_ON_MISC),
SPRD_PINCTRL_PIN(SC9860_RFSCK1_MISC),
SPRD_PINCTRL_PIN(SC9860_RFSDA1_MISC),
SPRD_PINCTRL_PIN(SC9860_RFSEN1_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL38_MISC),
SPRD_PINCTRL_PIN(SC9860_RFCTL39_MISC),
};
static int sprd_pinctrl_probe(struct platform_device *pdev)
{
return sprd_pinctrl_core_probe(pdev, sprd_sc9860_pins_info,
ARRAY_SIZE(sprd_sc9860_pins_info));
}
static const struct of_device_id sprd_pinctrl_of_match[] = {
{
.compatible = "sprd,sc9860-pinctrl",
},
{ },
};
MODULE_DEVICE_TABLE(of, sprd_pinctrl_of_match);
static struct platform_driver sprd_pinctrl_driver = {
.driver = {
.name = "sprd-pinctrl",
.owner = THIS_MODULE,
.of_match_table = sprd_pinctrl_of_match,
},
.probe = sprd_pinctrl_probe,
.remove = sprd_pinctrl_remove,
.shutdown = sprd_pinctrl_shutdown,
};
static int sprd_pinctrl_init(void)
{
return platform_driver_register(&sprd_pinctrl_driver);
}
module_init(sprd_pinctrl_init);
static void sprd_pinctrl_exit(void)
{
platform_driver_unregister(&sprd_pinctrl_driver);
}
module_exit(sprd_pinctrl_exit);
MODULE_DESCRIPTION("SPREADTRUM Pin Controller Driver");
MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>");
MODULE_LICENSE("GPL v2");

1113
drivers/pinctrl/sprd/pinctrl-sprd.c Normal file
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File diff suppressed because it is too large Load diff

67
drivers/pinctrl/sprd/pinctrl-sprd.h Normal file
View file

@ -0,0 +1,67 @@
/*
* Driver header file for pin controller driver
* Copyright (C) 2017 Spreadtrum - http://www.spreadtrum.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
#ifndef __PINCTRL_SPRD_H__
#define __PINCTRL_SPRD_H__
struct platform_device;
#define NUM_OFFSET (20)
#define TYPE_OFFSET (16)
#define BIT_OFFSET (8)
#define WIDTH_OFFSET (4)
#define SPRD_PIN_INFO(num, type, offset, width, reg) \
(((num) & 0xFFF) << NUM_OFFSET | \
((type) & 0xF) << TYPE_OFFSET | \
((offset) & 0xFF) << BIT_OFFSET | \
((width) & 0xF) << WIDTH_OFFSET | \
((reg) & 0xF))
#define SPRD_PINCTRL_PIN(pin) SPRD_PINCTRL_PIN_DATA(pin, #pin)
#define SPRD_PINCTRL_PIN_DATA(a, b) \
{ \
.name = b, \
.num = (((a) >> NUM_OFFSET) & 0xfff), \
.type = (((a) >> TYPE_OFFSET) & 0xf), \
.bit_offset = (((a) >> BIT_OFFSET) & 0xff), \
.bit_width = ((a) >> WIDTH_OFFSET & 0xf), \
.reg = ((a) & 0xf) \
}
enum pin_type {
GLOBAL_CTRL_PIN,
COMMON_PIN,
MISC_PIN,
};
struct sprd_pins_info {
const char *name;
unsigned int num;
enum pin_type type;
/* for global control pins configuration */
unsigned long bit_offset;
unsigned long bit_width;
unsigned int reg;
};
int sprd_pinctrl_core_probe(struct platform_device *pdev,
struct sprd_pins_info *sprd_soc_pin_info,
int pins_cnt);
int sprd_pinctrl_remove(struct platform_device *pdev);
void sprd_pinctrl_shutdown(struct platform_device *pdev);
#endif /* __PINCTRL_SPRD_H__ */

2
drivers/pinctrl/stm32/pinctrl-stm32.c
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@ -952,7 +952,7 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
int npins = STM32_GPIO_PINS_PER_BANK;
int bank_nr, err;
rstc = of_reset_control_get(np, NULL);
rstc = of_reset_control_get_exclusive(np, NULL);
if (!IS_ERR(rstc))
reset_control_deassert(rstc);

2
drivers/pinctrl/sunxi/Kconfig
View file

@ -7,7 +7,7 @@ config PINCTRL_SUNXI
select GPIOLIB
config PINCTRL_SUN4I_A10
def_bool MACH_SUN4I || MACH_SUN7I
def_bool MACH_SUN4I || MACH_SUN7I || MACH_SUN8I
select PINCTRL_SUNXI
config PINCTRL_SUN5I

273
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
View file

@ -26,7 +26,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
SUNXI_FUNCTION(0x4, "uart2"), /* RTS */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD3 */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -34,7 +35,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
SUNXI_FUNCTION(0x4, "uart2"), /* CTS */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD2 */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -42,7 +44,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
SUNXI_FUNCTION(0x4, "uart2"), /* TX */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD1 */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -50,65 +53,75 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
SUNXI_FUNCTION(0x4, "uart2"), /* RX */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXD0 */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD3 */
SUNXI_FUNCTION(0x3, "spi1"), /* CS1 */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD3 */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD2 */
SUNXI_FUNCTION(0x3, "spi3"), /* CS0 */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD2 */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD1 */
SUNXI_FUNCTION(0x3, "spi3"), /* CLK */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD1 */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ETXD0 */
SUNXI_FUNCTION(0x3, "spi3"), /* MOSI */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXD0 */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXCK */
SUNXI_FUNCTION(0x3, "spi3"), /* MISO */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXCK */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXERR */
SUNXI_FUNCTION(0x3, "spi3"), /* CS1 */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ERXERR */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* MCLK */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* ERXDV */
SUNXI_FUNCTION(0x4, "uart1"), /* TX */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GRXDV */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "emac"), /* EMDC */
SUNXI_FUNCTION(0x4, "uart1"), /* RX */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* EMDC */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -116,7 +129,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
SUNXI_FUNCTION(0x4, "uart1"), /* RTS */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* EMDIO */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -124,7 +138,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
SUNXI_FUNCTION(0x4, "uart1"), /* CTS */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXCTL / ETXEN */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -132,9 +147,11 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "uart7"), /* TX */
SUNXI_FUNCTION(0x4, "uart1"), /* DTR */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ETXCK */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* BCLK */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -142,9 +159,11 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "uart7"), /* RX */
SUNXI_FUNCTION(0x4, "uart1"), /* DSR */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GTXCK / ECRS */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* LRCK */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -152,9 +171,11 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "can"), /* TX */
SUNXI_FUNCTION(0x4, "uart1"), /* DCD */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GCLKIN / ECOL */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* DO */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -162,14 +183,18 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x3, "can"), /* RX */
SUNXI_FUNCTION(0x4, "uart1"), /* RING */
SUNXI_FUNCTION_VARIANT(0x5, "gmac", /* GNULL / ETXERR */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x6, "i2s1", /* DI */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
SUNXI_FUNCTION_VARIANT(0x3, "pll_lock_dbg",
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -177,11 +202,19 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
SUNXI_FUNCTION_VARIANT(0x2, "pwm", /* PWM0 */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_VARIANT(0x3, "pwm", /* PWM0 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ir0"), /* TX */
SUNXI_FUNCTION_VARIANT(0x2, "ir0", /* TX */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_VARIANT(0x3, "pwm", /* PWM1 */
PINCTRL_SUN8I_R40),
/*
* The SPDIF block is not referenced at all in the A10 user
* manual. However it is described in the code leaked and the
@ -205,7 +238,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* MCLK */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* MCLK */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
@ -213,7 +247,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* BCLK */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* BCLK */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
SUNXI_FUNCTION(0x0, "gpio_in"),
@ -221,7 +256,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* LRCK */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* LRCK */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
SUNXI_FUNCTION(0x0, "gpio_in"),
@ -229,7 +265,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO0 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO0 */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x3, "ac97")), /* DO */
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
SUNXI_FUNCTION(0x0, "gpio_in"),
@ -237,31 +274,41 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO1 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO1 */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x4, "pwm", /* PWM6 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO2 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO2 */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_VARIANT(0x4, "pwm", /* PWM7 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DO3 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DO3 */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x2, "i2s", /* DI */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x2, "i2s0", /* DI */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x3, "ac97"), /* DI */
/* Undocumented mux function on A10 - See SPDIF MCLK above */
SUNXI_FUNCTION(0x4, "spdif")), /* SPDIF IN */
SUNXI_FUNCTION_VARIANT(0x4, "spdif", /* SPDIF IN */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -299,16 +346,22 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */
SUNXI_FUNCTION_VARIANT(0x4, "pwm", /* PWM4 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */
SUNXI_FUNCTION_VARIANT(0x4, "pwm", /* PWM5 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 22),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "uart0"), /* TX */
SUNXI_FUNCTION(0x3, "ir1")), /* TX */
SUNXI_FUNCTION_VARIANT(0x3, "ir1", /* TX */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 23),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -341,7 +394,9 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
SUNXI_FUNCTION(0x2, "nand0"), /* NRE# */
SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* DS */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -375,19 +430,27 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* D4 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* D5 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* D6 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* D7 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -427,7 +490,9 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 24),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
SUNXI_FUNCTION_VARIANT(0x3, "mmc2", /* RST */
PINCTRL_SUN8I_R40)),
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
@ -728,14 +793,18 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
SUNXI_FUNCTION(0x5, "csi0"), /* D13 */
SUNXI_FUNCTION_VARIANT(0x6, "bist", /* RESULT0 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
SUNXI_FUNCTION(0x4, "uart4"), /* TX */
SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
SUNXI_FUNCTION(0x5, "csi0"), /* D14 */
SUNXI_FUNCTION_VARIANT(0x6, "bist", /* RESULT1 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -805,7 +874,9 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD2 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart5"), /* TX */
SUNXI_FUNCTION(0x5, "ms"), /* BS */
SUNXI_FUNCTION_VARIANT(0x5, "ms", /* BS */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 6), /* EINT6 */
SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
@ -815,7 +886,9 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD3 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION(0x4, "uart5"), /* RX */
SUNXI_FUNCTION(0x5, "ms"), /* CLK */
SUNXI_FUNCTION_VARIANT(0x5, "ms", /* CLK */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 7), /* EINT7 */
SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
@ -825,9 +898,12 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD4 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD3 */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
SUNXI_FUNCTION(0x5, "ms"), /* D0 */
SUNXI_FUNCTION_VARIANT(0x5, "ms", /* D0 */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 8), /* EINT8 */
SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
@ -837,9 +913,12 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD5 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD2 */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
SUNXI_FUNCTION(0x5, "ms"), /* D1 */
SUNXI_FUNCTION_VARIANT(0x5, "ms", /* D1 */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 9), /* EINT9 */
SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
@ -849,9 +928,12 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD6 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD1 */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
SUNXI_FUNCTION(0x5, "ms"), /* D2 */
SUNXI_FUNCTION_VARIANT(0x5, "ms", /* D2 */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 10), /* EINT10 */
SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
@ -861,9 +943,12 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD7 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXD0 */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
SUNXI_FUNCTION(0x5, "ms"), /* D3 */
SUNXI_FUNCTION_VARIANT(0x5, "ms", /* D3 */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_IRQ(0x6, 11), /* EINT11 */
SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
@ -892,7 +977,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD10 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD3 */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
SUNXI_FUNCTION_IRQ(0x6, 14), /* EINT14 */
@ -904,7 +990,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD11 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD2 */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
SUNXI_FUNCTION_IRQ(0x6, 15), /* EINT15 */
@ -916,7 +1003,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD12 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD1 */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
SUNXI_FUNCTION(0x5, "sim"), /* DET */
SUNXI_FUNCTION_IRQ(0x6, 16), /* EINT16 */
@ -928,7 +1016,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD13 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXD0 */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
SUNXI_FUNCTION_IRQ(0x6, 17), /* EINT17 */
@ -940,7 +1029,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD14 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXCK */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
SUNXI_FUNCTION(0x5, "sim"), /* SCK */
SUNXI_FUNCTION_IRQ(0x6, 18), /* EINT18 */
@ -952,7 +1042,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAD15 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXERR */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
SUNXI_FUNCTION(0x5, "sim"), /* SDA */
SUNXI_FUNCTION_IRQ(0x6, 19), /* EINT19 */
@ -964,7 +1055,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAOE */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ERXDV */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "can"), /* TX */
SUNXI_FUNCTION_IRQ(0x6, 20), /* EINT20 */
SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
@ -975,7 +1067,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATADREQ */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* EMDC */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "can"), /* RX */
SUNXI_FUNCTION_IRQ(0x6, 21), /* EINT21 */
SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
@ -986,7 +1079,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATADACK */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* EMDIO */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
@ -997,7 +1091,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATACS0 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXEN */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
@ -1008,7 +1103,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATACS1 */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXCK */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
@ -1019,7 +1115,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIORDY */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ECRS */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
@ -1030,7 +1127,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIOR */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ECOL */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
@ -1041,7 +1139,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION_VARIANT(0x3, "pata", /* ATAIOW */
PINCTRL_SUN4I_A10),
SUNXI_FUNCTION_VARIANT(0x3, "emac", /* ETXERR */
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
@ -1050,23 +1149,27 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SCK */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SDA */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION_VARIANT(0x3, "i2c4", /* SCK */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "pwm"), /* PWM1 */
SUNXI_FUNCTION_VARIANT(0x3, "i2c3", /* SDA */
PINCTRL_SUN7I_A20)),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
@ -1109,7 +1212,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
SUNXI_FUNCTION(0x3, "uart6"), /* TX */
SUNXI_FUNCTION_VARIANT(0x4, "clk_out_a",
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_IRQ(0x6, 24)), /* EINT24 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
SUNXI_FUNCTION(0x0, "gpio_in"),
@ -1117,7 +1221,8 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
SUNXI_FUNCTION(0x3, "uart6"), /* RX */
SUNXI_FUNCTION_VARIANT(0x4, "clk_out_b",
PINCTRL_SUN7I_A20),
PINCTRL_SUN7I_A20 |
PINCTRL_SUN8I_R40),
SUNXI_FUNCTION_IRQ(0x6, 25)), /* EINT25 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
SUNXI_FUNCTION(0x0, "gpio_in"),
@ -1162,13 +1267,21 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
SUNXI_FUNCTION(0x3, "uart7"), /* TX */
SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
SUNXI_FUNCTION_VARIANT(0x4, "hdmi", /* HSCL */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_VARIANT(0x6, "pwm", /* PWM2 */
PINCTRL_SUN8I_R40)),
SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 21),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
SUNXI_FUNCTION(0x3, "uart7"), /* RX */
SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
SUNXI_FUNCTION_VARIANT(0x4, "hdmi", /* HSDA */
PINCTRL_SUN4I_A10 |
PINCTRL_SUN7I_A20),
SUNXI_FUNCTION_VARIANT(0x6, "pwm", /* PWM3 */
PINCTRL_SUN8I_R40)),
};
static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
@ -1195,6 +1308,10 @@ static const struct of_device_id sun4i_a10_pinctrl_match[] = {
.compatible = "allwinner,sun7i-a20-pinctrl",
.data = (void *)PINCTRL_SUN7I_A20
},
{
.compatible = "allwinner,sun8i-r40-pinctrl",
.data = (void *)PINCTRL_SUN8I_R40
},
{}
};

22
drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
View file

@ -19,6 +19,7 @@
#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/pinctrl/pinctrl.h>
#include "pinctrl-sunxi.h"
@ -530,17 +531,36 @@ static const struct sunxi_desc_pin sun50i_h5_pins[] = {
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */
};
static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = {
static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data_broken = {
.pins = sun50i_h5_pins,
.npins = ARRAY_SIZE(sun50i_h5_pins),
.irq_banks = 2,
.irq_read_needs_mux = true
};
static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = {
.pins = sun50i_h5_pins,
.npins = ARRAY_SIZE(sun50i_h5_pins),
.irq_banks = 3,
.irq_read_needs_mux = true
};
static int sun50i_h5_pinctrl_probe(struct platform_device *pdev)
{
switch (of_irq_count(pdev->dev.of_node)) {
case 2:
dev_warn(&pdev->dev,
"Your device tree's pinctrl node is broken, which has no IRQ of PG bank routed.\n");
dev_warn(&pdev->dev,
"Please update the device tree, otherwise PG bank IRQ won't work.\n");
return sunxi_pinctrl_init(pdev,
&sun50i_h5_pinctrl_data_broken);
case 3:
return sunxi_pinctrl_init(pdev,
&sun50i_h5_pinctrl_data);
default:
return -EINVAL;
}
}
static const struct of_device_id sun50i_h5_pinctrl_match[] = {

6
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
View file

@ -25,12 +25,12 @@ static const struct sunxi_desc_pin sun6i_a31_r_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_twi"), /* SCK */
SUNXI_FUNCTION(0x2, "s_i2c"), /* SCK */
SUNXI_FUNCTION(0x3, "s_p2wi")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_twi"), /* SDA */
SUNXI_FUNCTION(0x2, "s_i2c"), /* SDA */
SUNXI_FUNCTION(0x3, "s_p2wi")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
@ -113,7 +113,7 @@ static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev)
struct reset_control *rstc;
int ret;
rstc = devm_reset_control_get(&pdev->dev, NULL);
rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(rstc)) {
dev_err(&pdev->dev, "Reset controller missing\n");
return PTR_ERR(rstc);

6
drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
View file

@ -29,13 +29,13 @@ static const struct sunxi_desc_pin sun8i_a23_r_pins[] = {
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_rsb"), /* SCK */
SUNXI_FUNCTION(0x3, "s_twi"), /* SCK */
SUNXI_FUNCTION(0x3, "s_i2c"), /* SCK */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 0)), /* PL_EINT0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
SUNXI_FUNCTION(0x2, "s_rsb"), /* SDA */
SUNXI_FUNCTION(0x3, "s_twi"), /* SDA */
SUNXI_FUNCTION(0x3, "s_i2c"), /* SDA */
SUNXI_FUNCTION_IRQ_BANK(0x4, 0, 1)), /* PL_EINT1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
SUNXI_FUNCTION(0x0, "gpio_in"),
@ -100,7 +100,7 @@ static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev)
struct reset_control *rstc;
int ret;
rstc = devm_reset_control_get(&pdev->dev, NULL);
rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
if (IS_ERR(rstc)) {
dev_err(&pdev->dev, "Reset controller missing\n");
return PTR_ERR(rstc);

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