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drm/amd/pm: add some basic functions to support umd P-state function for vangogh.
This patch is to add some basic functions to support umd P-state function for vangogh. Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Xiaojian Du
Alex Deucher
parent
16a0fd2a15
commit
d0e4e112a9
2 changed files with 232 additions and 1 deletions
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@ -556,6 +556,235 @@ static int vangogh_print_fine_grain_clk(struct smu_context *smu,
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return size;
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}
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static int vangogh_get_profiling_clk_mask(struct smu_context *smu,
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enum amd_dpm_forced_level level,
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uint32_t *vclk_mask,
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uint32_t *dclk_mask,
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uint32_t *mclk_mask,
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uint32_t *fclk_mask,
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uint32_t *soc_mask)
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{
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DpmClocks_t *clk_table = smu->smu_table.clocks_table;
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if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
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if (soc_mask)
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*soc_mask = 0;
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} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
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if (mclk_mask)
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/* mclk levels are in reverse order */
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*mclk_mask = clk_table->NumDfPstatesEnabled - 1;
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/* fclk levels are in reverse order */
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if (fclk_mask)
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*fclk_mask = clk_table->NumDfPstatesEnabled - 1;
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} else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
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if (mclk_mask)
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/* mclk levels are in reverse order */
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*mclk_mask = 0;
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/* fclk levels are in reverse order */
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if (fclk_mask)
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*fclk_mask = 0;
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if (soc_mask)
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*soc_mask = clk_table->NumSocClkLevelsEnabled - 1;
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}
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return 0;
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}
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bool vangogh_clk_dpm_is_enabled(struct smu_context *smu,
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enum smu_clk_type clk_type)
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{
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enum smu_feature_mask feature_id = 0;
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switch (clk_type) {
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case SMU_MCLK:
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case SMU_UCLK:
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case SMU_FCLK:
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feature_id = SMU_FEATURE_DPM_FCLK_BIT;
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break;
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case SMU_GFXCLK:
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case SMU_SCLK:
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feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
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break;
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case SMU_SOCCLK:
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feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
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break;
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case SMU_VCLK:
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case SMU_DCLK:
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feature_id = SMU_FEATURE_VCN_DPM_BIT;
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break;
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default:
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return true;
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}
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if (!smu_cmn_feature_is_enabled(smu, feature_id))
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return false;
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return true;
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}
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static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu,
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enum smu_clk_type clk_type,
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uint32_t *min,
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uint32_t *max)
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{
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int ret = 0;
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uint32_t soc_mask;
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uint32_t vclk_mask;
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uint32_t dclk_mask;
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uint32_t mclk_mask;
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uint32_t fclk_mask;
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uint32_t clock_limit;
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if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) {
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switch (clk_type) {
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case SMU_MCLK:
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case SMU_UCLK:
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clock_limit = smu->smu_table.boot_values.uclk;
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break;
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case SMU_FCLK:
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clock_limit = smu->smu_table.boot_values.fclk;
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break;
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case SMU_GFXCLK:
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case SMU_SCLK:
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clock_limit = smu->smu_table.boot_values.gfxclk;
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break;
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case SMU_SOCCLK:
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clock_limit = smu->smu_table.boot_values.socclk;
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break;
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case SMU_VCLK:
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clock_limit = smu->smu_table.boot_values.vclk;
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break;
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case SMU_DCLK:
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clock_limit = smu->smu_table.boot_values.dclk;
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break;
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default:
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clock_limit = 0;
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break;
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}
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/* clock in Mhz unit */
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if (min)
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*min = clock_limit / 100;
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if (max)
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*max = clock_limit / 100;
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return 0;
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}
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if (max) {
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ret = vangogh_get_profiling_clk_mask(smu,
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AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
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&vclk_mask,
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&dclk_mask,
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&mclk_mask,
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&fclk_mask,
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&soc_mask);
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if (ret)
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goto failed;
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switch (clk_type) {
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case SMU_UCLK:
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case SMU_MCLK:
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ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
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if (ret)
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goto failed;
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break;
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case SMU_SOCCLK:
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ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
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if (ret)
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goto failed;
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break;
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case SMU_FCLK:
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ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max);
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if (ret)
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goto failed;
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break;
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case SMU_VCLK:
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ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max);
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if (ret)
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goto failed;
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break;
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case SMU_DCLK:
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ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max);
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if (ret)
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goto failed;
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break;
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default:
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ret = -EINVAL;
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goto failed;
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}
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}
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if (min) {
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switch (clk_type) {
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case SMU_UCLK:
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case SMU_MCLK:
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ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min);
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if (ret)
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goto failed;
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break;
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case SMU_SOCCLK:
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ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min);
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if (ret)
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goto failed;
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break;
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case SMU_FCLK:
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ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min);
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if (ret)
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goto failed;
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break;
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case SMU_VCLK:
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ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min);
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if (ret)
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goto failed;
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break;
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case SMU_DCLK:
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ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min);
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if (ret)
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goto failed;
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break;
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default:
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ret = -EINVAL;
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goto failed;
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}
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}
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failed:
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return ret;
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}
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static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
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{
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int workload_type, ret;
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uint32_t profile_mode = input[size];
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if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
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dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
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return -EINVAL;
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}
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/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
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workload_type = smu_cmn_to_asic_specific_index(smu,
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CMN2ASIC_MAPPING_WORKLOAD,
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profile_mode);
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if (workload_type < 0) {
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dev_err_once(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n",
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profile_mode);
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return -EINVAL;
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}
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
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1 << workload_type,
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NULL);
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if (ret) {
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dev_err_once(smu->adev->dev, "Fail to set workload type %d\n",
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workload_type);
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return ret;
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}
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smu->power_profile_mode = profile_mode;
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return 0;
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}
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static int vangogh_read_sensor(struct smu_context *smu,
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enum amd_pp_sensors sensor,
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void *data, uint32_t *size)
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@ -945,6 +1174,8 @@ static const struct pptable_funcs vangogh_ppt_funcs = {
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.set_default_dpm_table = vangogh_set_default_dpm_tables,
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.set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,
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.system_features_control = vangogh_system_features_control,
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.feature_is_enabled = smu_cmn_feature_is_enabled,
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.set_power_profile_mode = vangogh_set_power_profile_mode,
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.get_dpm_clock_table = vangogh_get_dpm_clock_table,
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.post_init = vangogh_post_smu_init,
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};
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@ -29,7 +29,7 @@ extern void vangogh_set_ppt_funcs(struct smu_context *smu);
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/* UMD PState Vangogh Msg Parameters in MHz */
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#define VANGOGH_UMD_PSTATE_GFXCLK 700
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#define VANGOGH_UMD_PSTATE_SOCCLK 678
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#define VANGOGH_UMD_PSTATE_SOCCLK 600
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#define VANGOGH_UMD_PSTATE_FCLK 800
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/* RLC Power Status */
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