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drm/i915: add single combo phy init/unit functions

Browse source 
Work on the principle that files should prefer not to expose platform
specific functions.

v2, v3: Rebase

Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190502145234.7002-1-jani.nikula@intel.com
This commit is contained in:
Jani Nikula 2019-05-02 17:52:34 +03:00
parent 263a8cf1ff
commit c9fd91668d
3 changed files with 27 additions and 13 deletions
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24
drivers/gpu/drm/i915/intel_combo_phy.c
View file

@ -148,7 +148,7 @@ static bool cnl_combo_phy_verify_state(struct drm_i915_private *dev_priv)
return ret; return ret;
} }
void cnl_combo_phys_init(struct drm_i915_private *dev_priv) static void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
{ {
u32 val; u32 val;
@ -168,7 +168,7 @@ void cnl_combo_phys_init(struct drm_i915_private *dev_priv)
I915_WRITE(CNL_PORT_CL1CM_DW5, val); I915_WRITE(CNL_PORT_CL1CM_DW5, val);
} }
void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv) static void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv)
{ {
u32 val; u32 val;
@ -256,7 +256,7 @@ void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
I915_WRITE(ICL_PORT_CL_DW10(port), val); I915_WRITE(ICL_PORT_CL_DW10(port), val);
} }
void icl_combo_phys_init(struct drm_i915_private *dev_priv) static void icl_combo_phys_init(struct drm_i915_private *dev_priv)
{ {
enum port port; enum port port;
@ -285,7 +285,7 @@ void icl_combo_phys_init(struct drm_i915_private *dev_priv)
} }
} }
void icl_combo_phys_uninit(struct drm_i915_private *dev_priv) static void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
{ {
enum port port; enum port port;
@ -306,3 +306,19 @@ void icl_combo_phys_uninit(struct drm_i915_private *dev_priv)
I915_WRITE(ICL_PORT_COMP_DW0(port), val); I915_WRITE(ICL_PORT_COMP_DW0(port), val);
} }
} }
void intel_combo_phy_init(struct drm_i915_private *i915)
{
if (INTEL_GEN(i915) >= 11)
icl_combo_phys_init(i915);
else if (IS_CANNONLAKE(i915))
cnl_combo_phys_init(i915);
}
void intel_combo_phy_uninit(struct drm_i915_private *i915)
{
if (INTEL_GEN(i915) >= 11)
icl_combo_phys_uninit(i915);
else if (IS_CANNONLAKE(i915))
cnl_combo_phys_uninit(i915);
}

6
drivers/gpu/drm/i915/intel_combo_phy.h
View file

@ -11,10 +11,8 @@
struct drm_i915_private; struct drm_i915_private;
void icl_combo_phys_init(struct drm_i915_private *dev_priv); void intel_combo_phy_init(struct drm_i915_private *dev_priv);
void icl_combo_phys_uninit(struct drm_i915_private *dev_priv); void intel_combo_phy_uninit(struct drm_i915_private *dev_priv);
void cnl_combo_phys_init(struct drm_i915_private *dev_priv);
void cnl_combo_phys_uninit(struct drm_i915_private *dev_priv);
void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, void intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv,
enum port port, bool is_dsi, enum port port, bool is_dsi,
int lane_count, bool lane_reversal); int lane_count, bool lane_reversal);

10
drivers/gpu/drm/i915/intel_runtime_pm.c
View file

@ -1140,7 +1140,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
* PHY's HW context for port B is lost after DC transitions, * PHY's HW context for port B is lost after DC transitions,
* so we need to restore it manually. * so we need to restore it manually.
*/ */
icl_combo_phys_init(dev_priv); intel_combo_phy_init(dev_priv);
} }
static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
@ -3779,7 +3779,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
/* 2-3. */ /* 2-3. */
cnl_combo_phys_init(dev_priv); intel_combo_phy_init(dev_priv);
/* /*
* 4. Enable Power Well 1 (PG1). * 4. Enable Power Well 1 (PG1).
@ -3828,7 +3828,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
usleep_range(10, 30); /* 10 us delay per Bspec */ usleep_range(10, 30); /* 10 us delay per Bspec */
/* 5. */ /* 5. */
cnl_combo_phys_uninit(dev_priv); intel_combo_phy_uninit(dev_priv);
} }
void icl_display_core_init(struct drm_i915_private *dev_priv, void icl_display_core_init(struct drm_i915_private *dev_priv,
@ -3843,7 +3843,7 @@ void icl_display_core_init(struct drm_i915_private *dev_priv,
intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
/* 2. Initialize all combo phys */ /* 2. Initialize all combo phys */
icl_combo_phys_init(dev_priv); intel_combo_phy_init(dev_priv);
/* /*
* 3. Enable Power Well 1 (PG1). * 3. Enable Power Well 1 (PG1).
@ -3893,7 +3893,7 @@ void icl_display_core_uninit(struct drm_i915_private *dev_priv)
mutex_unlock(&power_domains->lock); mutex_unlock(&power_domains->lock);
/* 5. */ /* 5. */
icl_combo_phys_uninit(dev_priv); intel_combo_phy_uninit(dev_priv);
} }
static void chv_phy_control_init(struct drm_i915_private *dev_priv) static void chv_phy_control_init(struct drm_i915_private *dev_priv)