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drm/amdgpu/gfx9: add rlc bo init/fini
setup the save and restore buffers used for gfx powergating. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang
Alex Deucher
parent
e999e6e945
commit
c9719c69ac
1 changed files with 209 additions and 27 deletions
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@ -529,6 +529,209 @@ out:
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return err;
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}
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static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
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{
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u32 count = 0;
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const struct cs_section_def *sect = NULL;
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const struct cs_extent_def *ext = NULL;
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/* begin clear state */
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count += 2;
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/* context control state */
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count += 3;
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for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
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for (ext = sect->section; ext->extent != NULL; ++ext) {
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if (sect->id == SECT_CONTEXT)
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count += 2 + ext->reg_count;
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else
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return 0;
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}
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}
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/* end clear state */
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count += 2;
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/* clear state */
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count += 2;
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return count;
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}
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static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
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volatile u32 *buffer)
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{
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u32 count = 0, i;
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const struct cs_section_def *sect = NULL;
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const struct cs_extent_def *ext = NULL;
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if (adev->gfx.rlc.cs_data == NULL)
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return;
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if (buffer == NULL)
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return;
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buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
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buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
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buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
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buffer[count++] = cpu_to_le32(0x80000000);
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buffer[count++] = cpu_to_le32(0x80000000);
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for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
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for (ext = sect->section; ext->extent != NULL; ++ext) {
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if (sect->id == SECT_CONTEXT) {
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buffer[count++] =
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cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
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buffer[count++] = cpu_to_le32(ext->reg_index -
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PACKET3_SET_CONTEXT_REG_START);
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for (i = 0; i < ext->reg_count; i++)
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buffer[count++] = cpu_to_le32(ext->extent[i]);
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} else {
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return;
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}
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}
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}
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buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
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buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
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buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
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buffer[count++] = cpu_to_le32(0);
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}
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static void rv_init_cp_jump_table(struct amdgpu_device *adev)
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{
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const __le32 *fw_data;
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volatile u32 *dst_ptr;
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int me, i, max_me = 5;
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u32 bo_offset = 0;
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u32 table_offset, table_size;
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/* write the cp table buffer */
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dst_ptr = adev->gfx.rlc.cp_table_ptr;
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for (me = 0; me < max_me; me++) {
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if (me == 0) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.ce_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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} else if (me == 1) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.pfp_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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} else if (me == 2) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.me_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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} else if (me == 3) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.mec_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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} else if (me == 4) {
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const struct gfx_firmware_header_v1_0 *hdr =
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(const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
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fw_data = (const __le32 *)
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(adev->gfx.mec2_fw->data +
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le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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table_offset = le32_to_cpu(hdr->jt_offset);
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table_size = le32_to_cpu(hdr->jt_size);
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}
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for (i = 0; i < table_size; i ++) {
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dst_ptr[bo_offset + i] =
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cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
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}
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bo_offset += table_size;
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}
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}
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static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
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{
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/* clear state block */
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amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
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&adev->gfx.rlc.clear_state_gpu_addr,
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(void **)&adev->gfx.rlc.cs_ptr);
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/* jump table block */
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amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
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&adev->gfx.rlc.cp_table_gpu_addr,
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(void **)&adev->gfx.rlc.cp_table_ptr);
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}
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static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
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{
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volatile u32 *dst_ptr;
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u32 dws;
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const struct cs_section_def *cs_data;
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int r;
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adev->gfx.rlc.cs_data = gfx9_cs_data;
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cs_data = adev->gfx.rlc.cs_data;
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if (cs_data) {
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/* clear state block */
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adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
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if (adev->gfx.rlc.clear_state_obj == NULL) {
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r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&adev->gfx.rlc.clear_state_obj,
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&adev->gfx.rlc.clear_state_gpu_addr,
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(void **)&adev->gfx.rlc.cs_ptr);
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if (r) {
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dev_err(adev->dev,
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"(%d) failed to create rlc csb bo\n", r);
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gfx_v9_0_rlc_fini(adev);
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return r;
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}
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}
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/* set up the cs buffer */
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dst_ptr = adev->gfx.rlc.cs_ptr;
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gfx_v9_0_get_csb_buffer(adev, dst_ptr);
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amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
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amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
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}
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if (adev->asic_type == CHIP_RAVEN) {
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/* TODO: double check the cp_table_size for RV */
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adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
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if (adev->gfx.rlc.cp_table_obj == NULL) {
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r = amdgpu_bo_create_kernel(adev, adev->gfx.rlc.cp_table_size,
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PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
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&adev->gfx.rlc.cp_table_obj,
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&adev->gfx.rlc.cp_table_gpu_addr,
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(void **)&adev->gfx.rlc.cp_table_ptr);
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if (r) {
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dev_err(adev->dev,
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"(%d) failed to create cp table bo\n", r);
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gfx_v9_0_rlc_fini(adev);
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return r;
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}
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}
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rv_init_cp_jump_table(adev);
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amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
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amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
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}
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return 0;
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}
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static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
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{
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int r;
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@ -1152,6 +1355,12 @@ static int gfx_v9_0_sw_init(void *handle)
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return r;
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}
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r = gfx_v9_0_rlc_init(adev);
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if (r) {
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DRM_ERROR("Failed to init rlc BOs!\n");
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return r;
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}
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r = gfx_v9_0_mec_init(adev);
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if (r) {
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DRM_ERROR("Failed to init MEC BOs!\n");
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@ -1646,33 +1855,6 @@ static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
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return 0;
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}
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static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
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{
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u32 count = 0;
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const struct cs_section_def *sect = NULL;
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const struct cs_extent_def *ext = NULL;
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/* begin clear state */
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count += 2;
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/* context control state */
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count += 3;
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for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
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for (ext = sect->section; ext->extent != NULL; ++ext) {
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if (sect->id == SECT_CONTEXT)
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count += 2 + ext->reg_count;
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else
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return 0;
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}
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}
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/* end clear state */
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count += 2;
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/* clear state */
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count += 2;
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return count;
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}
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static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
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{
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struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
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