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drm/amdgpu: enable xgmi support for sienna cichlid
set xgmi support flag suring nv ip init sequence Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -446,6 +446,9 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
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adev->nbio.funcs = &nbio_v2_3_funcs;
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adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
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if (adev->asic_type == CHIP_SIENNA_CICHLID)
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adev->gmc.xgmi.supported = true;
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/* Set IP register base before any HW register access */
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r = nv_reg_base_init(adev);
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if (r)
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