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ARM: socfpga: dts: Correct the parent clock for l3_sp_clk and dbg_clk

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The l3_sp_clk's parent should be the l3_mp_clk. This will account for
the extra divider that is present for the l3_mp_clk.

The dbg_clk's parent should be the dbg_at_clk. This will account for
the extra divider that is present for the dbg_at_clk.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
This commit is contained in:
Dinh Nguyen 2013-11-20 09:39:17 -06:00
parent 57c0f8c9c4
commit c5dab6e2c1
1 changed files with 2 additions and 2 deletions
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4
arch/arm/boot/dts/socfpga.dtsi
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@ -318,7 +318,7 @@
l3_sp_clk: l3_sp_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&mainclk>;
clocks = <&l3_mp_clk>;
div-reg = <0x64 2 2>;
};
@ -349,7 +349,7 @@
dbg_clk: dbg_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&dbg_base_clk>;
clocks = <&dbg_at_clk>;
div-reg = <0x68 2 2>;
clk-gate = <0x60 5>;
};