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drm/amd/powerplay: fit the SOC clock also to the new performance level

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The SOC clock needs also to fit the new performance level.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2019-01-21 14:05:37 +08:00 • committed by Alex Deucher
parent 921935dc64
commit c3e5bb04cc
1 changed files with 37 additions and 0 deletions
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37
drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
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@ -2170,6 +2170,12 @@ static int vega20_force_dpm_highest(struct pp_hwmgr *hwmgr)
data->dpm_table.mem_table.dpm_state.soft_max_level = data->dpm_table.mem_table.dpm_state.soft_max_level =
data->dpm_table.mem_table.dpm_levels[soft_level].value; data->dpm_table.mem_table.dpm_levels[soft_level].value;
soft_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
data->dpm_table.soc_table.dpm_state.soft_min_level =
data->dpm_table.soc_table.dpm_state.soft_max_level =
data->dpm_table.soc_table.dpm_levels[soft_level].value;
ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF); ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE(!ret,
"Failed to upload boot level to highest!", "Failed to upload boot level to highest!",
@ -2202,6 +2208,12 @@ static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
data->dpm_table.mem_table.dpm_state.soft_max_level = data->dpm_table.mem_table.dpm_state.soft_max_level =
data->dpm_table.mem_table.dpm_levels[soft_level].value; data->dpm_table.mem_table.dpm_levels[soft_level].value;
soft_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
data->dpm_table.soc_table.dpm_state.soft_min_level =
data->dpm_table.soc_table.dpm_state.soft_max_level =
data->dpm_table.soc_table.dpm_levels[soft_level].value;
ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF); ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE(!ret,
"Failed to upload boot level to highest!", "Failed to upload boot level to highest!",
@ -2218,8 +2230,32 @@ static int vega20_force_dpm_lowest(struct pp_hwmgr *hwmgr)
static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr) static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
{ {
struct vega20_hwmgr *data =
(struct vega20_hwmgr *)(hwmgr->backend);
uint32_t soft_min_level, soft_max_level;
int ret = 0; int ret = 0;
soft_min_level = vega20_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
soft_max_level = vega20_find_highest_dpm_level(&(data->dpm_table.gfx_table));
data->dpm_table.gfx_table.dpm_state.soft_min_level =
data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
data->dpm_table.gfx_table.dpm_state.soft_max_level =
data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
soft_min_level = vega20_find_lowest_dpm_level(&(data->dpm_table.mem_table));
soft_max_level = vega20_find_highest_dpm_level(&(data->dpm_table.mem_table));
data->dpm_table.mem_table.dpm_state.soft_min_level =
data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
data->dpm_table.mem_table.dpm_state.soft_max_level =
data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
soft_min_level = vega20_find_lowest_dpm_level(&(data->dpm_table.soc_table));
soft_max_level = vega20_find_highest_dpm_level(&(data->dpm_table.soc_table));
data->dpm_table.soc_table.dpm_state.soft_min_level =
data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
data->dpm_table.soc_table.dpm_state.soft_max_level =
data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF); ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
PP_ASSERT_WITH_CODE(!ret, PP_ASSERT_WITH_CODE(!ret,
"Failed to upload DPM Bootup Levels!", "Failed to upload DPM Bootup Levels!",
@ -2457,6 +2493,7 @@ static int vega20_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
return ret; return ret;
vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask); vega20_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask); vega20_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask);
break; break;
case AMD_DPM_FORCED_LEVEL_MANUAL: case AMD_DPM_FORCED_LEVEL_MANUAL: