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drm/msm: sync generated headers

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We haven't sync'd for a while.. pull in updates to get definitions for
some fields in pkt7 payloads.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Rob Clark 2020-07-07 13:34:59 -07:00
parent 51dd427192
commit c28c82e9db
18 changed files with 5889 additions and 1189 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1100
drivers/gpu/drm/msm/adreno/a2xx.xml.h
View file

File diff suppressed because it is too large Load diff

100
drivers/gpu/drm/msm/adreno/a3xx.xml.h
View file

@ -8,19 +8,21 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
Copyright (C) 2013-2018 by the following authors:
Copyright (C) 2013-2020 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@ -48,7 +50,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
enum a3xx_tile_mode {
LINEAR = 0,
TILE_4X4 = 1,
TILE_32X32 = 2,
TILE_4X2 = 3,
};
enum a3xx_state_block_id {
@ -123,6 +127,7 @@ enum a3xx_vtx_fmt {
VFMT_2_10_10_10_UNORM = 61,
VFMT_2_10_10_10_SINT = 62,
VFMT_2_10_10_10_SNORM = 63,
VFMT_NONE = 255,
};
enum a3xx_tex_fmt {
@ -206,15 +211,7 @@ enum a3xx_tex_fmt {
TFMT_ETC2_RGBA8 = 116,
TFMT_ETC2_RGB8A1 = 117,
TFMT_ETC2_RGB8 = 118,
};
enum a3xx_tex_fetchsize {
TFETCH_DISABLE = 0,
TFETCH_1_BYTE = 1,
TFETCH_2_BYTE = 2,
TFETCH_4_BYTE = 3,
TFETCH_8_BYTE = 4,
TFETCH_16_BYTE = 5,
TFMT_NONE = 255,
};
enum a3xx_color_fmt {
@ -228,8 +225,8 @@ enum a3xx_color_fmt {
RB_R8G8B8A8_SINT = 11,
RB_R8G8_UNORM = 12,
RB_R8G8_SNORM = 13,
RB_R8_UINT = 14,
RB_R8_SINT = 15,
RB_R8G8_UINT = 14,
RB_R8G8_SINT = 15,
RB_R10G10B10A2_UNORM = 16,
RB_A2R10G10B10_UNORM = 17,
RB_R10G10B10A2_UINT = 18,
@ -261,6 +258,7 @@ enum a3xx_color_fmt {
RB_R32_UINT = 56,
RB_R32G32_UINT = 57,
RB_R32G32B32A32_UINT = 59,
RB_NONE = 255,
};
enum a3xx_cp_perfcounter_select {
@ -932,6 +930,9 @@ static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460
#define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040
#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000
#define A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTER 0x00002000
#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTROID 0x00004000
#define A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTROID 0x00008000
#define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000
#define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000
#define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000
@ -1170,10 +1171,12 @@ static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)
}
#define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000
#define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000
#define A3XX_RB_RENDER_CONTROL_XCOORD 0x00004000
#define A3XX_RB_RENDER_CONTROL_YCOORD 0x00008000
#define A3XX_RB_RENDER_CONTROL_ZCOORD 0x00010000
#define A3XX_RB_RENDER_CONTROL_WCOORD 0x00020000
#define A3XX_RB_RENDER_CONTROL_COORD_MASK__MASK 0x0003c000
#define A3XX_RB_RENDER_CONTROL_COORD_MASK__SHIFT 14
static inline uint32_t A3XX_RB_RENDER_CONTROL_COORD_MASK(uint32_t val)
{
return ((val) << A3XX_RB_RENDER_CONTROL_COORD_MASK__SHIFT) & A3XX_RB_RENDER_CONTROL_COORD_MASK__MASK;
}
#define A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE 0x00080000
#define A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE 0x00100000
#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000
@ -1755,11 +1758,29 @@ static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
}
#define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203
#define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
#define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__MASK 0x000000ff
#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__SHIFT 0
static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID(uint32_t val)
{
return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK;
return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__MASK;
}
#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__MASK 0x0000ff00
#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__SHIFT 8
static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID(uint32_t val)
{
return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__MASK;
}
#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__MASK 0x00ff0000
#define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__SHIFT 16
static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID(uint32_t val)
{
return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__MASK;
}
#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__MASK 0xff000000
#define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__SHIFT 24
static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID(uint32_t val)
{
return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__MASK;
}
#define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204
@ -1944,8 +1965,6 @@ static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
#define REG_A3XX_VFD_INDEX_OFFSET 0x00002245
#define REG_A3XX_VFD_INDEX_OFFSET 0x00002245
static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; }
static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; }
@ -3107,7 +3126,12 @@ static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val)
}
#define REG_A3XX_TEX_CONST_0 0x00000000
#define A3XX_TEX_CONST_0_TILED 0x00000001
#define A3XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
#define A3XX_TEX_CONST_0_TILE_MODE__SHIFT 0
static inline uint32_t A3XX_TEX_CONST_0_TILE_MODE(enum a3xx_tile_mode val)
{
return ((val) << A3XX_TEX_CONST_0_TILE_MODE__SHIFT) & A3XX_TEX_CONST_0_TILE_MODE__MASK;
}
#define A3XX_TEX_CONST_0_SRGB 0x00000004
#define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
#define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4
@ -3172,11 +3196,11 @@ static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val)
{
return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK;
}
#define A3XX_TEX_CONST_1_FETCHSIZE__MASK 0xf0000000
#define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT 28
static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val)
#define A3XX_TEX_CONST_1_PITCHALIGN__MASK 0xf0000000
#define A3XX_TEX_CONST_1_PITCHALIGN__SHIFT 28
static inline uint32_t A3XX_TEX_CONST_1_PITCHALIGN(uint32_t val)
{
return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK;
return ((val) << A3XX_TEX_CONST_1_PITCHALIGN__SHIFT) & A3XX_TEX_CONST_1_PITCHALIGN__MASK;
}
#define REG_A3XX_TEX_CONST_2 0x00000002

123
drivers/gpu/drm/msm/adreno/a4xx.xml.h
View file

@ -8,19 +8,21 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
Copyright (C) 2013-2018 by the following authors:
Copyright (C) 2013-2020 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@ -91,6 +93,7 @@ enum a4xx_color_fmt {
RB4_R32G32B32A32_FLOAT = 60,
RB4_R32G32B32A32_UINT = 61,
RB4_R32G32B32A32_SINT = 62,
RB4_NONE = 255,
};
enum a4xx_tile_mode {
@ -161,6 +164,7 @@ enum a4xx_vtx_fmt {
VFMT4_2_10_10_10_UNORM = 61,
VFMT4_2_10_10_10_SINT = 62,
VFMT4_2_10_10_10_SNORM = 63,
VFMT4_NONE = 255,
};
enum a4xx_tex_fmt {
@ -248,14 +252,7 @@ enum a4xx_tex_fmt {
TFMT4_ASTC_10x10 = 122,
TFMT4_ASTC_12x10 = 123,
TFMT4_ASTC_12x12 = 124,
};
enum a4xx_tex_fetchsize {
TFETCH4_1_BYTE = 0,
TFETCH4_2_BYTE = 1,
TFETCH4_4_BYTE = 2,
TFETCH4_8_BYTE = 3,
TFETCH4_16_BYTE = 4,
TFMT4_NONE = 255,
};
enum a4xx_depth_format {
@ -949,10 +946,12 @@ static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
}
#define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3
#define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001
#define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002
#define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004
#define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008
#define A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK 0x0000000f
#define A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT 0
static inline uint32_t A4XX_RB_RENDER_CONTROL2_COORD_MASK(uint32_t val)
{
return ((val) << A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT) & A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK;
}
#define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010
#define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020
#define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040
@ -963,7 +962,10 @@ static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
}
#define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800
#define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000
#define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_PIXEL 0x00001000
#define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_CENTROID 0x00002000
#define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_SAMPLE 0x00004000
#define A4XX_RB_RENDER_CONTROL2_SIZE 0x00008000
static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
@ -1877,10 +1879,6 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x
#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114
#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
#define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116
#define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117
@ -2061,8 +2059,6 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0)
#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a
#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
#define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
@ -2210,8 +2206,18 @@ static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
{
return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK;
}
#define A4XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
#define A4XX_CP_PROTECT_REG_TRAP_READ 0x40000000
#define A4XX_CP_PROTECT_REG_TRAP_WRITE__MASK 0x20000000
#define A4XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT 29
static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val)
{
return ((val) << A4XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A4XX_CP_PROTECT_REG_TRAP_WRITE__MASK;
}
#define A4XX_CP_PROTECT_REG_TRAP_READ__MASK 0x40000000
#define A4XX_CP_PROTECT_REG_TRAP_READ__SHIFT 30
static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_READ(uint32_t val)
{
return ((val) << A4XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A4XX_CP_PROTECT_REG_TRAP_READ__MASK;
}
#define REG_A4XX_CP_PROTECT_CTRL 0x00000250
@ -3151,8 +3157,9 @@ static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
#define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000
#define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
#define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003
#define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001
#define REG_A4XX_GRAS_CNTL 0x00002003
#define A4XX_GRAS_CNTL_IJ_PERSP 0x00000001
#define A4XX_GRAS_CNTL_IJ_LINEAR 0x00000002
#define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004
#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
@ -3524,14 +3531,44 @@ static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
}
#define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3
#define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
#define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
{
return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK;
return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
}
#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
{
return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
}
#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
{
return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
}
#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
{
return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
}
#define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4
#define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
#define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
{
return ((val) << A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
}
#define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
#define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
{
return ((val) << A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
}
#define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5
#define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
@ -4115,11 +4152,11 @@ static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
}
#define REG_A4XX_TEX_CONST_2 0x00000002
#define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
#define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val)
#define A4XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
#define A4XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
static inline uint32_t A4XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
{
return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK;
return ((val) << A4XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A4XX_TEX_CONST_2_PITCHALIGN__MASK;
}
#define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
#define A4XX_TEX_CONST_2_PITCH__SHIFT 9

401
drivers/gpu/drm/msm/adreno/a5xx.xml.h
View file

@ -8,19 +8,21 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/ubuntu/envytools/envytools/rnndb/./adreno.xml ( 501 bytes, from 2019-05-29 01:28:15)
- /home/ubuntu/envytools/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2019-05-29 01:28:15)
- /home/ubuntu/envytools/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-05-29 01:28:15)
- /home/ubuntu/envytools/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2019-05-29 01:28:15)
- /home/ubuntu/envytools/envytools/rnndb/adreno/adreno_pm4.xml ( 43155 bytes, from 2019-05-29 01:28:15)
- /home/ubuntu/envytools/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2019-05-29 01:28:15)
- /home/ubuntu/envytools/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2019-05-29 01:28:15)
- /home/ubuntu/envytools/envytools/rnndb/adreno/a5xx.xml ( 147291 bytes, from 2019-05-29 14:51:41)
- /home/ubuntu/envytools/envytools/rnndb/adreno/a6xx.xml ( 148461 bytes, from 2019-05-29 01:28:15)
- /home/ubuntu/envytools/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2019-05-29 01:28:15)
- /home/ubuntu/envytools/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2019-05-29 01:28:15)
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
Copyright (C) 2013-2019 by the following authors:
Copyright (C) 2013-2020 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@ -91,6 +93,7 @@ enum a5xx_color_fmt {
RB5_R32G32B32A32_FLOAT = 130,
RB5_R32G32B32A32_UINT = 131,
RB5_R32G32B32A32_SINT = 132,
RB5_NONE = 255,
};
enum a5xx_tile_mode {
@ -165,6 +168,7 @@ enum a5xx_vtx_fmt {
VFMT5_32_32_32_32_UINT = 131,
VFMT5_32_32_32_32_SINT = 132,
VFMT5_32_32_32_32_FIXED = 133,
VFMT5_NONE = 255,
};
enum a5xx_tex_fmt {
@ -250,14 +254,7 @@ enum a5xx_tex_fmt {
TFMT5_ASTC_10x10 = 204,
TFMT5_ASTC_12x10 = 205,
TFMT5_ASTC_12x12 = 206,
};
enum a5xx_tex_fetchsize {
TFETCH5_1_BYTE = 0,
TFETCH5_2_BYTE = 1,
TFETCH5_4_BYTE = 2,
TFETCH5_8_BYTE = 3,
TFETCH5_16_BYTE = 4,
TFMT5_NONE = 255,
};
enum a5xx_depth_format {
@ -1052,8 +1049,18 @@ static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
{
return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK;
}
#define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
#define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000
#define A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK 0x20000000
#define A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT 29
static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val)
{
return ((val) << A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK;
}
#define A5XX_CP_PROTECT_REG_TRAP_READ__MASK 0x40000000
#define A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT 30
static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val)
{
return ((val) << A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_READ__MASK;
}
#define REG_A5XX_CP_PROTECT_CNTL 0x000008a0
@ -1825,37 +1832,192 @@ static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
#define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3
#define REG_A5XX_RBBM_STATUS 0x000004f5
#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000
#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000
#define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
#define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000
#define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000
#define A5XX_RBBM_STATUS_SP_BUSY 0x04000000
#define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000
#define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000
#define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000
#define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000
#define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000
#define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
#define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000
#define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000
#define A5XX_RBBM_STATUS_COM_BUSY 0x00010000
#define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000
#define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000
#define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000
#define A5XX_RBBM_STATUS_RB_BUSY 0x00001000
#define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800
#define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400
#define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200
#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100
#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080
#define A5XX_RBBM_STATUS_CP_BUSY 0x00000040
#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020
#define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010
#define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008
#define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
#define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK 0x80000000
#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT 31
static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK;
}
#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK 0x40000000
#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT 30
static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK;
}
#define A5XX_RBBM_STATUS_HLSQ_BUSY__MASK 0x20000000
#define A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT 29
static inline uint32_t A5XX_RBBM_STATUS_HLSQ_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT) & A5XX_RBBM_STATUS_HLSQ_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_VSC_BUSY__MASK 0x10000000
#define A5XX_RBBM_STATUS_VSC_BUSY__SHIFT 28
static inline uint32_t A5XX_RBBM_STATUS_VSC_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_VSC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VSC_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_TPL1_BUSY__MASK 0x08000000
#define A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT 27
static inline uint32_t A5XX_RBBM_STATUS_TPL1_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT) & A5XX_RBBM_STATUS_TPL1_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_SP_BUSY__MASK 0x04000000
#define A5XX_RBBM_STATUS_SP_BUSY__SHIFT 26
static inline uint32_t A5XX_RBBM_STATUS_SP_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_SP_BUSY__SHIFT) & A5XX_RBBM_STATUS_SP_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_UCHE_BUSY__MASK 0x02000000
#define A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT 25
static inline uint32_t A5XX_RBBM_STATUS_UCHE_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_UCHE_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_VPC_BUSY__MASK 0x01000000
#define A5XX_RBBM_STATUS_VPC_BUSY__SHIFT 24
static inline uint32_t A5XX_RBBM_STATUS_VPC_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_VPC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VPC_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_VFDP_BUSY__MASK 0x00800000
#define A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT 23
static inline uint32_t A5XX_RBBM_STATUS_VFDP_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFDP_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_VFD_BUSY__MASK 0x00400000
#define A5XX_RBBM_STATUS_VFD_BUSY__SHIFT 22
static inline uint32_t A5XX_RBBM_STATUS_VFD_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_VFD_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFD_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_TESS_BUSY__MASK 0x00200000
#define A5XX_RBBM_STATUS_TESS_BUSY__SHIFT 21
static inline uint32_t A5XX_RBBM_STATUS_TESS_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_TESS_BUSY__SHIFT) & A5XX_RBBM_STATUS_TESS_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK 0x00100000
#define A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT 20
static inline uint32_t A5XX_RBBM_STATUS_PC_VSD_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK 0x00080000
#define A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT 19
static inline uint32_t A5XX_RBBM_STATUS_PC_DCALL_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK 0x00040000
#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT 18
static inline uint32_t A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_DCOM_BUSY__MASK 0x00020000
#define A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT 17
static inline uint32_t A5XX_RBBM_STATUS_DCOM_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT) & A5XX_RBBM_STATUS_DCOM_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_COM_BUSY__MASK 0x00010000
#define A5XX_RBBM_STATUS_COM_BUSY__SHIFT 16
static inline uint32_t A5XX_RBBM_STATUS_COM_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_COM_BUSY__SHIFT) & A5XX_RBBM_STATUS_COM_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_LRZ_BUZY__MASK 0x00008000
#define A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT 15
static inline uint32_t A5XX_RBBM_STATUS_LRZ_BUZY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT) & A5XX_RBBM_STATUS_LRZ_BUZY__MASK;
}
#define A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK 0x00004000
#define A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT 14
static inline uint32_t A5XX_RBBM_STATUS_A2D_DSP_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT) & A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK 0x00002000
#define A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT 13
static inline uint32_t A5XX_RBBM_STATUS_CCUFCHE_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_RB_BUSY__MASK 0x00001000
#define A5XX_RBBM_STATUS_RB_BUSY__SHIFT 12
static inline uint32_t A5XX_RBBM_STATUS_RB_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_RB_BUSY__SHIFT) & A5XX_RBBM_STATUS_RB_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_RAS_BUSY__MASK 0x00000800
#define A5XX_RBBM_STATUS_RAS_BUSY__SHIFT 11
static inline uint32_t A5XX_RBBM_STATUS_RAS_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_RAS_BUSY__SHIFT) & A5XX_RBBM_STATUS_RAS_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_TSE_BUSY__MASK 0x00000400
#define A5XX_RBBM_STATUS_TSE_BUSY__SHIFT 10
static inline uint32_t A5XX_RBBM_STATUS_TSE_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_TSE_BUSY__SHIFT) & A5XX_RBBM_STATUS_TSE_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_VBIF_BUSY__MASK 0x00000200
#define A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT 9
static inline uint32_t A5XX_RBBM_STATUS_VBIF_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT) & A5XX_RBBM_STATUS_VBIF_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK 0x00000100
#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT 8
static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK;
}
#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK 0x00000080
#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT 7
static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK;
}
#define A5XX_RBBM_STATUS_CP_BUSY__MASK 0x00000040
#define A5XX_RBBM_STATUS_CP_BUSY__SHIFT 6
static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_CP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK 0x00000020
#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT 5
static inline uint32_t A5XX_RBBM_STATUS_GPMU_MASTER_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK 0x00000010
#define A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT 4
static inline uint32_t A5XX_RBBM_STATUS_CP_CRASH_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK 0x00000008
#define A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT 3
static inline uint32_t A5XX_RBBM_STATUS_CP_ETS_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK 0x00000004
#define A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT 2
static inline uint32_t A5XX_RBBM_STATUS_CP_PFP_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_CP_ME_BUSY__MASK 0x00000002
#define A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT 1
static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val)
{
return ((val) << A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ME_BUSY__MASK;
}
#define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
#define REG_A5XX_RBBM_STATUS3 0x00000530
@ -1884,14 +2046,6 @@ static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a
#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
#define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f
#define REG_A5XX_RBBM_AHB_ERROR 0x000004ed
@ -2455,8 +2609,6 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
#define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894
#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
#define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1
#define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6
@ -2659,12 +2811,16 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
#define REG_A5XX_UNKNOWN_E004 0x0000e004
#define REG_A5XX_GRAS_CNTL 0x0000e005
#define A5XX_GRAS_CNTL_VARYING 0x00000001
#define A5XX_GRAS_CNTL_UNK3 0x00000008
#define A5XX_GRAS_CNTL_XCOORD 0x00000040
#define A5XX_GRAS_CNTL_YCOORD 0x00000080
#define A5XX_GRAS_CNTL_ZCOORD 0x00000100
#define A5XX_GRAS_CNTL_WCOORD 0x00000200
#define A5XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
#define A5XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
#define A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
#define A5XX_GRAS_CNTL_SIZE 0x00000008
#define A5XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0
#define A5XX_GRAS_CNTL_COORD_MASK__SHIFT 6
static inline uint32_t A5XX_GRAS_CNTL_COORD_MASK(uint32_t val)
{
return ((val) << A5XX_GRAS_CNTL_COORD_MASK__SHIFT) & A5XX_GRAS_CNTL_COORD_MASK__MASK;
}
#define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006
#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
@ -2991,12 +3147,16 @@ static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
#define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
#define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144
#define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001
#define A5XX_RB_RENDER_CONTROL0_UNK3 0x00000008
#define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
#define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
#define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
#define A5XX_RB_RENDER_CONTROL0_WCOORD 0x00000200
#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001
#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002
#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004
#define A5XX_RB_RENDER_CONTROL0_SIZE 0x00000008
#define A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0
#define A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6
static inline uint32_t A5XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
{
return ((val) << A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
}
#define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145
#define A5XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
@ -4450,16 +4610,52 @@ static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
{
return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
}
#define A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK 0xff000000
#define A5XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT 24
static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SIZE(uint32_t val)
{
return ((val) << A5XX_HLSQ_CONTROL_2_REG_SIZE__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SIZE__MASK;
}
#define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787
#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK 0x000000ff
#define A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT 0
static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(uint32_t val)
#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
{
return ((val) << A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID__MASK;
return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
}
#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
{
return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
}
#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
{
return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
}
#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
{
return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
}
#define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788
#define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
#define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
{
return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
}
#define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
#define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
{
return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
}
#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
@ -4855,10 +5051,26 @@ static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)
#define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141
#define REG_A5XX_RB_2D_SRC_FLAGS_PITCH 0x00002142
#define A5XX_RB_2D_SRC_FLAGS_PITCH__MASK 0xffffffff
#define A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val)
{
return ((val >> 6) << A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_SRC_FLAGS_PITCH__MASK;
}
#define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143
#define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
#define REG_A5XX_RB_2D_DST_FLAGS_PITCH 0x00002145
#define A5XX_RB_2D_DST_FLAGS_PITCH__MASK 0xffffffff
#define A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
{
return ((val >> 6) << A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_DST_FLAGS_PITCH__MASK;
}
#define REG_A5XX_GRAS_2D_BLIT_CNTL 0x00002180
#define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181
@ -5059,11 +5271,11 @@ static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
}
#define REG_A5XX_TEX_CONST_2 0x00000002
#define A5XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
#define A5XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
static inline uint32_t A5XX_TEX_CONST_2_FETCHSIZE(enum a5xx_tex_fetchsize val)
#define A5XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
#define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
{
return ((val) << A5XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A5XX_TEX_CONST_2_FETCHSIZE__MASK;
return ((val) << A5XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A5XX_TEX_CONST_2_PITCHALIGN__MASK;
}
#define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
#define A5XX_TEX_CONST_2_PITCH__SHIFT 7
@ -5085,6 +5297,13 @@ static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
{
return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
}
#define A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000
#define A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23
static inline uint32_t A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
{
return ((val >> 12) << A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
}
#define A5XX_TEX_CONST_3_TILE_ALL 0x08000000
#define A5XX_TEX_CONST_3_FLAG 0x10000000
#define REG_A5XX_TEX_CONST_4 0x00000004
@ -5197,5 +5416,21 @@ static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val)
return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK;
}
#define REG_A5XX_UBO_0 0x00000000
#define A5XX_UBO_0_BASE_LO__MASK 0xffffffff
#define A5XX_UBO_0_BASE_LO__SHIFT 0
static inline uint32_t A5XX_UBO_0_BASE_LO(uint32_t val)
{
return ((val) << A5XX_UBO_0_BASE_LO__SHIFT) & A5XX_UBO_0_BASE_LO__MASK;
}
#define REG_A5XX_UBO_1 0x00000001
#define A5XX_UBO_1_BASE_HI__MASK 0x0001ffff
#define A5XX_UBO_1_BASE_HI__SHIFT 0
static inline uint32_t A5XX_UBO_1_BASE_HI(uint32_t val)
{
return ((val) << A5XX_UBO_1_BASE_HI__SHIFT) & A5XX_UBO_1_BASE_HI__MASK;
}
#endif /* A5XX_XML */

3608
drivers/gpu/drm/msm/adreno/a6xx.xml.h
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File diff suppressed because it is too large Load diff

145
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
View file

@ -8,19 +8,21 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
Copyright (C) 2013-2018 by the following authors:
Copyright (C) 2013-2020 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@ -46,24 +48,109 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB 0x00800000
#define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB 0x40000000
#define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK 0x00400000
#define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK 0x40000000
#define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK 0x40000000
#define A6XX_GMU_OOB_DCVS_SET_MASK 0x00800000
#define A6XX_GMU_OOB_DCVS_CHECK_MASK 0x80000000
#define A6XX_GMU_OOB_DCVS_CLEAR_MASK 0x80000000
#define A6XX_GMU_OOB_GPU_SET_MASK 0x00040000
#define A6XX_GMU_OOB_GPU_CHECK_MASK 0x04000000
#define A6XX_GMU_OOB_GPU_CLEAR_MASK 0x04000000
#define A6XX_GMU_OOB_PERFCNTR_SET_MASK 0x00020000
#define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK 0x02000000
#define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK 0x02000000
#define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__MASK 0x00800000
#define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__SHIFT 23
static inline uint32_t A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB(uint32_t val)
{
return ((val) << A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__SHIFT) & A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__MASK;
}
#define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__MASK 0x40000000
#define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__SHIFT 30
static inline uint32_t A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB(uint32_t val)
{
return ((val) << A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__SHIFT) & A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__MASK;
}
#define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__MASK 0x00400000
#define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__SHIFT 22
static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK(uint32_t val)
{
return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__MASK;
}
#define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__MASK 0x40000000
#define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__SHIFT 30
static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK(uint32_t val)
{
return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__MASK;
}
#define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__MASK 0x40000000
#define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__SHIFT 30
static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK(uint32_t val)
{
return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__MASK;
}
#define A6XX_GMU_OOB_DCVS_SET_MASK__MASK 0x00800000
#define A6XX_GMU_OOB_DCVS_SET_MASK__SHIFT 23
static inline uint32_t A6XX_GMU_OOB_DCVS_SET_MASK(uint32_t val)
{
return ((val) << A6XX_GMU_OOB_DCVS_SET_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_SET_MASK__MASK;
}
#define A6XX_GMU_OOB_DCVS_CHECK_MASK__MASK 0x80000000
#define A6XX_GMU_OOB_DCVS_CHECK_MASK__SHIFT 31
static inline uint32_t A6XX_GMU_OOB_DCVS_CHECK_MASK(uint32_t val)
{
return ((val) << A6XX_GMU_OOB_DCVS_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_CHECK_MASK__MASK;
}
#define A6XX_GMU_OOB_DCVS_CLEAR_MASK__MASK 0x80000000
#define A6XX_GMU_OOB_DCVS_CLEAR_MASK__SHIFT 31
static inline uint32_t A6XX_GMU_OOB_DCVS_CLEAR_MASK(uint32_t val)
{
return ((val) << A6XX_GMU_OOB_DCVS_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_CLEAR_MASK__MASK;
}
#define A6XX_GMU_OOB_GPU_SET_MASK__MASK 0x00040000
#define A6XX_GMU_OOB_GPU_SET_MASK__SHIFT 18
static inline uint32_t A6XX_GMU_OOB_GPU_SET_MASK(uint32_t val)
{
return ((val) << A6XX_GMU_OOB_GPU_SET_MASK__SHIFT) & A6XX_GMU_OOB_GPU_SET_MASK__MASK;
}
#define A6XX_GMU_OOB_GPU_CHECK_MASK__MASK 0x04000000
#define A6XX_GMU_OOB_GPU_CHECK_MASK__SHIFT 26
static inline uint32_t A6XX_GMU_OOB_GPU_CHECK_MASK(uint32_t val)
{
return ((val) << A6XX_GMU_OOB_GPU_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_GPU_CHECK_MASK__MASK;
}
#define A6XX_GMU_OOB_GPU_CLEAR_MASK__MASK 0x04000000
#define A6XX_GMU_OOB_GPU_CLEAR_MASK__SHIFT 26
static inline uint32_t A6XX_GMU_OOB_GPU_CLEAR_MASK(uint32_t val)
{
return ((val) << A6XX_GMU_OOB_GPU_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_GPU_CLEAR_MASK__MASK;
}
#define A6XX_GMU_OOB_PERFCNTR_SET_MASK__MASK 0x00020000
#define A6XX_GMU_OOB_PERFCNTR_SET_MASK__SHIFT 17
static inline uint32_t A6XX_GMU_OOB_PERFCNTR_SET_MASK(uint32_t val)
{
return ((val) << A6XX_GMU_OOB_PERFCNTR_SET_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_SET_MASK__MASK;
}
#define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__MASK 0x02000000
#define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__SHIFT 25
static inline uint32_t A6XX_GMU_OOB_PERFCNTR_CHECK_MASK(uint32_t val)
{
return ((val) << A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__MASK;
}
#define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__MASK 0x02000000
#define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__SHIFT 25
static inline uint32_t A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK(uint32_t val)
{
return ((val) << A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__MASK;
}
#define A6XX_HFI_IRQ_MSGQ_MASK 0x00000001
#define A6XX_HFI_IRQ_DSGQ_MASK 0x00000002
#define A6XX_HFI_IRQ_BLOCKED_MSG_MASK 0x00000004
#define A6XX_HFI_IRQ_CM3_FAULT_MASK 0x00800000
#define A6XX_HFI_IRQ_DSGQ_MASK__MASK 0x00000002
#define A6XX_HFI_IRQ_DSGQ_MASK__SHIFT 1
static inline uint32_t A6XX_HFI_IRQ_DSGQ_MASK(uint32_t val)
{
return ((val) << A6XX_HFI_IRQ_DSGQ_MASK__SHIFT) & A6XX_HFI_IRQ_DSGQ_MASK__MASK;
}
#define A6XX_HFI_IRQ_BLOCKED_MSG_MASK__MASK 0x00000004
#define A6XX_HFI_IRQ_BLOCKED_MSG_MASK__SHIFT 2
static inline uint32_t A6XX_HFI_IRQ_BLOCKED_MSG_MASK(uint32_t val)
{
return ((val) << A6XX_HFI_IRQ_BLOCKED_MSG_MASK__SHIFT) & A6XX_HFI_IRQ_BLOCKED_MSG_MASK__MASK;
}
#define A6XX_HFI_IRQ_CM3_FAULT_MASK__MASK 0x00800000
#define A6XX_HFI_IRQ_CM3_FAULT_MASK__SHIFT 23
static inline uint32_t A6XX_HFI_IRQ_CM3_FAULT_MASK(uint32_t val)
{
return ((val) << A6XX_HFI_IRQ_CM3_FAULT_MASK__SHIFT) & A6XX_HFI_IRQ_CM3_FAULT_MASK__MASK;
}
#define A6XX_HFI_IRQ_GMU_ERR_MASK__MASK 0x007f0000
#define A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT 16
static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val)

228
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
View file

@ -8,19 +8,21 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14)
Copyright (C) 2013-2018 by the following authors:
Copyright (C) 2013-2020 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@ -159,6 +161,7 @@ enum a3xx_msaa_samples {
MSAA_ONE = 0,
MSAA_TWO = 1,
MSAA_FOUR = 2,
MSAA_EIGHT = 3,
};
enum a3xx_threadmode {
@ -197,6 +200,11 @@ enum a4xx_tess_spacing {
EVEN_SPACING = 3,
};
enum a5xx_address_mode {
ADDR_32B = 0,
ADDR_64B = 1,
};
#define REG_AXXX_CP_RB_BASE 0x000001c0
#define REG_AXXX_CP_RB_CNTL 0x000001c1
@ -446,34 +454,174 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
#define REG_AXXX_CP_IB2_BUFSZ 0x0000045b
#define REG_AXXX_CP_STAT 0x0000047f
#define AXXX_CP_STAT_CP_BUSY 0x80000000
#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000
#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000
#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000
#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000
#define AXXX_CP_STAT_ME_BUSY 0x04000000
#define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000
#define AXXX_CP_STAT_CP_3D_BUSY 0x00800000
#define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000
#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000
#define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000
#define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000
#define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000
#define AXXX_CP_STAT_PFP_BUSY 0x00020000
#define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000
#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000
#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000
#define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800
#define AXXX_CP_STAT_CSF_BUSY 0x00000400
#define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200
#define AXXX_CP_STAT_EVENT_BUSY 0x00000100
#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080
#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040
#define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020
#define AXXX_CP_STAT_RCIU_BUSY 0x00000010
#define AXXX_CP_STAT_RBIU_BUSY 0x00000008
#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004
#define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002
#define AXXX_CP_STAT_CP_BUSY__MASK 0x80000000
#define AXXX_CP_STAT_CP_BUSY__SHIFT 31
static inline uint32_t AXXX_CP_STAT_CP_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_CP_BUSY__SHIFT) & AXXX_CP_STAT_CP_BUSY__MASK;
}
#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__MASK 0x40000000
#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__SHIFT 30
static inline uint32_t AXXX_CP_STAT_VS_EVENT_FIFO_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__MASK;
}
#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__MASK 0x20000000
#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__SHIFT 29
static inline uint32_t AXXX_CP_STAT_PS_EVENT_FIFO_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__MASK;
}
#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__MASK 0x10000000
#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__SHIFT 28
static inline uint32_t AXXX_CP_STAT_CF_EVENT_FIFO_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__MASK;
}
#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__MASK 0x08000000
#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__SHIFT 27
static inline uint32_t AXXX_CP_STAT_RB_EVENT_FIFO_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__MASK;
}
#define AXXX_CP_STAT_ME_BUSY__MASK 0x04000000
#define AXXX_CP_STAT_ME_BUSY__SHIFT 26
static inline uint32_t AXXX_CP_STAT_ME_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_ME_BUSY__SHIFT) & AXXX_CP_STAT_ME_BUSY__MASK;
}
#define AXXX_CP_STAT_MIU_WR_C_BUSY__MASK 0x02000000
#define AXXX_CP_STAT_MIU_WR_C_BUSY__SHIFT 25
static inline uint32_t AXXX_CP_STAT_MIU_WR_C_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_MIU_WR_C_BUSY__SHIFT) & AXXX_CP_STAT_MIU_WR_C_BUSY__MASK;
}
#define AXXX_CP_STAT_CP_3D_BUSY__MASK 0x00800000
#define AXXX_CP_STAT_CP_3D_BUSY__SHIFT 23
static inline uint32_t AXXX_CP_STAT_CP_3D_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_CP_3D_BUSY__SHIFT) & AXXX_CP_STAT_CP_3D_BUSY__MASK;
}
#define AXXX_CP_STAT_CP_NRT_BUSY__MASK 0x00400000
#define AXXX_CP_STAT_CP_NRT_BUSY__SHIFT 22
static inline uint32_t AXXX_CP_STAT_CP_NRT_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_CP_NRT_BUSY__SHIFT) & AXXX_CP_STAT_CP_NRT_BUSY__MASK;
}
#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY__MASK 0x00200000
#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY__SHIFT 21
static inline uint32_t AXXX_CP_STAT_RBIU_SCRATCH_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_RBIU_SCRATCH_BUSY__SHIFT) & AXXX_CP_STAT_RBIU_SCRATCH_BUSY__MASK;
}
#define AXXX_CP_STAT_RCIU_ME_BUSY__MASK 0x00100000
#define AXXX_CP_STAT_RCIU_ME_BUSY__SHIFT 20
static inline uint32_t AXXX_CP_STAT_RCIU_ME_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_RCIU_ME_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_ME_BUSY__MASK;
}
#define AXXX_CP_STAT_RCIU_PFP_BUSY__MASK 0x00080000
#define AXXX_CP_STAT_RCIU_PFP_BUSY__SHIFT 19
static inline uint32_t AXXX_CP_STAT_RCIU_PFP_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_RCIU_PFP_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_PFP_BUSY__MASK;
}
#define AXXX_CP_STAT_MEQ_RING_BUSY__MASK 0x00040000
#define AXXX_CP_STAT_MEQ_RING_BUSY__SHIFT 18
static inline uint32_t AXXX_CP_STAT_MEQ_RING_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_MEQ_RING_BUSY__SHIFT) & AXXX_CP_STAT_MEQ_RING_BUSY__MASK;
}
#define AXXX_CP_STAT_PFP_BUSY__MASK 0x00020000
#define AXXX_CP_STAT_PFP_BUSY__SHIFT 17
static inline uint32_t AXXX_CP_STAT_PFP_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_PFP_BUSY__SHIFT) & AXXX_CP_STAT_PFP_BUSY__MASK;
}
#define AXXX_CP_STAT_ST_QUEUE_BUSY__MASK 0x00010000
#define AXXX_CP_STAT_ST_QUEUE_BUSY__SHIFT 16
static inline uint32_t AXXX_CP_STAT_ST_QUEUE_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_ST_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_ST_QUEUE_BUSY__MASK;
}
#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__MASK 0x00002000
#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__SHIFT 13
static inline uint32_t AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__MASK;
}
#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__MASK 0x00001000
#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__SHIFT 12
static inline uint32_t AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__MASK;
}
#define AXXX_CP_STAT_RING_QUEUE_BUSY__MASK 0x00000800
#define AXXX_CP_STAT_RING_QUEUE_BUSY__SHIFT 11
static inline uint32_t AXXX_CP_STAT_RING_QUEUE_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_RING_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_RING_QUEUE_BUSY__MASK;
}
#define AXXX_CP_STAT_CSF_BUSY__MASK 0x00000400
#define AXXX_CP_STAT_CSF_BUSY__SHIFT 10
static inline uint32_t AXXX_CP_STAT_CSF_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_CSF_BUSY__SHIFT) & AXXX_CP_STAT_CSF_BUSY__MASK;
}
#define AXXX_CP_STAT_CSF_ST_BUSY__MASK 0x00000200
#define AXXX_CP_STAT_CSF_ST_BUSY__SHIFT 9
static inline uint32_t AXXX_CP_STAT_CSF_ST_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_CSF_ST_BUSY__SHIFT) & AXXX_CP_STAT_CSF_ST_BUSY__MASK;
}
#define AXXX_CP_STAT_EVENT_BUSY__MASK 0x00000100
#define AXXX_CP_STAT_EVENT_BUSY__SHIFT 8
static inline uint32_t AXXX_CP_STAT_EVENT_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_EVENT_BUSY__SHIFT) & AXXX_CP_STAT_EVENT_BUSY__MASK;
}
#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY__MASK 0x00000080
#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY__SHIFT 7
static inline uint32_t AXXX_CP_STAT_CSF_INDIRECT2_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_CSF_INDIRECT2_BUSY__SHIFT) & AXXX_CP_STAT_CSF_INDIRECT2_BUSY__MASK;
}
#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY__MASK 0x00000040
#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY__SHIFT 6
static inline uint32_t AXXX_CP_STAT_CSF_INDIRECTS_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_CSF_INDIRECTS_BUSY__SHIFT) & AXXX_CP_STAT_CSF_INDIRECTS_BUSY__MASK;
}
#define AXXX_CP_STAT_CSF_RING_BUSY__MASK 0x00000020
#define AXXX_CP_STAT_CSF_RING_BUSY__SHIFT 5
static inline uint32_t AXXX_CP_STAT_CSF_RING_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_CSF_RING_BUSY__SHIFT) & AXXX_CP_STAT_CSF_RING_BUSY__MASK;
}
#define AXXX_CP_STAT_RCIU_BUSY__MASK 0x00000010
#define AXXX_CP_STAT_RCIU_BUSY__SHIFT 4
static inline uint32_t AXXX_CP_STAT_RCIU_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_RCIU_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_BUSY__MASK;
}
#define AXXX_CP_STAT_RBIU_BUSY__MASK 0x00000008
#define AXXX_CP_STAT_RBIU_BUSY__SHIFT 3
static inline uint32_t AXXX_CP_STAT_RBIU_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_RBIU_BUSY__SHIFT) & AXXX_CP_STAT_RBIU_BUSY__MASK;
}
#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY__MASK 0x00000004
#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY__SHIFT 2
static inline uint32_t AXXX_CP_STAT_MIU_RD_RETURN_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_MIU_RD_RETURN_BUSY__SHIFT) & AXXX_CP_STAT_MIU_RD_RETURN_BUSY__MASK;
}
#define AXXX_CP_STAT_MIU_RD_REQ_BUSY__MASK 0x00000002
#define AXXX_CP_STAT_MIU_RD_REQ_BUSY__SHIFT 1
static inline uint32_t AXXX_CP_STAT_MIU_RD_REQ_BUSY(uint32_t val)
{
return ((val) << AXXX_CP_STAT_MIU_RD_REQ_BUSY__SHIFT) & AXXX_CP_STAT_MIU_RD_REQ_BUSY__MASK;
}
#define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001
#define REG_AXXX_CP_SCRATCH_REG0 0x00000578

939
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
View file

File diff suppressed because it is too large Load diff

24
drivers/gpu/drm/msm/disp/mdp4/mdp4.xml.h
View file

@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
Copyright (C) 2013-2018 by the following authors:
Copyright (C) 2013-2020 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)

24
drivers/gpu/drm/msm/disp/mdp5/mdp5.xml.h
View file

@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
Copyright (C) 2013-2018 by the following authors:
Copyright (C) 2013-2020 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)

24
drivers/gpu/drm/msm/disp/mdp_common.xml.h
View file

@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
Copyright (C) 2013-2018 by the following authors:
Copyright (C) 2013-2020 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)

228
drivers/gpu/drm/msm/dsi/dsi.xml.h
View file

@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
Copyright (C) 2013-2018 by the following authors:
Copyright (C) 2013-2020 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
@ -148,7 +148,31 @@ static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val)
#define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000
#define REG_DSI_FIFO_STATUS 0x00000008
#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW 0x00000001
#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW 0x00000008
#define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080
#define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH 0x00000100
#define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH 0x00000200
#define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW 0x00000400
#define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY 0x00001000
#define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL 0x00002000
#define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW 0x00004000
#define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY 0x00010000
#define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL 0x00020000
#define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW 0x00040000
#define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW 0x00080000
#define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY 0x00100000
#define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL 0x00200000
#define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW 0x00400000
#define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW 0x00800000
#define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY 0x01000000
#define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL 0x02000000
#define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW 0x04000000
#define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW 0x08000000
#define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY 0x10000000
#define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL 0x20000000
#define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW 0x40000000
#define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW 0x80000000
#define REG_DSI_VID_CFG0 0x0000000c
#define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003
@ -318,38 +342,72 @@ static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val)
#define REG_DSI_DMA_LEN 0x00000048
#define REG_DSI_CMD_MDP_STREAM_CTRL 0x00000054
#define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK 0x0000003f
#define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT 0
static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val)
#define REG_DSI_CMD_MDP_STREAM0_CTRL 0x00000054
#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK 0x0000003f
#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT 0
static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK;
return ((val) << DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK;
}
#define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
#define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT 8
static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val)
#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT 8
static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK;
return ((val) << DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK;
}
#define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK 0xffff0000
#define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT 16
static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val)
#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK 0xffff0000
#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT 16
static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK;
return ((val) << DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK;
}
#define REG_DSI_CMD_MDP_STREAM_TOTAL 0x00000058
#define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK 0x00000fff
#define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT 0
static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val)
#define REG_DSI_CMD_MDP_STREAM0_TOTAL 0x00000058
#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK 0x00000fff
#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT 0
static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK;
return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK;
}
#define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK 0x0fff0000
#define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT 16
static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val)
#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK 0x0fff0000
#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT 16
static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK;
return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK;
}
#define REG_DSI_CMD_MDP_STREAM1_CTRL 0x0000005c
#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK 0x0000003f
#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT 0
static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK;
}
#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT 8
static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK;
}
#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK 0xffff0000
#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT 16
static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK;
}
#define REG_DSI_CMD_MDP_STREAM1_TOTAL 0x00000060
#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK 0x0000ffff
#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT 0
static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK;
}
#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK 0xffff0000
#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT 16
static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val)
{
return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK;
}
#define REG_DSI_ACK_ERR_STATUS 0x00000064
@ -389,6 +447,35 @@ static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val)
#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000
#define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000
#define REG_DSI_LP_TIMER_CTRL 0x000000b4
#define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK 0x0000ffff
#define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT 0
static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val)
{
return ((val) << DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT) & DSI_LP_TIMER_CTRL_LP_RX_TO__MASK;
}
#define DSI_LP_TIMER_CTRL_BTA_TO__MASK 0xffff0000
#define DSI_LP_TIMER_CTRL_BTA_TO__SHIFT 16
static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val)
{
return ((val) << DSI_LP_TIMER_CTRL_BTA_TO__SHIFT) & DSI_LP_TIMER_CTRL_BTA_TO__MASK;
}
#define REG_DSI_HS_TIMER_CTRL 0x000000b8
#define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK 0x0000ffff
#define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT 0
static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val)
{
return ((val) << DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT) & DSI_HS_TIMER_CTRL_HS_TX_TO__MASK;
}
#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK 0x000f0000
#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT 16
static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val)
{
return ((val) << DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT) & DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK;
}
#define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN 0x10000000
#define REG_DSI_TIMEOUT_STATUS 0x000000bc
#define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0
@ -409,6 +496,19 @@ static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
#define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001
#define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010
#define REG_DSI_LANE_STATUS 0x000000a4
#define DSI_LANE_STATUS_DLN0_STOPSTATE 0x00000001
#define DSI_LANE_STATUS_DLN1_STOPSTATE 0x00000002
#define DSI_LANE_STATUS_DLN2_STOPSTATE 0x00000004
#define DSI_LANE_STATUS_DLN3_STOPSTATE 0x00000008
#define DSI_LANE_STATUS_CLKLN_STOPSTATE 0x00000010
#define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT 0x00000100
#define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT 0x00000200
#define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT 0x00000400
#define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT 0x00000800
#define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT 0x00001000
#define DSI_LANE_STATUS_DLN0_DIRECTION 0x00010000
#define REG_DSI_LANE_CTRL 0x000000a8
#define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000
@ -436,6 +536,21 @@ static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
#define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200
#define REG_DSI_CLK_STATUS 0x0000011c
#define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE 0x00000001
#define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE 0x00000002
#define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE 0x00000004
#define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE 0x00000008
#define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE 0x00000010
#define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE 0x00000020
#define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE 0x00000040
#define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE 0x00000080
#define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE 0x00000100
#define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE 0x00000200
#define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE 0x00000400
#define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE 0x00001000
#define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE 0x00002000
#define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE 0x00004000
#define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT 0x00008000
#define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000
#define REG_DSI_PHY_RESET 0x00000128
@ -444,6 +559,51 @@ static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)
#define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c
#define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001
#define REG_DSI_CMD_MODE_MDP_CTRL2 0x000001b4
#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK 0x0000000f
#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT 0
static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val)
{
return ((val) << DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK;
}
#define DSI_CMD_MODE_MDP_CTRL2_R_SEL 0x00000010
#define DSI_CMD_MODE_MDP_CTRL2_G_SEL 0x00000020
#define DSI_CMD_MODE_MDP_CTRL2_B_SEL 0x00000040
#define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP 0x00000080
#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK 0x00000700
#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT 8
static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val)
{
return ((val) << DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK;
}
#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK 0x00007000
#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT 12
static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val)
{
return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK;
}
#define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000
#define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT 0
static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val)
{
return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK;
}
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT 8
static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val)
{
return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK;
}
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK 0xffff0000
#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT 16
static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val)
{
return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK;
}
#define REG_DSI_RDBK_DATA_CTRL 0x000001d0
#define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000
#define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16

14
drivers/gpu/drm/msm/dsi/dsi_host.c
View file

@ -993,16 +993,16 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi)
/* image data and 1 byte write_memory_start cmd */
wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,
DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) |
DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(
msm_host->channel) |
DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(
DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(
MIPI_DSI_DCS_LONG_WRITE));
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,
DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(hdisplay) |
DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay));
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL,
DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) |
DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay));
}
}

24
drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
View file

@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
Copyright (C) 2013-2018 by the following authors:
Copyright (C) 2013-2020 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)

24
drivers/gpu/drm/msm/dsi/sfpb.xml.h
View file

@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
Copyright (C) 2013-2018 by the following authors:
Copyright (C) 2013-2020 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)

24
drivers/gpu/drm/msm/edp/edp.xml.h
View file

@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
Copyright (C) 2013-2018 by the following authors:
Copyright (C) 2013-2020 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)

24
drivers/gpu/drm/msm/hdmi/hdmi.xml.h
View file

@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
Copyright (C) 2013-2018 by the following authors:
Copyright (C) 2013-2020 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)

24
drivers/gpu/drm/msm/hdmi/qfprom.xml.h
View file

@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13)
- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14)
- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14)
Copyright (C) 2013-2018 by the following authors:
Copyright (C) 2013-2020 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)