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drm/xe: Create a xe_gt_freq component for raw management and sysfs
Goals of this new xe_gt_freq component: 1. Detach sysfs controls and raw freq management from GuC SLPC. 2. Create a directory that could later be aligned with devfreq. 3. Encapsulate all the freq control in a single directory. Although we only have one freq domain per GT, already start with a numbered freq0 directory so it could be expanded in the future if multiple domains or PLL are needed. Note: Although in the goal #1, the raw freq management control is mentioned, this patch only starts by the sysfs control. The RP freq configuration and init freq selection are still under the guc_pc, but should be moved to this component in a follow-up patch. v2: - Add /tile# to the doc and remove unnecessary kobject_put (Riana) - s/ssize_t/int on some ret variables (Vinay) Cc: Sujaritha Sundaresan <sujaritha.sundaresan@intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Cc: Riana Tauro <riana.tauro@intel.com> Reviewed-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Rodrigo Vivi
parent
2ab3cc4bf5
commit
bef52b5c7a
7 changed files with 349 additions and 106 deletions
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@ -73,6 +73,7 @@ xe-y += xe_bb.o \
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xe_gt_ccs_mode.o \
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xe_gt_clock.o \
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xe_gt_debugfs.o \
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xe_gt_freq.o \
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xe_gt_idle.o \
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xe_gt_mcr.o \
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xe_gt_pagefault.o \
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@ -24,6 +24,7 @@
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#include "xe_gsc.h"
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#include "xe_gt_ccs_mode.h"
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#include "xe_gt_clock.h"
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#include "xe_gt_freq.h"
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#include "xe_gt_idle.h"
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#include "xe_gt_mcr.h"
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#include "xe_gt_pagefault.h"
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@ -511,6 +512,8 @@ int xe_gt_init(struct xe_gt *gt)
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if (err)
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return err;
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xe_gt_freq_init(gt);
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xe_force_wake_init_engines(gt, gt_to_fw(gt));
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err = all_fw_domain_init(gt);
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216
drivers/gpu/drm/xe/xe_gt_freq.c
Normal file
216
drivers/gpu/drm/xe/xe_gt_freq.c
Normal file
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@ -0,0 +1,216 @@
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// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#include "xe_gt_freq.h"
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#include <linux/kobject.h>
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#include <linux/sysfs.h>
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#include <drm/drm_managed.h>
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#include <drm/drm_print.h>
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#include "xe_device_types.h"
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#include "xe_gt_sysfs.h"
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#include "xe_guc_pc.h"
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/**
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* DOC: Xe GT Frequency Management
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*
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* This component is responsible for the raw GT frequency management, including
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* the sysfs API.
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*
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* Underneath, Xe enables GuC SLPC automated frequency management. GuC is then
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* allowed to request PCODE any frequency between the Minimum and the Maximum
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* selected by this component. Furthermore, it is important to highlight that
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* PCODE is the ultimate decision maker of the actual running frequency, based
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* on thermal and other running conditions.
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*
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* Xe's Freq provides a sysfs API for frequency management:
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*
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* device/tile#/gt#/freq0/<item>_freq *read-only* files:
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* - act_freq: The actual resolved frequency decided by PCODE.
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* - cur_freq: The current one requested by GuC PC to the PCODE.
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* - rpn_freq: The Render Performance (RP) N level, which is the minimal one.
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* - rpe_freq: The Render Performance (RP) E level, which is the efficient one.
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* - rp0_freq: The Render Performance (RP) 0 level, which is the maximum one.
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*
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* device/tile#/gt#/freq0/<item>_freq *read-write* files:
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* - min_freq: Min frequency request.
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* - max_freq: Max frequency request.
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* If max <= min, then freq_min becomes a fixed frequency request.
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*/
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static struct xe_guc_pc *
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dev_to_pc(struct device *dev)
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{
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return &kobj_to_gt(dev->kobj.parent)->uc.guc.pc;
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}
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static ssize_t act_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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return sysfs_emit(buf, "%d\n", xe_guc_pc_get_act_freq(pc));
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}
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static DEVICE_ATTR_RO(act_freq);
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static ssize_t cur_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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u32 freq;
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ssize_t ret;
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ret = xe_guc_pc_get_cur_freq(pc, &freq);
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if (ret)
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return ret;
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return sysfs_emit(buf, "%d\n", freq);
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}
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static DEVICE_ATTR_RO(cur_freq);
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static ssize_t rp0_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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return sysfs_emit(buf, "%d\n", xe_guc_pc_get_rp0_freq(pc));
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}
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static DEVICE_ATTR_RO(rp0_freq);
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static ssize_t rpe_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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return sysfs_emit(buf, "%d\n", xe_guc_pc_get_rpe_freq(pc));
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}
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static DEVICE_ATTR_RO(rpe_freq);
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static ssize_t rpn_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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return sysfs_emit(buf, "%d\n", xe_guc_pc_get_rpn_freq(pc));
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}
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static DEVICE_ATTR_RO(rpn_freq);
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static ssize_t min_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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u32 freq;
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ssize_t ret;
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ret = xe_guc_pc_get_min_freq(pc, &freq);
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if (ret)
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return ret;
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return sysfs_emit(buf, "%d\n", freq);
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}
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static ssize_t min_freq_store(struct device *dev, struct device_attribute *attr,
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const char *buff, size_t count)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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u32 freq;
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ssize_t ret;
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ret = kstrtou32(buff, 0, &freq);
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if (ret)
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return ret;
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ret = xe_guc_pc_set_min_freq(pc, freq);
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if (ret)
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return ret;
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return count;
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}
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static DEVICE_ATTR_RW(min_freq);
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static ssize_t max_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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u32 freq;
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ssize_t ret;
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ret = xe_guc_pc_get_max_freq(pc, &freq);
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if (ret)
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return ret;
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return sysfs_emit(buf, "%d\n", freq);
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}
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static ssize_t max_freq_store(struct device *dev, struct device_attribute *attr,
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const char *buff, size_t count)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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u32 freq;
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ssize_t ret;
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ret = kstrtou32(buff, 0, &freq);
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if (ret)
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return ret;
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ret = xe_guc_pc_set_max_freq(pc, freq);
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if (ret)
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return ret;
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return count;
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}
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static DEVICE_ATTR_RW(max_freq);
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static const struct attribute *freq_attrs[] = {
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&dev_attr_act_freq.attr,
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&dev_attr_cur_freq.attr,
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&dev_attr_rp0_freq.attr,
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&dev_attr_rpe_freq.attr,
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&dev_attr_rpn_freq.attr,
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&dev_attr_min_freq.attr,
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&dev_attr_max_freq.attr,
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NULL
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};
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static void freq_fini(struct drm_device *drm, void *arg)
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{
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struct kobject *kobj = arg;
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sysfs_remove_files(kobj, freq_attrs);
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kobject_put(kobj);
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}
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/**
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* xe_gt_freq_init - Initialize Xe Freq component
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* @gt: Xe GT object
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*
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* It needs to be initialized after GT Sysfs and GuC PC components are ready.
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*/
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void xe_gt_freq_init(struct xe_gt *gt)
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{
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struct xe_device *xe = gt_to_xe(gt);
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int err;
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gt->freq = kobject_create_and_add("freq0", gt->sysfs);
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if (!gt->freq) {
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drm_warn(&xe->drm, "failed to add freq0 directory to %s, err: %d\n",
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kobject_name(gt->sysfs), err);
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return;
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}
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err = drmm_add_action_or_reset(&xe->drm, freq_fini, gt->freq);
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if (err) {
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drm_warn(&xe->drm, "%s: drmm_add_action_or_reset failed, err: %d\n",
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__func__, err);
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return;
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}
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err = sysfs_create_files(gt->freq, freq_attrs);
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if (err)
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drm_warn(&xe->drm, "failed to add freq attrs to %s, err: %d\n",
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kobject_name(gt->freq), err);
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}
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13
drivers/gpu/drm/xe/xe_gt_freq.h
Normal file
13
drivers/gpu/drm/xe/xe_gt_freq.h
Normal file
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@ -0,0 +1,13 @@
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_GT_FREQ_H_
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#define _XE_GT_FREQ_H_
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struct xe_gt;
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void xe_gt_freq_init(struct xe_gt *gt);
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#endif
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@ -307,6 +307,9 @@ struct xe_gt {
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/** @sysfs: sysfs' kobj used by xe_gt_sysfs */
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struct kobject *sysfs;
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/** @freq: Main GT freq sysfs control */
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struct kobject *freq;
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/** @mocs: info */
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struct {
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/** @uc_index: UC index */
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@ -57,19 +57,6 @@
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*
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* Xe driver enables SLPC with all of its defaults features and frequency
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* selection, which varies per platform.
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* Xe's GuC PC provides a sysfs API for frequency management:
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*
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* device/gt#/freq_* *read-only* files:
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* - act_freq: The actual resolved frequency decided by PCODE.
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* - cur_freq: The current one requested by GuC PC to the Hardware.
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* - rpn_freq: The Render Performance (RP) N level, which is the minimal one.
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* - rpe_freq: The Render Performance (RP) E level, which is the efficient one.
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* - rp0_freq: The Render Performance (RP) 0 level, which is the maximum one.
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*
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* device/gt#/freq_* *read-write* files:
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* - min_freq: GuC PC min request.
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* - max_freq: GuC PC max request.
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* If max <= min, then freq_min becomes a fixed frequency request.
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*
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* Render-C States:
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* ================
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@ -100,12 +87,6 @@ pc_to_gt(struct xe_guc_pc *pc)
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return container_of(pc, struct xe_gt, uc.guc.pc);
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}
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static struct xe_guc_pc *
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dev_to_pc(struct device *dev)
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{
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return &kobj_to_gt(&dev->kobj)->uc.guc.pc;
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}
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static struct iosys_map *
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pc_to_maps(struct xe_guc_pc *pc)
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{
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@ -388,14 +369,17 @@ static void pc_update_rp_values(struct xe_guc_pc *pc)
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pc->rpn_freq = min(pc->rpn_freq, pc->rpe_freq);
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}
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static ssize_t act_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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/**
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* xe_guc_pc_get_act_freq - Get Actual running frequency
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* @pc: The GuC PC
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*
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* Returns: The Actual running frequency. Which might be 0 if GT is in Render-C sleep state (RC6).
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*/
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u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc)
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{
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struct kobject *kobj = &dev->kobj;
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struct xe_gt *gt = kobj_to_gt(kobj);
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struct xe_gt *gt = pc_to_gt(pc);
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struct xe_device *xe = gt_to_xe(gt);
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u32 freq;
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ssize_t ret;
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xe_device_mem_access_get(gt_to_xe(gt));
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@ -408,20 +392,25 @@ static ssize_t act_freq_show(struct device *dev,
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freq = REG_FIELD_GET(CAGF_MASK, freq);
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}
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ret = sysfs_emit(buf, "%d\n", decode_freq(freq));
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freq = decode_freq(freq);
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xe_device_mem_access_put(gt_to_xe(gt));
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return ret;
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}
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static DEVICE_ATTR_RO(act_freq);
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static ssize_t cur_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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return freq;
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}
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/**
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* xe_guc_pc_get_cur_freq - Get Current requested frequency
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* @pc: The GuC PC
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* @freq: A pointer to a u32 where the freq value will be returned
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*
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* Returns: 0 on success,
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* -EAGAIN if GuC PC not ready (likely in middle of a reset).
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*/
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int xe_guc_pc_get_cur_freq(struct xe_guc_pc *pc, u32 *freq)
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{
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struct kobject *kobj = &dev->kobj;
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struct xe_gt *gt = kobj_to_gt(kobj);
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u32 freq;
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ssize_t ret;
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struct xe_gt *gt = pc_to_gt(pc);
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int ret;
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xe_device_mem_access_get(gt_to_xe(gt));
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/*
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@ -432,56 +421,69 @@ static ssize_t cur_freq_show(struct device *dev,
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if (ret)
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goto out;
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freq = xe_mmio_read32(gt, RPNSWREQ);
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*freq = xe_mmio_read32(gt, RPNSWREQ);
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freq = REG_FIELD_GET(REQ_RATIO_MASK, freq);
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ret = sysfs_emit(buf, "%d\n", decode_freq(freq));
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*freq = REG_FIELD_GET(REQ_RATIO_MASK, *freq);
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*freq = decode_freq(*freq);
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XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));
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out:
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xe_device_mem_access_put(gt_to_xe(gt));
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return ret;
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}
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static DEVICE_ATTR_RO(cur_freq);
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static ssize_t rp0_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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/**
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* xe_guc_pc_get_rp0_freq - Get the RP0 freq
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* @pc: The GuC PC
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*
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* Returns: RP0 freq.
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*/
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u32 xe_guc_pc_get_rp0_freq(struct xe_guc_pc *pc)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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return sysfs_emit(buf, "%d\n", pc->rp0_freq);
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return pc->rp0_freq;
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}
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static DEVICE_ATTR_RO(rp0_freq);
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static ssize_t rpe_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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/**
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* xe_guc_pc_get_rpe_freq - Get the RPe freq
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* @pc: The GuC PC
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*
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* Returns: RPe freq.
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*/
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u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc)
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{
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struct xe_guc_pc *pc = dev_to_pc(dev);
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struct xe_gt *gt = pc_to_gt(pc);
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struct xe_device *xe = gt_to_xe(gt);
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xe_device_mem_access_get(xe);
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pc_update_rp_values(pc);
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xe_device_mem_access_put(xe);
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return sysfs_emit(buf, "%d\n", pc->rpe_freq);
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return pc->rpe_freq;
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}
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static DEVICE_ATTR_RO(rpe_freq);
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static ssize_t rpn_freq_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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/**
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* xe_guc_pc_get_rpn_freq - Get the RPn freq
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* @pc: The GuC PC
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*
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* Returns: RPn freq.
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*/
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u32 xe_guc_pc_get_rpn_freq(struct xe_guc_pc *pc)
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{
|
||||
struct xe_guc_pc *pc = dev_to_pc(dev);
|
||||
|
||||
return sysfs_emit(buf, "%d\n", pc->rpn_freq);
|
||||
return pc->rpn_freq;
|
||||
}
|
||||
static DEVICE_ATTR_RO(rpn_freq);
|
||||
|
||||
static ssize_t min_freq_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
/**
|
||||
* xe_guc_pc_get_min_freq - Get the min operational frequency
|
||||
* @pc: The GuC PC
|
||||
* @freq: A pointer to a u32 where the freq value will be returned
|
||||
*
|
||||
* Returns: 0 on success,
|
||||
* -EAGAIN if GuC PC not ready (likely in middle of a reset).
|
||||
*/
|
||||
int xe_guc_pc_get_min_freq(struct xe_guc_pc *pc, u32 *freq)
|
||||
{
|
||||
struct xe_guc_pc *pc = dev_to_pc(dev);
|
||||
struct xe_gt *gt = pc_to_gt(pc);
|
||||
ssize_t ret;
|
||||
int ret;
|
||||
|
||||
xe_device_mem_access_get(pc_to_xe(pc));
|
||||
mutex_lock(&pc->freq_lock);
|
||||
|
|
@ -503,7 +505,7 @@ static ssize_t min_freq_show(struct device *dev,
|
|||
if (ret)
|
||||
goto fw;
|
||||
|
||||
ret = sysfs_emit(buf, "%d\n", pc_get_min_freq(pc));
|
||||
*freq = pc_get_min_freq(pc);
|
||||
|
||||
fw:
|
||||
XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));
|
||||
|
|
@ -513,16 +515,18 @@ out:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static ssize_t min_freq_store(struct device *dev, struct device_attribute *attr,
|
||||
const char *buff, size_t count)
|
||||
/**
|
||||
* xe_guc_pc_set_min_freq - Set the minimal operational frequency
|
||||
* @pc: The GuC PC
|
||||
* @freq: The selected minimal frequency
|
||||
*
|
||||
* Returns: 0 on success,
|
||||
* -EAGAIN if GuC PC not ready (likely in middle of a reset),
|
||||
* -EINVAL if value out of bounds.
|
||||
*/
|
||||
int xe_guc_pc_set_min_freq(struct xe_guc_pc *pc, u32 freq)
|
||||
{
|
||||
struct xe_guc_pc *pc = dev_to_pc(dev);
|
||||
u32 freq;
|
||||
ssize_t ret;
|
||||
|
||||
ret = kstrtou32(buff, 0, &freq);
|
||||
if (ret)
|
||||
return ret;
|
||||
int ret;
|
||||
|
||||
xe_device_mem_access_get(pc_to_xe(pc));
|
||||
mutex_lock(&pc->freq_lock);
|
||||
|
|
@ -541,15 +545,21 @@ static ssize_t min_freq_store(struct device *dev, struct device_attribute *attr,
|
|||
out:
|
||||
mutex_unlock(&pc->freq_lock);
|
||||
xe_device_mem_access_put(pc_to_xe(pc));
|
||||
return ret ?: count;
|
||||
}
|
||||
static DEVICE_ATTR_RW(min_freq);
|
||||
|
||||
static ssize_t max_freq_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* xe_guc_pc_get_max_freq - Get Maximum operational frequency
|
||||
* @pc: The GuC PC
|
||||
* @freq: A pointer to a u32 where the freq value will be returned
|
||||
*
|
||||
* Returns: 0 on success,
|
||||
* -EAGAIN if GuC PC not ready (likely in middle of a reset).
|
||||
*/
|
||||
int xe_guc_pc_get_max_freq(struct xe_guc_pc *pc, u32 *freq)
|
||||
{
|
||||
struct xe_guc_pc *pc = dev_to_pc(dev);
|
||||
ssize_t ret;
|
||||
int ret;
|
||||
|
||||
xe_device_mem_access_get(pc_to_xe(pc));
|
||||
mutex_lock(&pc->freq_lock);
|
||||
|
|
@ -563,7 +573,7 @@ static ssize_t max_freq_show(struct device *dev,
|
|||
if (ret)
|
||||
goto out;
|
||||
|
||||
ret = sysfs_emit(buf, "%d\n", pc_get_max_freq(pc));
|
||||
*freq = pc_get_max_freq(pc);
|
||||
|
||||
out:
|
||||
mutex_unlock(&pc->freq_lock);
|
||||
|
|
@ -571,16 +581,18 @@ out:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static ssize_t max_freq_store(struct device *dev, struct device_attribute *attr,
|
||||
const char *buff, size_t count)
|
||||
/**
|
||||
* xe_guc_pc_set_max_freq - Set the maximum operational frequency
|
||||
* @pc: The GuC PC
|
||||
* @freq: The selected maximum frequency value
|
||||
*
|
||||
* Returns: 0 on success,
|
||||
* -EAGAIN if GuC PC not ready (likely in middle of a reset),
|
||||
* -EINVAL if value out of bounds.
|
||||
*/
|
||||
int xe_guc_pc_set_max_freq(struct xe_guc_pc *pc, u32 freq)
|
||||
{
|
||||
struct xe_guc_pc *pc = dev_to_pc(dev);
|
||||
u32 freq;
|
||||
ssize_t ret;
|
||||
|
||||
ret = kstrtou32(buff, 0, &freq);
|
||||
if (ret)
|
||||
return ret;
|
||||
int ret;
|
||||
|
||||
xe_device_mem_access_get(pc_to_xe(pc));
|
||||
mutex_lock(&pc->freq_lock);
|
||||
|
|
@ -599,9 +611,8 @@ static ssize_t max_freq_store(struct device *dev, struct device_attribute *attr,
|
|||
out:
|
||||
mutex_unlock(&pc->freq_lock);
|
||||
xe_device_mem_access_put(pc_to_xe(pc));
|
||||
return ret ?: count;
|
||||
return ret;
|
||||
}
|
||||
static DEVICE_ATTR_RW(max_freq);
|
||||
|
||||
/**
|
||||
* xe_guc_pc_c_status - get the current GT C state
|
||||
|
|
@ -666,17 +677,6 @@ u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc)
|
|||
return reg;
|
||||
}
|
||||
|
||||
static const struct attribute *pc_attrs[] = {
|
||||
&dev_attr_act_freq.attr,
|
||||
&dev_attr_cur_freq.attr,
|
||||
&dev_attr_rp0_freq.attr,
|
||||
&dev_attr_rpe_freq.attr,
|
||||
&dev_attr_rpn_freq.attr,
|
||||
&dev_attr_min_freq.attr,
|
||||
&dev_attr_max_freq.attr,
|
||||
NULL
|
||||
};
|
||||
|
||||
static void mtl_init_fused_rp_values(struct xe_guc_pc *pc)
|
||||
{
|
||||
struct xe_gt *gt = pc_to_gt(pc);
|
||||
|
|
@ -952,6 +952,10 @@ out:
|
|||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* xe_guc_pc_fini - Finalize GuC's Power Conservation component
|
||||
* @pc: Xe_GuC_PC instance
|
||||
*/
|
||||
void xe_guc_pc_fini(struct xe_guc_pc *pc)
|
||||
{
|
||||
struct xe_device *xe = pc_to_xe(pc);
|
||||
|
|
@ -963,7 +967,6 @@ void xe_guc_pc_fini(struct xe_guc_pc *pc)
|
|||
|
||||
XE_WARN_ON(xe_guc_pc_gucrc_disable(pc));
|
||||
XE_WARN_ON(xe_guc_pc_stop(pc));
|
||||
sysfs_remove_files(pc_to_gt(pc)->sysfs, pc_attrs);
|
||||
mutex_destroy(&pc->freq_lock);
|
||||
}
|
||||
|
||||
|
|
@ -978,7 +981,6 @@ int xe_guc_pc_init(struct xe_guc_pc *pc)
|
|||
struct xe_device *xe = gt_to_xe(gt);
|
||||
struct xe_bo *bo;
|
||||
u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
|
||||
int err;
|
||||
|
||||
if (xe->info.skip_guc_pc)
|
||||
return 0;
|
||||
|
|
@ -992,10 +994,5 @@ int xe_guc_pc_init(struct xe_guc_pc *pc)
|
|||
return PTR_ERR(bo);
|
||||
|
||||
pc->bo = bo;
|
||||
|
||||
err = sysfs_create_files(gt->sysfs, pc_attrs);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -14,6 +14,16 @@ int xe_guc_pc_start(struct xe_guc_pc *pc);
|
|||
int xe_guc_pc_stop(struct xe_guc_pc *pc);
|
||||
int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc);
|
||||
|
||||
u32 xe_guc_pc_get_act_freq(struct xe_guc_pc *pc);
|
||||
int xe_guc_pc_get_cur_freq(struct xe_guc_pc *pc, u32 *freq);
|
||||
u32 xe_guc_pc_get_rp0_freq(struct xe_guc_pc *pc);
|
||||
u32 xe_guc_pc_get_rpe_freq(struct xe_guc_pc *pc);
|
||||
u32 xe_guc_pc_get_rpn_freq(struct xe_guc_pc *pc);
|
||||
int xe_guc_pc_get_min_freq(struct xe_guc_pc *pc, u32 *freq);
|
||||
int xe_guc_pc_set_min_freq(struct xe_guc_pc *pc, u32 freq);
|
||||
int xe_guc_pc_get_max_freq(struct xe_guc_pc *pc, u32 *freq);
|
||||
int xe_guc_pc_set_max_freq(struct xe_guc_pc *pc, u32 freq);
|
||||
|
||||
enum xe_gt_idle_state xe_guc_pc_c_status(struct xe_guc_pc *pc);
|
||||
u64 xe_guc_pc_rc6_residency(struct xe_guc_pc *pc);
|
||||
u64 xe_guc_pc_mc6_residency(struct xe_guc_pc *pc);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue