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KVM: arm64: nv: Add emulation of AT S12E{0,1}{R,W}
On the face of it, AT S12E{0,1}{R,W} is pretty simple. It is the
combination of AT S1E{0,1}{R,W}, followed by an extra S2 walk.
However, there is a great deal of complexity coming from combining
the S1 and S2 attributes to report something consistent in PAR_EL1.
This is an absolute mine field, and I have a splitting headache.
Signed-off-by: Marc Zyngier <maz@kernel.org>
This commit is contained in:
Marc Zyngier
parent
e794049b9a
commit
be04cebf3e
2 changed files with 254 additions and 0 deletions
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@ -238,6 +238,7 @@ extern int __kvm_tlbi_s1e2(struct kvm_s2_mmu *mmu, u64 va, u64 sys_encoding);
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extern void __kvm_timer_set_cntvoff(u64 cntvoff);
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extern void __kvm_at_s1e01(struct kvm_vcpu *vcpu, u32 op, u64 vaddr);
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extern void __kvm_at_s1e2(struct kvm_vcpu *vcpu, u32 op, u64 vaddr);
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extern void __kvm_at_s12(struct kvm_vcpu *vcpu, u32 op, u64 vaddr);
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extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
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@ -71,6 +71,200 @@ static bool at_s1e1p_fast(struct kvm_vcpu *vcpu, u32 op, u64 vaddr)
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return fail;
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}
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#define MEMATTR(ic, oc) (MEMATTR_##oc << 4 | MEMATTR_##ic)
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#define MEMATTR_NC 0b0100
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#define MEMATTR_Wt 0b1000
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#define MEMATTR_Wb 0b1100
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#define MEMATTR_WbRaWa 0b1111
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#define MEMATTR_IS_DEVICE(m) (((m) & GENMASK(7, 4)) == 0)
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static u8 s2_memattr_to_attr(u8 memattr)
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{
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memattr &= 0b1111;
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switch (memattr) {
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case 0b0000:
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case 0b0001:
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case 0b0010:
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case 0b0011:
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return memattr << 2;
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case 0b0100:
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return MEMATTR(Wb, Wb);
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case 0b0101:
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return MEMATTR(NC, NC);
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case 0b0110:
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return MEMATTR(Wt, NC);
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case 0b0111:
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return MEMATTR(Wb, NC);
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case 0b1000:
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/* Reserved, assume NC */
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return MEMATTR(NC, NC);
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case 0b1001:
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return MEMATTR(NC, Wt);
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case 0b1010:
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return MEMATTR(Wt, Wt);
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case 0b1011:
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return MEMATTR(Wb, Wt);
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case 0b1100:
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/* Reserved, assume NC */
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return MEMATTR(NC, NC);
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case 0b1101:
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return MEMATTR(NC, Wb);
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case 0b1110:
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return MEMATTR(Wt, Wb);
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case 0b1111:
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return MEMATTR(Wb, Wb);
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default:
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unreachable();
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}
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}
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static u8 combine_s1_s2_attr(u8 s1, u8 s2)
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{
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bool transient;
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u8 final = 0;
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/* Upgrade transient s1 to non-transient to simplify things */
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switch (s1) {
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case 0b0001 ... 0b0011: /* Normal, Write-Through Transient */
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transient = true;
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s1 = MEMATTR_Wt | (s1 & GENMASK(1,0));
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break;
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case 0b0101 ... 0b0111: /* Normal, Write-Back Transient */
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transient = true;
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s1 = MEMATTR_Wb | (s1 & GENMASK(1,0));
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break;
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default:
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transient = false;
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}
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/* S2CombineS1AttrHints() */
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if ((s1 & GENMASK(3, 2)) == MEMATTR_NC ||
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(s2 & GENMASK(3, 2)) == MEMATTR_NC)
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final = MEMATTR_NC;
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else if ((s1 & GENMASK(3, 2)) == MEMATTR_Wt ||
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(s2 & GENMASK(3, 2)) == MEMATTR_Wt)
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final = MEMATTR_Wt;
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else
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final = MEMATTR_Wb;
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if (final != MEMATTR_NC) {
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/* Inherit RaWa hints form S1 */
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if (transient) {
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switch (s1 & GENMASK(3, 2)) {
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case MEMATTR_Wt:
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final = 0;
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break;
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case MEMATTR_Wb:
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final = MEMATTR_NC;
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break;
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}
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}
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final |= s1 & GENMASK(1, 0);
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}
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return final;
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}
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#define ATTR_NSH 0b00
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#define ATTR_RSV 0b01
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#define ATTR_OSH 0b10
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#define ATTR_ISH 0b11
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static u8 compute_sh(u8 attr, u64 desc)
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{
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u8 sh;
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/* Any form of device, as well as NC has SH[1:0]=0b10 */
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if (MEMATTR_IS_DEVICE(attr) || attr == MEMATTR(NC, NC))
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return ATTR_OSH;
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sh = FIELD_GET(PTE_SHARED, desc);
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if (sh == ATTR_RSV) /* Reserved, mapped to NSH */
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sh = ATTR_NSH;
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return sh;
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}
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static u64 compute_par_s12(struct kvm_vcpu *vcpu, u64 s1_par,
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struct kvm_s2_trans *tr)
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{
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u8 s1_parattr, s2_memattr, final_attr;
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u64 par;
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/* If S2 has failed to translate, report the damage */
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if (tr->esr) {
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par = SYS_PAR_EL1_RES1;
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par |= SYS_PAR_EL1_F;
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par |= SYS_PAR_EL1_S;
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par |= FIELD_PREP(SYS_PAR_EL1_FST, tr->esr);
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return par;
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}
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s1_parattr = FIELD_GET(SYS_PAR_EL1_ATTR, s1_par);
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s2_memattr = FIELD_GET(GENMASK(5, 2), tr->desc);
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if (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_FWB) {
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if (!kvm_has_feat(vcpu->kvm, ID_AA64PFR2_EL1, MTEPERM, IMP))
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s2_memattr &= ~BIT(3);
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/* Combination of R_VRJSW and R_RHWZM */
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switch (s2_memattr) {
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case 0b0101:
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if (MEMATTR_IS_DEVICE(s1_parattr))
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final_attr = s1_parattr;
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else
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final_attr = MEMATTR(NC, NC);
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break;
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case 0b0110:
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case 0b1110:
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final_attr = MEMATTR(WbRaWa, WbRaWa);
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break;
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case 0b0111:
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case 0b1111:
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/* Preserve S1 attribute */
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final_attr = s1_parattr;
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break;
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case 0b0100:
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case 0b1100:
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case 0b1101:
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/* Reserved, do something non-silly */
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final_attr = s1_parattr;
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break;
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default:
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/* MemAttr[2]=0, Device from S2 */
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final_attr = s2_memattr & GENMASK(1,0) << 2;
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}
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} else {
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/* Combination of R_HMNDG, R_TNHFM and R_GQFSF */
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u8 s2_parattr = s2_memattr_to_attr(s2_memattr);
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if (MEMATTR_IS_DEVICE(s1_parattr) ||
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MEMATTR_IS_DEVICE(s2_parattr)) {
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final_attr = min(s1_parattr, s2_parattr);
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} else {
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/* At this stage, this is memory vs memory */
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final_attr = combine_s1_s2_attr(s1_parattr & 0xf,
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s2_parattr & 0xf);
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final_attr |= combine_s1_s2_attr(s1_parattr >> 4,
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s2_parattr >> 4) << 4;
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}
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}
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if ((__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_CD) &&
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!MEMATTR_IS_DEVICE(final_attr))
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final_attr = MEMATTR(NC, NC);
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par = FIELD_PREP(SYS_PAR_EL1_ATTR, final_attr);
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par |= tr->output & GENMASK(47, 12);
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par |= FIELD_PREP(SYS_PAR_EL1_SH,
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compute_sh(final_attr, tr->desc));
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return par;
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}
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/*
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* Return the PAR_EL1 value as the result of a valid translation.
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*
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@ -215,3 +409,62 @@ void __kvm_at_s1e2(struct kvm_vcpu *vcpu, u32 op, u64 vaddr)
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vcpu_write_sys_reg(vcpu, par, PAR_EL1);
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}
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void __kvm_at_s12(struct kvm_vcpu *vcpu, u32 op, u64 vaddr)
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{
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struct kvm_s2_trans out = {};
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u64 ipa, par;
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bool write;
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int ret;
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/* Do the stage-1 translation */
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switch (op) {
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case OP_AT_S12E1R:
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op = OP_AT_S1E1R;
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write = false;
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break;
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case OP_AT_S12E1W:
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op = OP_AT_S1E1W;
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write = true;
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break;
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case OP_AT_S12E0R:
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op = OP_AT_S1E0R;
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write = false;
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break;
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case OP_AT_S12E0W:
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op = OP_AT_S1E0W;
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write = true;
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break;
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default:
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WARN_ON_ONCE(1);
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return;
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}
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__kvm_at_s1e01(vcpu, op, vaddr);
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par = vcpu_read_sys_reg(vcpu, PAR_EL1);
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if (par & SYS_PAR_EL1_F)
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return;
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/*
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* If we only have a single stage of translation (E2H=0 or
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* TGE=1), exit early. Same thing if {VM,DC}=={0,0}.
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*/
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if (!vcpu_el2_e2h_is_set(vcpu) || vcpu_el2_tge_is_set(vcpu) ||
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!(vcpu_read_sys_reg(vcpu, HCR_EL2) & (HCR_VM | HCR_DC)))
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return;
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/* Do the stage-2 translation */
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ipa = (par & GENMASK_ULL(47, 12)) | (vaddr & GENMASK_ULL(11, 0));
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out.esr = 0;
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ret = kvm_walk_nested_s2(vcpu, ipa, &out);
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if (ret < 0)
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return;
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/* Check the access permission */
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if (!out.esr &&
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((!write && !out.readable) || (write && !out.writable)))
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out.esr = ESR_ELx_FSC_PERM | (out.level & 0x3);
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par = compute_par_s12(vcpu, par, &out);
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vcpu_write_sys_reg(vcpu, par, PAR_EL1);
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}
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