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powerpc/test_emulate_step: Add testcases for divde[.] and divdeu[.] instructions

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Add testcases for divde, divde., divdeu, divdeu. emulated instructions
to cover few scenarios,
  - with same dividend and divisor to have undefine RT
    for divdeu[.]
  - with divide by zero to have undefine RT for both
    divde[.] and divdeu[.]
  - with negative dividend to cover -|divisor| < r <= 0 if
    the dividend is negative for divde[.]
  - normal case with proper dividend and divisor for both
    divde[.] and divdeu[.]

Signed-off-by: Balamuruhan S <bala24@linux.ibm.com>
Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>
Acked-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200728130308.1790982-4-bala24@linux.ibm.com
This commit is contained in:
Balamuruhan S 2020-07-28 18:33:08 +05:30 • committed by Michael Ellerman
parent 151c32bf5e
commit b859c95cf4
1 changed files with 156 additions and 0 deletions
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156
arch/powerpc/lib/test_emulate_step.c
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@ -1019,6 +1019,162 @@ static struct compute_test compute_tests[] = {
} }
} }
}, },
{
.mnemonic = "divde",
.subtests = {
{
.descr = "RA = LONG_MIN, RB = LONG_MIN",
.instr = ppc_inst(PPC_RAW_DIVDE(20, 21, 22)),
.regs = {
.gpr[21] = LONG_MIN,
.gpr[22] = LONG_MIN,
}
},
{
.descr = "RA = 1L, RB = 0",
.instr = ppc_inst(PPC_RAW_DIVDE(20, 21, 22)),
.flags = IGNORE_GPR(20),
.regs = {
.gpr[21] = 1L,
.gpr[22] = 0,
}
},
{
.descr = "RA = LONG_MIN, RB = LONG_MAX",
.instr = ppc_inst(PPC_RAW_DIVDE(20, 21, 22)),
.regs = {
.gpr[21] = LONG_MIN,
.gpr[22] = LONG_MAX,
}
}
}
},
{
.mnemonic = "divde.",
.subtests = {
{
.descr = "RA = LONG_MIN, RB = LONG_MIN",
.instr = ppc_inst(PPC_RAW_DIVDE_DOT(20, 21, 22)),
.regs = {
.gpr[21] = LONG_MIN,
.gpr[22] = LONG_MIN,
}
},
{
.descr = "RA = 1L, RB = 0",
.instr = ppc_inst(PPC_RAW_DIVDE_DOT(20, 21, 22)),
.flags = IGNORE_GPR(20),
.regs = {
.gpr[21] = 1L,
.gpr[22] = 0,
}
},
{
.descr = "RA = LONG_MIN, RB = LONG_MAX",
.instr = ppc_inst(PPC_RAW_DIVDE_DOT(20, 21, 22)),
.regs = {
.gpr[21] = LONG_MIN,
.gpr[22] = LONG_MAX,
}
}
}
},
{
.mnemonic = "divdeu",
.subtests = {
{
.descr = "RA = LONG_MIN, RB = LONG_MIN",
.instr = ppc_inst(PPC_RAW_DIVDEU(20, 21, 22)),
.flags = IGNORE_GPR(20),
.regs = {
.gpr[21] = LONG_MIN,
.gpr[22] = LONG_MIN,
}
},
{
.descr = "RA = 1L, RB = 0",
.instr = ppc_inst(PPC_RAW_DIVDEU(20, 21, 22)),
.flags = IGNORE_GPR(20),
.regs = {
.gpr[21] = 1L,
.gpr[22] = 0,
}
},
{
.descr = "RA = LONG_MIN, RB = LONG_MAX",
.instr = ppc_inst(PPC_RAW_DIVDEU(20, 21, 22)),
.regs = {
.gpr[21] = LONG_MIN,
.gpr[22] = LONG_MAX,
}
},
{
.descr = "RA = LONG_MAX - 1, RB = LONG_MAX",
.instr = ppc_inst(PPC_RAW_DIVDEU(20, 21, 22)),
.regs = {
.gpr[21] = LONG_MAX - 1,
.gpr[22] = LONG_MAX,
}
},
{
.descr = "RA = LONG_MIN + 1, RB = LONG_MIN",
.instr = ppc_inst(PPC_RAW_DIVDEU(20, 21, 22)),
.flags = IGNORE_GPR(20),
.regs = {
.gpr[21] = LONG_MIN + 1,
.gpr[22] = LONG_MIN,
}
}
}
},
{
.mnemonic = "divdeu.",
.subtests = {
{
.descr = "RA = LONG_MIN, RB = LONG_MIN",
.instr = ppc_inst(PPC_RAW_DIVDEU_DOT(20, 21, 22)),
.flags = IGNORE_GPR(20),
.regs = {
.gpr[21] = LONG_MIN,
.gpr[22] = LONG_MIN,
}
},
{
.descr = "RA = 1L, RB = 0",
.instr = ppc_inst(PPC_RAW_DIVDEU_DOT(20, 21, 22)),
.flags = IGNORE_GPR(20),
.regs = {
.gpr[21] = 1L,
.gpr[22] = 0,
}
},
{
.descr = "RA = LONG_MIN, RB = LONG_MAX",
.instr = ppc_inst(PPC_RAW_DIVDEU_DOT(20, 21, 22)),
.regs = {
.gpr[21] = LONG_MIN,
.gpr[22] = LONG_MAX,
}
},
{
.descr = "RA = LONG_MAX - 1, RB = LONG_MAX",
.instr = ppc_inst(PPC_RAW_DIVDEU_DOT(20, 21, 22)),
.regs = {
.gpr[21] = LONG_MAX - 1,
.gpr[22] = LONG_MAX,
}
},
{
.descr = "RA = LONG_MIN + 1, RB = LONG_MIN",
.instr = ppc_inst(PPC_RAW_DIVDEU_DOT(20, 21, 22)),
.flags = IGNORE_GPR(20),
.regs = {
.gpr[21] = LONG_MIN + 1,
.gpr[22] = LONG_MIN,
}
}
}
},
{ {
.mnemonic = "paddi", .mnemonic = "paddi",
.cpu_feature = CPU_FTR_ARCH_31, .cpu_feature = CPU_FTR_ARCH_31,