mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-11-01 09:13:37 +00:00
Pin control changes for the v6.14 kernel cycle:
No core changes this time New drivers: - New subdriver for the Qualcomm MSM8917 SoC TLMM - New subdriver for the Mediatek MT7988 SoC - New subdriver for the Rockchip RK3562 SoC - New subdriver for the Renesas RZ/G3E SoC Improvements: - Fix some missing pins in the Qualcomm IPQ5424 TLMM - Fix some missing LVDS pins in the Sunxi A100/A133 - Support Sunxi V853 (simple compatible string) - Cleanups in the Samsung driver - Fix some AMD suspend behaviour - Cleanups -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAmeR+5IACgkQQRCzN7AZ XXNkTQ/7Blf3alkeaUTjTj3LYFfaky2UjV8i2QLtRiznaLsNitNzRAOq8VYWFKHl ysDB8Bheal0vmUEig5I+CboTq2cTt5M5abcQHccOzq29Ln0O9nhlEgds2VjqRgxc 6rD5TtbeXISkaLBUQdOQ0CkfmoAq0ihH8krFT8gOP01iiiGdLMq3g+v0F6g+wgOX 0YV6v10wDTsxyh0xlBlshcEt+wTe4EC85WsQf9EerCnSbAqMk32lGLRGeIkazZyX l0mTm/JuB7m1UKS2eaZiyOpikK7aq7NirtFTdb5EGa3KYwlwYueiI0AjqCkx//NF 0txtrk83EU+ApQuP3cXt5mCm19BBpSbIMMuv5qmz1EiX3kBEK++NM7L00ERatHDV LXwWObedtkMwzLPmOSPW/RXg7LhnoO34HgbEjznJQ6vV06a9hCMyJZCcIXOrxIP+ +M5HHbVNrEt5MpcG5Q0FCTALiEKd7cmkQDoZAM9tracl4g5NdZawi4A+PwMdX6UO YYnAMYEdJGlCEvcpKNjTebdHz1PDRThk/bLtNNEJ9X8k0inA2H6XIOKW2LFjfR9c jNVBxQyOc6o2SKTWdzJm6+F4b/Rzo7awZzXFvURSguCRnbiJ81hIOwooE/o5+IJF Fg1N+7cC5AQdtKCy4rh7Hy0H+132XIFPSdeknk5BxUMtXpSGjh8= =qLiC -----END PGP SIGNATURE----- Merge tag 'pinctrl-v6.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "No core changes this time New drivers: - New subdriver for the Qualcomm MSM8917 SoC TLMM - New subdriver for the Mediatek MT7988 SoC - New subdriver for the Rockchip RK3562 SoC - New subdriver for the Renesas RZ/G3E SoC Improvements: - Fix some missing pins in the Qualcomm IPQ5424 TLMM - Fix some missing LVDS pins in the Sunxi A100/A133 - Support Sunxi V853 (simple compatible string) - Cleanups in the Samsung driver - Fix some AMD suspend behaviour - Cleanups" * tag 'pinctrl-v6.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (29 commits) dt-bindings: pinctrl: sunxi: add compatible for V853 pinctrl: Use str_enable_disable-like helpers dt-bindings: pinctrl: Correct indentation and style in DTS example pinctrl: amd: Take suspend type into consideration which pins are non-wake pinctrl: stm32: Add check for clk_enable() pinctrl: renesas: rzg2l: Fix PFC_MASK for RZ/V2H and RZ/G3E pinctrl: sunxi: add missed lvds pins for a100/a133 pinctrl: mediatek: Drop mtk_pinconf_bias_set_pd() pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table dt-bindings: pinctrl: renesas: Document RZ/G3E SoC dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H pinctrl: rockchip: add rk3562 support dt-bindings: pinctrl: Add rk3562 pinctrl support pinctrl: Fix the clean up on pinconf_apply_setting failure dt-bindings: pinctrl: add binding for MT7988 SoC pinctrl: mediatek: add MT7988 pinctrl driver pinctrl: mediatek: add support for MTK_PULL_PD_TYPE pinctrl: ocelot: Constify some structures pinctrl: renesas: rzg2l: Add audio clock pins on RZ/G3S ...
This commit is contained in:
Linus Torvalds
commit
b746043cb3
46 changed files with 4789 additions and 287 deletions
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@ -44,6 +44,7 @@ properties:
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||||||
- allwinner,sun8i-r40-pinctrl
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- allwinner,sun8i-r40-pinctrl
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||||||
- allwinner,sun8i-v3-pinctrl
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- allwinner,sun8i-v3-pinctrl
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||||||
- allwinner,sun8i-v3s-pinctrl
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- allwinner,sun8i-v3s-pinctrl
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||||||
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- allwinner,sun8i-v853-pinctrl
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||||||
- allwinner,sun9i-a80-pinctrl
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- allwinner,sun9i-a80-pinctrl
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||||||
- allwinner,sun9i-a80-r-pinctrl
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- allwinner,sun9i-a80-r-pinctrl
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||||||
- allwinner,sun20i-d1-pinctrl
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- allwinner,sun20i-d1-pinctrl
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||||||
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@ -179,6 +180,18 @@ allOf:
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||||||
minItems: 7
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minItems: 7
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maxItems: 7
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maxItems: 7
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- if:
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properties:
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compatible:
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enum:
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- allwinner,sun8i-v853-pinctrl
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then:
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properties:
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interrupts:
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minItems: 8
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maxItems: 8
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||||||
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- if:
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- if:
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properties:
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properties:
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compatible:
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compatible:
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@ -145,40 +145,40 @@ additionalProperties:
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examples:
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examples:
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- |
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- |
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#include <dt-bindings/clock/at91.h>
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#include <dt-bindings/clock/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/pinctrl/at91.h>
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pinctrl@fffff400 {
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pinctrl@fffff400 {
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#address-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
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compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
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ranges = <0xfffff400 0xfffff400 0x600>;
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ranges = <0xfffff400 0xfffff400 0x600>;
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atmel,mux-mask = <
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atmel,mux-mask = <
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/* A B */
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/* A B */
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0xffffffff 0xffc00c3b /* pioA */
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0xffffffff 0xffc00c3b /* pioA */
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0xffffffff 0x7fff3ccf /* pioB */
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0xffffffff 0x7fff3ccf /* pioB */
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0xffffffff 0x007fffff /* pioC */
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0xffffffff 0x007fffff /* pioC */
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>;
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>;
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dbgu {
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dbgu {
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pinctrl_dbgu: dbgu-0 {
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dbgu-0 {
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atmel,pins =
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atmel,pins =
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<AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
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<AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
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AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
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AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
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};
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};
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};
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};
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pioA: gpio@fffff400 {
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gpio@fffff400 {
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compatible = "atmel,at91rm9200-gpio";
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compatible = "atmel,at91rm9200-gpio";
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reg = <0xfffff400 0x200>;
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reg = <0xfffff400 0x200>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
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#gpio-cells = <2>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-controller;
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interrupt-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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#interrupt-cells = <2>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
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};
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};
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};
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};
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...
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...
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@ -0,0 +1,575 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7988-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek MT7988 Pin Controller
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maintainers:
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- Sean Wang <sean.wang@kernel.org>
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description:
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The MediaTek's MT7988 Pin controller is used to control SoC pins.
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properties:
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compatible:
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enum:
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- mediatek,mt7988-pinctrl
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reg:
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minItems: 7
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maxItems: 7
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reg-names:
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items:
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- const: gpio
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- const: iocfg_tr
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- const: iocfg_br
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- const: iocfg_rb
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- const: iocfg_lb
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- const: iocfg_tl
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- const: eint
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gpio-controller: true
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"#gpio-cells":
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const: 2
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gpio-ranges:
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minItems: 1
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maxItems: 5
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description:
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GPIO valid number range.
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interrupt-controller: true
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interrupts:
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maxItems: 1
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"#interrupt-cells":
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const: 2
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allOf:
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- $ref: pinctrl.yaml#
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required:
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- compatible
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- reg
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- reg-names
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- gpio-controller
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- "#gpio-cells"
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patternProperties:
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'-pins$':
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type: object
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additionalProperties: false
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properties:
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mux:
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type: object
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additionalProperties: false
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$ref: /schemas/pinctrl/pinmux-node.yaml
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description: |
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pinmux configuration nodes.
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The following table shows the effective values of "group", "function"
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properties and chip pinout pins
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groups function pins (in pin#)
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---------------------------------------------------------------------
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"tops_jtag0_0" "jtag" 0, 1, 2, 3, 4
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"wo0_jtag" "jtag" 50, 51, 52, 53, 54
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"wo1_jtag" "jtag" 50, 51, 52, 53, 54
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"wo2_jtag" "jtag" 50, 51, 52, 53, 54
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"jtag" "jtag" 58, 59, 60, 61, 62
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"tops_jtag0_1" "jtag" 58, 59, 60, 61, 62
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"int_usxgmii" "int_usxgmii" 2, 3
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"pwm0" "pwm" 57
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"pwm1" "pwm" 21
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"pwm2" "pwm" 80
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"pwm2_0" "pwm" 58
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"pwm3" "pwm" 81
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"pwm3_0" "pwm" 59
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"pwm4" "pwm" 82
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"pwm4_0" "pwm" 60
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"pwm5" "pwm" 83
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"pwm5_0" "pwm" 61
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"pwm6" "pwm" 69
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"pwm6_0" "pwm" 62
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"pwm7" "pwm" 70
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"pwm7_0" "pwm" 4
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"dfd" "dfd" 0, 1, 2, 3, 4
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"xfi_phy0_i2c0" "i2c" 0, 1
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"xfi_phy1_i2c0" "i2c" 0, 1
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"xfi_phy_pll_i2c0" "i2c" 3, 4
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"xfi_phy_pll_i2c1" "i2c" 3, 4
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"i2c0_0" "i2c" 5, 6
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"i2c1_sfp" "i2c" 5, 6
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"xfi_pextp_phy0_i2c" "i2c" 5, 6
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"xfi_pextp_phy1_i2c" "i2c" 5, 6
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"i2c0_1" "i2c" 15, 16
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"u30_phy_i2c0" "i2c" 15, 16
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"u32_phy_i2c0" "i2c" 15, 16
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"xfi_phy0_i2c1" "i2c" 15, 16
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"xfi_phy1_i2c1" "i2c" 15, 16
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"xfi_phy_pll_i2c2" "i2c" 15, 16
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"i2c1_0" "i2c" 17, 18
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"u30_phy_i2c1" "i2c" 17, 18
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"u32_phy_i2c1" "i2c" 17, 18
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"xfi_phy_pll_i2c3" "i2c" 17, 18
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"sgmii0_i2c" "i2c" 17, 18
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"sgmii1_i2c" "i2c" 17, 18
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"i2c1_2" "i2c" 69, 70
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"i2c2_0" "i2c" 69, 70
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"i2c2_1" "i2c" 71, 72
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"mdc_mdio0" "eth" 5, 6
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"2p5g_ext_mdio" "eth" 28, 29
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"gbe_ext_mdio" "eth" 30, 31
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"mdc_mdio1" "eth" 69, 70
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"pcie_wake_n0_0" "pcie" 7
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"pcie_clk_req_n0_0" "pcie" 8
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"pcie_wake_n3_0" "pcie" 9
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"pcie_clk_req_n3" "pcie" 10
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"pcie_clk_req_n0_1" "pcie" 10
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"pcie_p0_phy_i2c" "pcie" 7, 8
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"pcie_p1_phy_i2c" "pcie" 7, 8
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|
"pcie_p3_phy_i2c" "pcie" 9, 10
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|
"pcie_p2_phy_i2c" "pcie" 7, 8
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|
"ckm_phy_i2c" "pcie" 9, 10
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"pcie_wake_n0_1" "pcie" 13
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||||||
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"pcie_wake_n3_1" "pcie" 14
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"pcie_2l_0_pereset" "pcie" 19
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||||||
|
"pcie_1l_1_pereset" "pcie" 20
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||||||
|
"pcie_clk_req_n2_1" "pcie" 63
|
||||||
|
"pcie_2l_1_pereset" "pcie" 73
|
||||||
|
"pcie_1l_0_pereset" "pcie" 74
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||||||
|
"pcie_wake_n1_0" "pcie" 75
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||||||
|
"pcie_clk_req_n1" "pcie" 76
|
||||||
|
"pcie_wake_n2_0" "pcie" 77
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||||||
|
"pcie_clk_req_n2_0" "pcie" 78
|
||||||
|
"pcie_wake_n2_1" "pcie" 79
|
||||||
|
"pmic" "pmic" 11
|
||||||
|
"watchdog" "watchdog" 12
|
||||||
|
"spi0_wp_hold" "spi" 22, 23
|
||||||
|
"spi0" "spi" 24, 25, 26, 27
|
||||||
|
"spi1" "spi" 28, 29, 30, 31
|
||||||
|
"spi2" "spi" 32, 33, 34, 35
|
||||||
|
"spi2_wp_hold" "spi" 36, 37
|
||||||
|
"snfi" "flash" 22, 23, 24, 25, 26, 27
|
||||||
|
"emmc_45" "flash" 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37
|
||||||
|
"sdcard" "flash" 32, 33, 34, 35, 36, 37
|
||||||
|
"emmc_51" "flash" 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49
|
||||||
|
"uart2" "uart" 0, 1, 2, 3
|
||||||
|
"tops_uart0_0" "uart" 22, 23
|
||||||
|
"uart2_0" "uart" 28, 29, 30, 31
|
||||||
|
"uart1_0" "uart" 32, 33, 34, 35
|
||||||
|
"uart2_1" "uart" 32, 33, 34, 35
|
||||||
|
"net_wo0_uart_txd_0" "uart" 28
|
||||||
|
"net_wo1_uart_txd_0" "uart" 29
|
||||||
|
"net_wo2_uart_txd_0" "uart" 30
|
||||||
|
"tops_uart1_0" "uart" 28, 29
|
||||||
|
"tops_uart0_1" "uart" 30, 31
|
||||||
|
"tops_uart1_1" "uart" 36, 37
|
||||||
|
"uart0" "uart" 55, 56
|
||||||
|
"tops_uart0_2" "uart" 55, 56
|
||||||
|
"uart2_2" "uart" 50, 51, 52, 53
|
||||||
|
"uart1_1" "uart" 58, 59, 60, 61
|
||||||
|
"uart2_3" "uart" 58, 59, 60, 61
|
||||||
|
"uart1_2" "uart" 80, 81, 82, 83
|
||||||
|
"uart1_2_lite" "uart" 80, 81
|
||||||
|
"tops_uart1_2" "uart" 80, 81
|
||||||
|
"net_wo0_uart_txd_1" "uart" 80
|
||||||
|
"net_wo1_uart_txd_1" "uart" 81
|
||||||
|
"net_wo2_uart_txd_1" "uart" 82
|
||||||
|
"udi" "udi" 32, 33, 34, 35, 36
|
||||||
|
"i2s" "audio" 50, 51, 52, 53, 54
|
||||||
|
"pcm" "audio" 50, 51, 52, 53
|
||||||
|
"gbe0_led1" "led" 58
|
||||||
|
"gbe1_led1" "led" 59
|
||||||
|
"gbe2_led1" "led" 60
|
||||||
|
"gbe3_led1" "led" 61
|
||||||
|
"2p5gbe_led1" "led" 62
|
||||||
|
"gbe0_led0" "led" 64
|
||||||
|
"gbe1_led0" "led" 65
|
||||||
|
"gbe2_led0" "led" 66
|
||||||
|
"gbe3_led0" "led" 67
|
||||||
|
"2p5gbe_led0" "led" 68
|
||||||
|
"drv_vbus_p1" "usb" 63
|
||||||
|
"drv_vbus" "usb" 79
|
||||||
|
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
description:
|
||||||
|
A string containing the name of the function to mux to the group.
|
||||||
|
enum: [audio, dfd, eth, flash, i2c, int_usxgmii, jtag, led, pcie, pmic, pwm, spi,
|
||||||
|
uart, udi, usb, watchdog]
|
||||||
|
groups:
|
||||||
|
description:
|
||||||
|
An array of strings. Each string contains the name of a group.
|
||||||
|
|
||||||
|
required:
|
||||||
|
- function
|
||||||
|
- groups
|
||||||
|
|
||||||
|
allOf:
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
const: audio
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
groups:
|
||||||
|
enum: [i2s, pcm]
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
const: jtag
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
groups:
|
||||||
|
enum: [jtag, tops_jtag0_0, tops_jtag0_1, wo0_jtag, wo1_jtag, wo2_jtag]
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
const: int_usxgmii
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
groups:
|
||||||
|
const: int_usxgmii
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
const: dfd
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
groups:
|
||||||
|
const: dfd
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
const: flash
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
groups:
|
||||||
|
enum: [emmc_45, emmc_51, sdcard, snfi]
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
const: eth
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
groups:
|
||||||
|
enum: [2p5g_ext_mdio, gbe_ext_mdio, mdc_mdio0, mdc_mdio1]
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
const: i2c
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
groups:
|
||||||
|
enum: [xfi_phy0_i2c0, xfi_phy1_i2c0, xfi_phy_pll_i2c0,
|
||||||
|
xfi_phy_pll_i2c1, i2c0_0, i2c1_sfp, xfi_pextp_phy0_i2c,
|
||||||
|
xfi_pextp_phy1_i2c, i2c0_1, u30_phy_i2c0, u32_phy_i2c0,
|
||||||
|
xfi_phy0_i2c1, xfi_phy1_i2c1, xfi_phy_pll_i2c2, i2c1_0,
|
||||||
|
u30_phy_i2c1, u32_phy_i2c1, xfi_phy_pll_i2c3, sgmii0_i2c,
|
||||||
|
sgmii1_i2c, i2c1_2, i2c2_0, i2c2_1]
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
const: led
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
groups:
|
||||||
|
enum: [2p5gbe_led0, 2p5gbe_led1, gbe0_led0, gbe0_led1, gbe1_led0, gbe1_led1,
|
||||||
|
gbe2_led0, gbe2_led1, gbe3_led0, gbe3_led1, wf5g_led0, wf5g_led1]
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
const: pcie
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
groups:
|
||||||
|
items:
|
||||||
|
enum: [pcie_wake_n0_0, pcie_clk_req_n0_0, pcie_wake_n3_0,
|
||||||
|
pcie_clk_req_n3, pcie_p0_phy_i2c, pcie_p1_phy_i2c,
|
||||||
|
pcie_p3_phy_i2c, pcie_p2_phy_i2c, ckm_phy_i2c,
|
||||||
|
pcie_wake_n0_1, pcie_wake_n3_1, pcie_2l_0_pereset,
|
||||||
|
pcie_1l_1_pereset, pcie_clk_req_n2_1, pcie_2l_1_pereset,
|
||||||
|
pcie_1l_0_pereset, pcie_wake_n1_0, pcie_clk_req_n1,
|
||||||
|
pcie_wake_n2_0, pcie_clk_req_n2_0, pcie_wake_n2_1,
|
||||||
|
pcie_clk_req_n0_1]
|
||||||
|
maxItems: 3
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
const: pmic
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
groups:
|
||||||
|
const: pmic
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
const: pwm
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
groups:
|
||||||
|
items:
|
||||||
|
enum: [pwm0, pwm1, pwm2, pwm2_0, pwm3, pwm3_0, pwm4, pwm4_0, pwm5, pwm5_0,
|
||||||
|
pwm6, pwm6_0, pwm7, pwm7_0]
|
||||||
|
maxItems: 2
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
const: spi
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
groups:
|
||||||
|
items:
|
||||||
|
enum: [spi0, spi0_wp_hold, spi1, spi2, spi2_wp_hold]
|
||||||
|
maxItems: 2
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
const: uart
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
groups:
|
||||||
|
items:
|
||||||
|
enum: [net_wo0_uart_txd_0, net_wo0_uart_txd_1, net_wo1_uart_txd_0,
|
||||||
|
net_wo1_uart_txd_1, net_wo2_uart_txd_0, net_wo2_uart_txd_1,
|
||||||
|
tops_uart0_0, tops_uart0_1, tops_uart0_2, tops_uart1_0,
|
||||||
|
tops_uart1_1, tops_uart1_2, uart0, uart1_0, uart1_1, uart1_2,
|
||||||
|
uart1_2_lite, uart2, uart2_0, uart2_1, uart2_3]
|
||||||
|
maxItems: 2
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
const: watchdog
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
groups:
|
||||||
|
const: watchdog
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
const: udi
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
groups:
|
||||||
|
const: udi
|
||||||
|
- if:
|
||||||
|
properties:
|
||||||
|
function:
|
||||||
|
const: usb
|
||||||
|
then:
|
||||||
|
properties:
|
||||||
|
groups:
|
||||||
|
items:
|
||||||
|
enum: [drv_vbus, drv_vbus_p1]
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
patternProperties:
|
||||||
|
'^conf(-[-a-z]*)?$':
|
||||||
|
type: object
|
||||||
|
additionalProperties: false
|
||||||
|
description:
|
||||||
|
pinconf configuration nodes.
|
||||||
|
$ref: /schemas/pinctrl/pincfg-node.yaml
|
||||||
|
|
||||||
|
properties:
|
||||||
|
pins:
|
||||||
|
description:
|
||||||
|
An array of strings. Each string contains the name of a pin.
|
||||||
|
items:
|
||||||
|
enum: [UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS, GPIO_A, SMI_0_MDC,
|
||||||
|
SMI_0_MDIO, PCIE30_2L_0_WAKE_N, PCIE30_2L_0_CLKREQ_N,
|
||||||
|
PCIE30_1L_1_WAKE_N, PCIE30_1L_1_CLKREQ_N, GPIO_P, WATCHDOG,
|
||||||
|
GPIO_RESET, GPIO_WPS, PMIC_I2C_SCL, PMIC_I2C_SDA, I2C_1_SCL,
|
||||||
|
I2C_1_SDA, PCIE30_2L_0_PRESET_N, PCIE30_1L_1_PRESET_N, PWMD1,
|
||||||
|
SPI0_WP, SPI0_HOLD, SPI0_CSB, SPI0_MISO, SPI0_MOSI, SPI0_CLK,
|
||||||
|
SPI1_CSB, SPI1_MISO, SPI1_MOSI, SPI1_CLK, SPI2_CLK, SPI2_MOSI,
|
||||||
|
SPI2_MISO, SPI2_CSB, SPI2_HOLD, SPI2_WP, EMMC_RSTB, EMMC_DSL,
|
||||||
|
EMMC_CK, EMMC_CMD, EMMC_DATA_7, EMMC_DATA_6, EMMC_DATA_5,
|
||||||
|
EMMC_DATA_4, EMMC_DATA_3, EMMC_DATA_2, EMMC_DATA_1,
|
||||||
|
EMMC_DATA_0, PCM_FS_I2S_LRCK, PCM_CLK_I2S_BCLK,
|
||||||
|
PCM_DRX_I2S_DIN, PCM_DTX_I2S_DOUT, PCM_MCK_I2S_MCLK,
|
||||||
|
UART0_RXD, UART0_TXD, PWMD0, JTAG_JTDI, JTAG_JTDO, JTAG_JTMS,
|
||||||
|
JTAG_JTCLK, JTAG_JTRST_N, USB_DRV_VBUS_P1, LED_A, LED_B, LED_C,
|
||||||
|
LED_D, LED_E, GPIO_B, GPIO_C, I2C_2_SCL, I2C_2_SDA,
|
||||||
|
PCIE30_2L_1_PRESET_N, PCIE30_1L_0_PRESET_N,
|
||||||
|
PCIE30_2L_1_WAKE_N, PCIE30_2L_1_CLKREQ_N,
|
||||||
|
PCIE30_1L_0_WAKE_N, PCIE30_1L_0_CLKREQ_N, USB_DRV_VBUS_P0,
|
||||||
|
UART1_RXD, UART1_TXD, UART1_CTS, UART1_RTS]
|
||||||
|
maxItems: 84
|
||||||
|
|
||||||
|
bias-disable: true
|
||||||
|
|
||||||
|
bias-pull-up:
|
||||||
|
oneOf:
|
||||||
|
- type: boolean
|
||||||
|
description: normal pull up.
|
||||||
|
- enum: [100, 101, 102, 103]
|
||||||
|
description:
|
||||||
|
PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
|
||||||
|
dt-bindings/pinctrl/mt65xx.h.
|
||||||
|
|
||||||
|
bias-pull-down:
|
||||||
|
oneOf:
|
||||||
|
- type: boolean
|
||||||
|
description: normal pull down.
|
||||||
|
- enum: [100, 101, 102, 103]
|
||||||
|
description:
|
||||||
|
PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
|
||||||
|
dt-bindings/pinctrl/mt65xx.h.
|
||||||
|
|
||||||
|
input-enable: true
|
||||||
|
|
||||||
|
input-disable: true
|
||||||
|
|
||||||
|
output-enable: true
|
||||||
|
|
||||||
|
output-low: true
|
||||||
|
|
||||||
|
output-high: true
|
||||||
|
|
||||||
|
input-schmitt-enable: true
|
||||||
|
|
||||||
|
input-schmitt-disable: true
|
||||||
|
|
||||||
|
drive-strength:
|
||||||
|
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||||
|
|
||||||
|
mediatek,pull-up-adv:
|
||||||
|
description: |
|
||||||
|
Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
|
||||||
|
Pull up settings for 2 pull resistors, R0 and R1. Valid arguments
|
||||||
|
are described as below:
|
||||||
|
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
|
||||||
|
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
|
||||||
|
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
|
||||||
|
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
enum: [0, 1, 2, 3]
|
||||||
|
|
||||||
|
mediatek,pull-down-adv:
|
||||||
|
description: |
|
||||||
|
Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
|
||||||
|
Pull down settings for 2 pull resistors, R0 and R1. Valid arguments
|
||||||
|
are described as below:
|
||||||
|
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
|
||||||
|
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
|
||||||
|
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
|
||||||
|
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
|
||||||
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
enum: [0, 1, 2, 3]
|
||||||
|
|
||||||
|
required:
|
||||||
|
- pins
|
||||||
|
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
#include <dt-bindings/interrupt-controller/irq.h>
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
#include <dt-bindings/pinctrl/mt65xx.h>
|
||||||
|
|
||||||
|
soc {
|
||||||
|
#address-cells = <2>;
|
||||||
|
#size-cells = <2>;
|
||||||
|
|
||||||
|
pio: pinctrl@1001f000 {
|
||||||
|
compatible = "mediatek,mt7988-pinctrl";
|
||||||
|
reg = <0 0x1001f000 0 0x1000>,
|
||||||
|
<0 0x11c10000 0 0x1000>,
|
||||||
|
<0 0x11d00000 0 0x1000>,
|
||||||
|
<0 0x11d20000 0 0x1000>,
|
||||||
|
<0 0x11e00000 0 0x1000>,
|
||||||
|
<0 0x11f00000 0 0x1000>,
|
||||||
|
<0 0x1000b000 0 0x1000>;
|
||||||
|
reg-names = "gpio", "iocfg_tr",
|
||||||
|
"iocfg_br", "iocfg_rb",
|
||||||
|
"iocfg_lb", "iocfg_tl", "eint";
|
||||||
|
gpio-controller;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
gpio-ranges = <&pio 0 0 84>;
|
||||||
|
interrupt-controller;
|
||||||
|
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
interrupt-parent = <&gic>;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
|
||||||
|
i2c0_pins: i2c0-g0-pins {
|
||||||
|
mux {
|
||||||
|
function = "i2c";
|
||||||
|
groups = "i2c0_1";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
mdio0_pins: mdio0-pins {
|
||||||
|
mux {
|
||||||
|
function = "eth";
|
||||||
|
groups = "mdc_mdio0";
|
||||||
|
};
|
||||||
|
|
||||||
|
conf {
|
||||||
|
pins = "SMI_0_MDC", "SMI_0_MDIO";
|
||||||
|
drive-strength = <8>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
mmc0_pins_emmc_51: mmc0-emmc-51-pins {
|
||||||
|
mux {
|
||||||
|
function = "flash";
|
||||||
|
groups = "emmc_51";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
mmc0_pins_sdcard: mmc0-sdcard-pins {
|
||||||
|
mux {
|
||||||
|
function = "flash";
|
||||||
|
groups = "sdcard";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pcie0_pins: pcie0-pins {
|
||||||
|
mux {
|
||||||
|
function = "pcie";
|
||||||
|
groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
|
||||||
|
"pcie_wake_n0_0";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pcie1_pins: pcie1-pins {
|
||||||
|
mux {
|
||||||
|
function = "pcie";
|
||||||
|
groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
|
||||||
|
"pcie_wake_n1_0";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pcie2_pins: pcie2-pins {
|
||||||
|
mux {
|
||||||
|
function = "pcie";
|
||||||
|
groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
|
||||||
|
"pcie_wake_n2_0";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pcie3_pins: pcie3-pins {
|
||||||
|
mux {
|
||||||
|
function = "pcie";
|
||||||
|
groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
|
||||||
|
"pcie_wake_n3_0";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
uart0_pins: uart0-pins {
|
||||||
|
mux {
|
||||||
|
function = "uart";
|
||||||
|
groups = "uart0";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -79,8 +79,8 @@ $defs:
|
||||||
qdss_cti_trig_out_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_b1,
|
qdss_cti_trig_out_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_b1,
|
||||||
qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_clk,
|
qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_clk,
|
||||||
qspi_cs, qspi_data, resout, rx0, rx1, rx2, sdc_clk, sdc_cmd,
|
qspi_cs, qspi_data, resout, rx0, rx1, rx2, sdc_clk, sdc_cmd,
|
||||||
sdc_data, spi0, spi1, spi10, spi11, tsens_max, uart0, uart1,
|
sdc_data, spi0_cs, spi0_clk, spi0_miso, spi0_mosi, spi1, spi10,
|
||||||
wci_txd, wci_rxd, wsi_clk, wsi_data ]
|
spi11, tsens_max, uart0, uart1, wci_txd, wci_rxd, wsi_clk, wsi_data ]
|
||||||
|
|
||||||
required:
|
required:
|
||||||
- pins
|
- pins
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,160 @@
|
||||||
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||||
|
%YAML 1.2
|
||||||
|
---
|
||||||
|
$id: http://devicetree.org/schemas/pinctrl/qcom,msm8917-pinctrl.yaml#
|
||||||
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||||
|
|
||||||
|
title: Qualcomm MSM8917 TLMM pin controller
|
||||||
|
|
||||||
|
maintainers:
|
||||||
|
- Barnabas Czeman <barnabas.czeman@mainlining.org>
|
||||||
|
|
||||||
|
description:
|
||||||
|
Top Level Mode Multiplexer pin controller in Qualcomm MSM8917 SoC.
|
||||||
|
|
||||||
|
properties:
|
||||||
|
compatible:
|
||||||
|
const: qcom,msm8917-pinctrl
|
||||||
|
|
||||||
|
reg:
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
interrupts:
|
||||||
|
maxItems: 1
|
||||||
|
|
||||||
|
gpio-reserved-ranges:
|
||||||
|
minItems: 1
|
||||||
|
maxItems: 66
|
||||||
|
|
||||||
|
gpio-line-names:
|
||||||
|
maxItems: 134
|
||||||
|
|
||||||
|
patternProperties:
|
||||||
|
"-state$":
|
||||||
|
oneOf:
|
||||||
|
- $ref: "#/$defs/qcom-msm8917-tlmm-state"
|
||||||
|
- patternProperties:
|
||||||
|
"-pins$":
|
||||||
|
$ref: "#/$defs/qcom-msm8917-tlmm-state"
|
||||||
|
additionalProperties: false
|
||||||
|
|
||||||
|
$defs:
|
||||||
|
qcom-msm8917-tlmm-state:
|
||||||
|
type: object
|
||||||
|
description:
|
||||||
|
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||||
|
Client device subnodes use below standard properties.
|
||||||
|
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||||
|
unevaluatedProperties: false
|
||||||
|
|
||||||
|
properties:
|
||||||
|
pins:
|
||||||
|
description:
|
||||||
|
List of gpio pins affected by the properties specified in this
|
||||||
|
subnode.
|
||||||
|
items:
|
||||||
|
oneOf:
|
||||||
|
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-2][0-9]|13[0-3])$"
|
||||||
|
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
|
||||||
|
sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0,
|
||||||
|
qdsd_data1, qdsd_data2, qdsd_data3 ]
|
||||||
|
minItems: 1
|
||||||
|
maxItems: 16
|
||||||
|
|
||||||
|
function:
|
||||||
|
description:
|
||||||
|
Specify the alternative function to be configured for the specified
|
||||||
|
pins.
|
||||||
|
|
||||||
|
enum: [ accel_int, adsp_ext, alsp_int, atest_bbrx0, atest_bbrx1,
|
||||||
|
atest_char, atest_char0, atest_char1, atest_char2,
|
||||||
|
atest_char3, atest_combodac_to_gpio_native,
|
||||||
|
atest_gpsadc_dtest0_native, atest_gpsadc_dtest1_native,
|
||||||
|
atest_tsens, atest_wlan0, atest_wlan1, audio_ref,
|
||||||
|
audio_reset, bimc_dte0, bimc_dte1, blsp6_spi, blsp8_spi,
|
||||||
|
blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
|
||||||
|
blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_spi1, blsp_spi2,
|
||||||
|
blsp_spi3, blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7,
|
||||||
|
blsp_spi8, blsp_uart1, blsp_uart2, blsp_uart3, blsp_uart4,
|
||||||
|
blsp_uart5, blsp_uart6, blsp_uart7, blsp_uart8, cam0_ldo,
|
||||||
|
cam1_rst, cam1_standby, cam2_rst, cam2_standby, cam_mclk,
|
||||||
|
cci_async, cci_i2c, cci_timer0, cci_timer1, cdc_pdm0,
|
||||||
|
codec_int1, codec_int2, codec_mad, coex_uart, cri_trng,
|
||||||
|
cri_trng0, cri_trng1, dbg_out, dmic0_clk, dmic0_data,
|
||||||
|
ebi_cdc, ebi_ch0, ext_lpass, forced_usb, fp_gpio, fp_int,
|
||||||
|
gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b,
|
||||||
|
gcc_gp3_clk_a, gcc_gp3_clk_b, gcc_plltest, gcc_tlmm, gpio,
|
||||||
|
gsm0_tx, key_focus, key_snapshot, key_volp, ldo_en,
|
||||||
|
ldo_update, lpass_slimbus, lpass_slimbus0, lpass_slimbus1,
|
||||||
|
m_voc, mag_int, mdp_vsync, mipi_dsi0, modem_tsync, nav_pps,
|
||||||
|
nav_pps_in_a, nav_pps_in_b, nav_tsync, nfc_pwr, ov_ldo,
|
||||||
|
pa_indicator, pbs0, pbs1, pbs2, pri_mi2s, pri_mi2s_mclk_a,
|
||||||
|
pri_mi2s_mclk_b, pri_mi2s_ws, prng_rosc,
|
||||||
|
pwr_crypto_enabled_a, pwr_crypto_enabled_b,
|
||||||
|
pwr_modem_enabled_a, pwr_modem_enabled_b, pwr_nav_enabled_a,
|
||||||
|
pwr_nav_enabled_b, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
|
||||||
|
qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
|
||||||
|
qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
|
||||||
|
qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
|
||||||
|
qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
|
||||||
|
qdss_tracedata_a, qdss_tracedata_b, sd_write, sdcard_det,
|
||||||
|
sec_mi2s, sec_mi2s_mclk_a, sec_mi2s_mclk_b, sensor_rst,
|
||||||
|
smb_int, ssbi_wtr1, ts_resout, ts_sample, uim1_clk,
|
||||||
|
uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
|
||||||
|
uim2_present, uim2_reset, uim_batt, us_emitter, us_euro,
|
||||||
|
wcss_bt, wcss_fm, wcss_wlan, wcss_wlan0, wcss_wlan1,
|
||||||
|
wcss_wlan2, webcam_rst, webcam_standby, wsa_io, wsa_irq ]
|
||||||
|
|
||||||
|
required:
|
||||||
|
- pins
|
||||||
|
|
||||||
|
allOf:
|
||||||
|
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||||
|
|
||||||
|
required:
|
||||||
|
- compatible
|
||||||
|
- reg
|
||||||
|
|
||||||
|
unevaluatedProperties: false
|
||||||
|
|
||||||
|
examples:
|
||||||
|
- |
|
||||||
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||||
|
|
||||||
|
tlmm: pinctrl@1000000 {
|
||||||
|
compatible = "qcom,msm8917-pinctrl";
|
||||||
|
reg = <0x01000000 0x300000>;
|
||||||
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
|
gpio-controller;
|
||||||
|
gpio-ranges = <&tlmm 0 0 134>;
|
||||||
|
#gpio-cells = <2>;
|
||||||
|
interrupt-controller;
|
||||||
|
#interrupt-cells = <2>;
|
||||||
|
|
||||||
|
blsp1-uart2-sleep-state {
|
||||||
|
pins = "gpio4", "gpio5";
|
||||||
|
function = "gpio";
|
||||||
|
|
||||||
|
drive-strength = <2>;
|
||||||
|
bias-pull-down;
|
||||||
|
};
|
||||||
|
|
||||||
|
spi1-default-state {
|
||||||
|
spi-pins {
|
||||||
|
pins = "gpio0", "gpio1", "gpio3";
|
||||||
|
function = "blsp_spi1";
|
||||||
|
|
||||||
|
drive-strength = <12>;
|
||||||
|
bias-disable;
|
||||||
|
};
|
||||||
|
|
||||||
|
cs-pins {
|
||||||
|
pins = "gpio2";
|
||||||
|
function = "gpio";
|
||||||
|
|
||||||
|
drive-strength = <16>;
|
||||||
|
bias-disable;
|
||||||
|
output-high;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
@ -159,30 +159,30 @@ additionalProperties: false
|
||||||
|
|
||||||
examples:
|
examples:
|
||||||
- |
|
- |
|
||||||
pinctrl@4e000 {
|
pinctrl@4e000 {
|
||||||
compatible = "realtek,rtd1315e-pinctrl";
|
compatible = "realtek,rtd1315e-pinctrl";
|
||||||
reg = <0x4e000 0x130>;
|
reg = <0x4e000 0x130>;
|
||||||
|
|
||||||
emmc-hs200-pins {
|
emmc-hs200-pins {
|
||||||
pins = "emmc_clk",
|
pins = "emmc_clk",
|
||||||
"emmc_cmd",
|
"emmc_cmd",
|
||||||
"emmc_data_0",
|
"emmc_data_0",
|
||||||
"emmc_data_1",
|
"emmc_data_1",
|
||||||
"emmc_data_2",
|
"emmc_data_2",
|
||||||
"emmc_data_3",
|
"emmc_data_3",
|
||||||
"emmc_data_4",
|
"emmc_data_4",
|
||||||
"emmc_data_5",
|
"emmc_data_5",
|
||||||
"emmc_data_6",
|
"emmc_data_6",
|
||||||
"emmc_data_7";
|
"emmc_data_7";
|
||||||
function = "emmc";
|
function = "emmc";
|
||||||
realtek,drive-strength-p = <0x2>;
|
realtek,drive-strength-p = <0x2>;
|
||||||
realtek,drive-strength-n = <0x2>;
|
realtek,drive-strength-n = <0x2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c-0-pins {
|
i2c-0-pins {
|
||||||
pins = "gpio_12",
|
pins = "gpio_12",
|
||||||
"gpio_13";
|
"gpio_13";
|
||||||
function = "i2c0";
|
function = "i2c0";
|
||||||
drive-strength = <4>;
|
drive-strength = <4>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -158,30 +158,30 @@ additionalProperties: false
|
||||||
|
|
||||||
examples:
|
examples:
|
||||||
- |
|
- |
|
||||||
pinctrl@4e000 {
|
pinctrl@4e000 {
|
||||||
compatible = "realtek,rtd1319d-pinctrl";
|
compatible = "realtek,rtd1319d-pinctrl";
|
||||||
reg = <0x4e000 0x130>;
|
reg = <0x4e000 0x130>;
|
||||||
|
|
||||||
emmc-hs200-pins {
|
emmc-hs200-pins {
|
||||||
pins = "emmc_clk",
|
pins = "emmc_clk",
|
||||||
"emmc_cmd",
|
"emmc_cmd",
|
||||||
"emmc_data_0",
|
"emmc_data_0",
|
||||||
"emmc_data_1",
|
"emmc_data_1",
|
||||||
"emmc_data_2",
|
"emmc_data_2",
|
||||||
"emmc_data_3",
|
"emmc_data_3",
|
||||||
"emmc_data_4",
|
"emmc_data_4",
|
||||||
"emmc_data_5",
|
"emmc_data_5",
|
||||||
"emmc_data_6",
|
"emmc_data_6",
|
||||||
"emmc_data_7";
|
"emmc_data_7";
|
||||||
function = "emmc";
|
function = "emmc";
|
||||||
realtek,drive-strength-p = <0x2>;
|
realtek,drive-strength-p = <0x2>;
|
||||||
realtek,drive-strength-n = <0x2>;
|
realtek,drive-strength-n = <0x2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c-0-pins {
|
i2c-0-pins {
|
||||||
pins = "gpio_12",
|
pins = "gpio_12",
|
||||||
"gpio_13";
|
"gpio_13";
|
||||||
function = "i2c0";
|
function = "i2c0";
|
||||||
drive-strength = <4>;
|
drive-strength = <4>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -157,30 +157,30 @@ additionalProperties: false
|
||||||
|
|
||||||
examples:
|
examples:
|
||||||
- |
|
- |
|
||||||
pinctrl@4e000 {
|
pinctrl@4e000 {
|
||||||
compatible = "realtek,rtd1619b-pinctrl";
|
compatible = "realtek,rtd1619b-pinctrl";
|
||||||
reg = <0x4e000 0x130>;
|
reg = <0x4e000 0x130>;
|
||||||
|
|
||||||
emmc-hs200-pins {
|
emmc-hs200-pins {
|
||||||
pins = "emmc_clk",
|
pins = "emmc_clk",
|
||||||
"emmc_cmd",
|
"emmc_cmd",
|
||||||
"emmc_data_0",
|
"emmc_data_0",
|
||||||
"emmc_data_1",
|
"emmc_data_1",
|
||||||
"emmc_data_2",
|
"emmc_data_2",
|
||||||
"emmc_data_3",
|
"emmc_data_3",
|
||||||
"emmc_data_4",
|
"emmc_data_4",
|
||||||
"emmc_data_5",
|
"emmc_data_5",
|
||||||
"emmc_data_6",
|
"emmc_data_6",
|
||||||
"emmc_data_7";
|
"emmc_data_7";
|
||||||
function = "emmc";
|
function = "emmc";
|
||||||
realtek,drive-strength-p = <0x2>;
|
realtek,drive-strength-p = <0x2>;
|
||||||
realtek,drive-strength-n = <0x2>;
|
realtek,drive-strength-n = <0x2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c-0-pins {
|
i2c-0-pins {
|
||||||
pins = "gpio_12",
|
pins = "gpio_12",
|
||||||
"gpio_13";
|
"gpio_13";
|
||||||
function = "i2c0";
|
function = "i2c0";
|
||||||
drive-strength = <4>;
|
drive-strength = <4>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
|
||||||
|
|
@ -26,6 +26,7 @@ properties:
|
||||||
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
|
- renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five
|
||||||
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
|
- renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
|
||||||
- renesas,r9a08g045-pinctrl # RZ/G3S
|
- renesas,r9a08g045-pinctrl # RZ/G3S
|
||||||
|
- renesas,r9a09g047-pinctrl # RZ/G3E
|
||||||
- renesas,r9a09g057-pinctrl # RZ/V2H(P)
|
- renesas,r9a09g057-pinctrl # RZ/V2H(P)
|
||||||
|
|
||||||
- items:
|
- items:
|
||||||
|
|
@ -125,7 +126,7 @@ additionalProperties:
|
||||||
drive-push-pull: true
|
drive-push-pull: true
|
||||||
renesas,output-impedance:
|
renesas,output-impedance:
|
||||||
description:
|
description:
|
||||||
Output impedance for pins on the RZ/V2H(P) SoC. The value provided by this
|
Output impedance for pins on the RZ/{G3E,V2H(P)} SoC. The value provided by this
|
||||||
property corresponds to register bit values that can be set in the PFC_IOLH_mn
|
property corresponds to register bit values that can be set in the PFC_IOLH_mn
|
||||||
register, which adjusts the drive strength value and is pin-dependent.
|
register, which adjusts the drive strength value and is pin-dependent.
|
||||||
$ref: /schemas/types.yaml#/definitions/uint32
|
$ref: /schemas/types.yaml#/definitions/uint32
|
||||||
|
|
@ -142,7 +143,9 @@ allOf:
|
||||||
properties:
|
properties:
|
||||||
compatible:
|
compatible:
|
||||||
contains:
|
contains:
|
||||||
const: renesas,r9a09g057-pinctrl
|
enum:
|
||||||
|
- renesas,r9a09g047-pinctrl
|
||||||
|
- renesas,r9a09g057-pinctrl
|
||||||
then:
|
then:
|
||||||
properties:
|
properties:
|
||||||
resets:
|
resets:
|
||||||
|
|
|
||||||
|
|
@ -44,6 +44,7 @@ properties:
|
||||||
- rockchip,rk3328-pinctrl
|
- rockchip,rk3328-pinctrl
|
||||||
- rockchip,rk3368-pinctrl
|
- rockchip,rk3368-pinctrl
|
||||||
- rockchip,rk3399-pinctrl
|
- rockchip,rk3399-pinctrl
|
||||||
|
- rockchip,rk3562-pinctrl
|
||||||
- rockchip,rk3568-pinctrl
|
- rockchip,rk3568-pinctrl
|
||||||
- rockchip,rk3576-pinctrl
|
- rockchip,rk3576-pinctrl
|
||||||
- rockchip,rk3588-pinctrl
|
- rockchip,rk3588-pinctrl
|
||||||
|
|
|
||||||
|
|
@ -180,38 +180,31 @@ additionalProperties: false
|
||||||
examples:
|
examples:
|
||||||
- |
|
- |
|
||||||
#include <dt-bindings/pinctrl/pinctrl-zynq.h>
|
#include <dt-bindings/pinctrl/pinctrl-zynq.h>
|
||||||
pinctrl0: pinctrl@700 {
|
pinctrl@700 {
|
||||||
compatible = "xlnx,pinctrl-zynq";
|
compatible = "xlnx,pinctrl-zynq";
|
||||||
reg = <0x700 0x200>;
|
reg = <0x700 0x200>;
|
||||||
syscon = <&slcr>;
|
syscon = <&slcr>;
|
||||||
|
|
||||||
pinctrl_uart1_default: uart1-default {
|
uart1-default {
|
||||||
mux {
|
mux {
|
||||||
groups = "uart1_10_grp";
|
groups = "uart1_10_grp";
|
||||||
function = "uart1";
|
function = "uart1";
|
||||||
};
|
};
|
||||||
|
|
||||||
conf {
|
conf {
|
||||||
groups = "uart1_10_grp";
|
groups = "uart1_10_grp";
|
||||||
slew-rate = <0>;
|
slew-rate = <0>;
|
||||||
power-source = <IO_STANDARD_LVCMOS18>;
|
power-source = <IO_STANDARD_LVCMOS18>;
|
||||||
};
|
};
|
||||||
|
|
||||||
conf-rx {
|
conf-rx {
|
||||||
pins = "MIO49";
|
pins = "MIO49";
|
||||||
bias-high-impedance;
|
bias-high-impedance;
|
||||||
};
|
};
|
||||||
|
|
||||||
conf-tx {
|
conf-tx {
|
||||||
pins = "MIO48";
|
pins = "MIO48";
|
||||||
bias-disable;
|
bias-disable;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
uart1 {
|
|
||||||
pinctrl-names = "default";
|
|
||||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
|
||||||
};
|
|
||||||
|
|
||||||
...
|
|
||||||
|
|
|
||||||
|
|
@ -21,6 +21,7 @@
|
||||||
#include <linux/pinctrl/pinctrl.h>
|
#include <linux/pinctrl/pinctrl.h>
|
||||||
#include <linux/platform_device.h>
|
#include <linux/platform_device.h>
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
|
#include <linux/string_choices.h>
|
||||||
|
|
||||||
#include "../pinctrl-utils.h"
|
#include "../pinctrl-utils.h"
|
||||||
|
|
||||||
|
|
@ -254,7 +255,7 @@ static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
|
||||||
raw_spin_unlock_irqrestore(&chip->lock, flags);
|
raw_spin_unlock_irqrestore(&chip->lock, flags);
|
||||||
|
|
||||||
dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
|
dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
|
||||||
level_low ? "true" : "false", falling ? "true" : "false");
|
str_true_false(level_low), str_true_false(falling));
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -15,6 +15,7 @@
|
||||||
#include <linux/of.h>
|
#include <linux/of.h>
|
||||||
#include <linux/platform_device.h>
|
#include <linux/platform_device.h>
|
||||||
#include <linux/regmap.h>
|
#include <linux/regmap.h>
|
||||||
|
#include <linux/string_choices.h>
|
||||||
|
|
||||||
#include <linux/pinctrl/consumer.h>
|
#include <linux/pinctrl/consumer.h>
|
||||||
#include <linux/pinctrl/pinconf-generic.h>
|
#include <linux/pinctrl/pinconf-generic.h>
|
||||||
|
|
@ -1068,7 +1069,7 @@ static void lochnagar_gpio_set(struct gpio_chip *chip,
|
||||||
value = !!value;
|
value = !!value;
|
||||||
|
|
||||||
dev_dbg(priv->dev, "Set GPIO %s to %s\n",
|
dev_dbg(priv->dev, "Set GPIO %s to %s\n",
|
||||||
pin->name, value ? "high" : "low");
|
pin->name, str_high_low(value));
|
||||||
|
|
||||||
switch (pin->type) {
|
switch (pin->type) {
|
||||||
case LN_PTYPE_MUX:
|
case LN_PTYPE_MUX:
|
||||||
|
|
|
||||||
|
|
@ -1256,6 +1256,20 @@ static void pinctrl_link_add(struct pinctrl_dev *pctldev,
|
||||||
DL_FLAG_AUTOREMOVE_CONSUMER);
|
DL_FLAG_AUTOREMOVE_CONSUMER);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void pinctrl_cond_disable_mux_setting(struct pinctrl_state *state,
|
||||||
|
struct pinctrl_setting *target_setting)
|
||||||
|
{
|
||||||
|
struct pinctrl_setting *setting;
|
||||||
|
|
||||||
|
list_for_each_entry(setting, &state->settings, node) {
|
||||||
|
if (target_setting && (&setting->node == &target_setting->node))
|
||||||
|
break;
|
||||||
|
|
||||||
|
if (setting->type == PIN_MAP_TYPE_MUX_GROUP)
|
||||||
|
pinmux_disable_setting(setting);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* pinctrl_commit_state() - select/activate/program a pinctrl state to HW
|
* pinctrl_commit_state() - select/activate/program a pinctrl state to HW
|
||||||
* @p: the pinctrl handle for the device that requests configuration
|
* @p: the pinctrl handle for the device that requests configuration
|
||||||
|
|
@ -1263,7 +1277,7 @@ static void pinctrl_link_add(struct pinctrl_dev *pctldev,
|
||||||
*/
|
*/
|
||||||
static int pinctrl_commit_state(struct pinctrl *p, struct pinctrl_state *state)
|
static int pinctrl_commit_state(struct pinctrl *p, struct pinctrl_state *state)
|
||||||
{
|
{
|
||||||
struct pinctrl_setting *setting, *setting2;
|
struct pinctrl_setting *setting;
|
||||||
struct pinctrl_state *old_state = READ_ONCE(p->state);
|
struct pinctrl_state *old_state = READ_ONCE(p->state);
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
|
|
@ -1274,11 +1288,7 @@ static int pinctrl_commit_state(struct pinctrl *p, struct pinctrl_state *state)
|
||||||
* still owned by the new state will be re-acquired by the call
|
* still owned by the new state will be re-acquired by the call
|
||||||
* to pinmux_enable_setting() in the loop below.
|
* to pinmux_enable_setting() in the loop below.
|
||||||
*/
|
*/
|
||||||
list_for_each_entry(setting, &old_state->settings, node) {
|
pinctrl_cond_disable_mux_setting(old_state, NULL);
|
||||||
if (setting->type != PIN_MAP_TYPE_MUX_GROUP)
|
|
||||||
continue;
|
|
||||||
pinmux_disable_setting(setting);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
p->state = NULL;
|
p->state = NULL;
|
||||||
|
|
@ -1322,7 +1332,7 @@ static int pinctrl_commit_state(struct pinctrl *p, struct pinctrl_state *state)
|
||||||
}
|
}
|
||||||
|
|
||||||
if (ret < 0) {
|
if (ret < 0) {
|
||||||
goto unapply_new_state;
|
goto unapply_mux_setting;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Do not link hogs (circular dependency) */
|
/* Do not link hogs (circular dependency) */
|
||||||
|
|
@ -1334,23 +1344,23 @@ static int pinctrl_commit_state(struct pinctrl *p, struct pinctrl_state *state)
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
|
unapply_mux_setting:
|
||||||
|
pinctrl_cond_disable_mux_setting(state, NULL);
|
||||||
|
goto restore_old_state;
|
||||||
|
|
||||||
unapply_new_state:
|
unapply_new_state:
|
||||||
dev_err(p->dev, "Error applying setting, reverse things back\n");
|
dev_err(p->dev, "Error applying setting, reverse things back\n");
|
||||||
|
|
||||||
list_for_each_entry(setting2, &state->settings, node) {
|
/*
|
||||||
if (&setting2->node == &setting->node)
|
* All we can do here is pinmux_disable_setting.
|
||||||
break;
|
* That means that some pins are muxed differently now
|
||||||
/*
|
* than they were before applying the setting (We can't
|
||||||
* All we can do here is pinmux_disable_setting.
|
* "unmux a pin"!), but it's not a big deal since the pins
|
||||||
* That means that some pins are muxed differently now
|
* are free to be muxed by another apply_setting.
|
||||||
* than they were before applying the setting (We can't
|
*/
|
||||||
* "unmux a pin"!), but it's not a big deal since the pins
|
pinctrl_cond_disable_mux_setting(state, setting);
|
||||||
* are free to be muxed by another apply_setting.
|
|
||||||
*/
|
|
||||||
if (setting2->type == PIN_MAP_TYPE_MUX_GROUP)
|
|
||||||
pinmux_disable_setting(setting2);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
restore_old_state:
|
||||||
/* There's no infinite recursive loop here because p->state is NULL */
|
/* There's no infinite recursive loop here because p->state is NULL */
|
||||||
if (old_state)
|
if (old_state)
|
||||||
pinctrl_select_state(p, old_state);
|
pinctrl_select_state(p, old_state);
|
||||||
|
|
|
||||||
|
|
@ -202,6 +202,13 @@ config PINCTRL_MT7986
|
||||||
default ARM64 && ARCH_MEDIATEK
|
default ARM64 && ARCH_MEDIATEK
|
||||||
select PINCTRL_MTK_MOORE
|
select PINCTRL_MTK_MOORE
|
||||||
|
|
||||||
|
config PINCTRL_MT7988
|
||||||
|
bool "Mediatek MT7988 pin control"
|
||||||
|
depends on OF
|
||||||
|
depends on ARM64 || COMPILE_TEST
|
||||||
|
default ARM64 && ARCH_MEDIATEK
|
||||||
|
select PINCTRL_MTK_MOORE
|
||||||
|
|
||||||
config PINCTRL_MT8167
|
config PINCTRL_MT8167
|
||||||
bool "MediaTek MT8167 pin control"
|
bool "MediaTek MT8167 pin control"
|
||||||
depends on OF
|
depends on OF
|
||||||
|
|
|
||||||
|
|
@ -28,6 +28,7 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
|
||||||
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
|
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
|
||||||
obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
|
obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
|
||||||
obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
|
obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
|
||||||
|
obj-$(CONFIG_PINCTRL_MT7988) += pinctrl-mt7988.o
|
||||||
obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
|
obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
|
||||||
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
|
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
|
||||||
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
|
obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o
|
||||||
|
|
|
||||||
1556
drivers/pinctrl/mediatek/pinctrl-mt7988.c
Normal file
1556
drivers/pinctrl/mediatek/pinctrl-mt7988.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -573,7 +573,7 @@ EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_rev1);
|
||||||
*/
|
*/
|
||||||
static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw,
|
static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw,
|
||||||
const struct mtk_pin_desc *desc,
|
const struct mtk_pin_desc *desc,
|
||||||
u32 pullup, u32 arg)
|
u32 pullup, u32 arg, bool pd_only)
|
||||||
{
|
{
|
||||||
int err, pu, pd;
|
int err, pu, pd;
|
||||||
|
|
||||||
|
|
@ -587,18 +587,16 @@ static int mtk_pinconf_bias_set_pu_pd(struct mtk_pinctrl *hw,
|
||||||
pu = 0;
|
pu = 0;
|
||||||
pd = 1;
|
pd = 1;
|
||||||
} else {
|
} else {
|
||||||
err = -EINVAL;
|
return -EINVAL;
|
||||||
goto out;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu);
|
if (!pd_only) {
|
||||||
if (err)
|
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PU, pu);
|
||||||
goto out;
|
if (err)
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
|
return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_PD, pd);
|
||||||
|
|
||||||
out:
|
|
||||||
return err;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
|
static int mtk_pinconf_bias_set_pullsel_pullen(struct mtk_pinctrl *hw,
|
||||||
|
|
@ -737,7 +735,7 @@ static int mtk_pinconf_bias_set_pu_pd_rsel(struct mtk_pinctrl *hw,
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable);
|
return mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, enable, false);
|
||||||
}
|
}
|
||||||
|
|
||||||
int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
|
int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
|
||||||
|
|
@ -758,8 +756,14 @@ int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw,
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (try_all_type & MTK_PULL_PD_TYPE) {
|
||||||
|
err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, true);
|
||||||
|
if (!err)
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
if (try_all_type & MTK_PULL_PU_PD_TYPE) {
|
if (try_all_type & MTK_PULL_PU_PD_TYPE) {
|
||||||
err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg);
|
err = mtk_pinconf_bias_set_pu_pd(hw, desc, pullup, arg, false);
|
||||||
if (!err)
|
if (!err)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
@ -878,6 +882,29 @@ out:
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int mtk_pinconf_bias_get_pd(struct mtk_pinctrl *hw,
|
||||||
|
const struct mtk_pin_desc *desc,
|
||||||
|
u32 *pullup, u32 *enable)
|
||||||
|
{
|
||||||
|
int err, pd;
|
||||||
|
|
||||||
|
err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_PD, &pd);
|
||||||
|
if (err)
|
||||||
|
goto out;
|
||||||
|
|
||||||
|
if (pd == 0) {
|
||||||
|
*pullup = 0;
|
||||||
|
*enable = MTK_DISABLE;
|
||||||
|
} else if (pd == 1) {
|
||||||
|
*pullup = 0;
|
||||||
|
*enable = MTK_ENABLE;
|
||||||
|
} else
|
||||||
|
err = -EINVAL;
|
||||||
|
|
||||||
|
out:
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
|
static int mtk_pinconf_bias_get_pullsel_pullen(struct mtk_pinctrl *hw,
|
||||||
const struct mtk_pin_desc *desc,
|
const struct mtk_pin_desc *desc,
|
||||||
u32 *pullup, u32 *enable)
|
u32 *pullup, u32 *enable)
|
||||||
|
|
@ -947,6 +974,12 @@ int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw,
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if (try_all_type & MTK_PULL_PD_TYPE) {
|
||||||
|
err = mtk_pinconf_bias_get_pd(hw, desc, pullup, enable);
|
||||||
|
if (!err)
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
if (try_all_type & MTK_PULL_PU_PD_TYPE) {
|
if (try_all_type & MTK_PULL_PU_PD_TYPE) {
|
||||||
err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
|
err = mtk_pinconf_bias_get_pu_pd(hw, desc, pullup, enable);
|
||||||
if (!err)
|
if (!err)
|
||||||
|
|
|
||||||
|
|
@ -24,6 +24,7 @@
|
||||||
* turned on/off itself. But it can't be selected pull up/down
|
* turned on/off itself. But it can't be selected pull up/down
|
||||||
*/
|
*/
|
||||||
#define MTK_PULL_RSEL_TYPE BIT(3)
|
#define MTK_PULL_RSEL_TYPE BIT(3)
|
||||||
|
#define MTK_PULL_PD_TYPE BIT(4)
|
||||||
/* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by
|
/* MTK_PULL_PU_PD_RSEL_TYPE is a type which is controlled by
|
||||||
* MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE.
|
* MTK_PULL_PU_PD_TYPE and MTK_PULL_RSEL_TYPE.
|
||||||
*/
|
*/
|
||||||
|
|
|
||||||
|
|
@ -22,6 +22,7 @@
|
||||||
#include <linux/property.h>
|
#include <linux/property.h>
|
||||||
#include <linux/seq_file.h>
|
#include <linux/seq_file.h>
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
|
#include <linux/string_choices.h>
|
||||||
#include <linux/types.h>
|
#include <linux/types.h>
|
||||||
|
|
||||||
#include <linux/mfd/abx500.h>
|
#include <linux/mfd/abx500.h>
|
||||||
|
|
@ -496,7 +497,7 @@ static void abx500_gpio_dbg_show_one(struct seq_file *s,
|
||||||
|
|
||||||
seq_printf(s, " %-9s", pull_up_down[pd]);
|
seq_printf(s, " %-9s", pull_up_down[pd]);
|
||||||
} else
|
} else
|
||||||
seq_printf(s, " %-9s", chip->get(chip, offset) ? "hi" : "lo");
|
seq_printf(s, " %-9s", str_hi_lo(chip->get(chip, offset)));
|
||||||
|
|
||||||
mode = abx500_get_mode(pctldev, chip, offset);
|
mode = abx500_get_mode(pctldev, chip, offset);
|
||||||
|
|
||||||
|
|
@ -865,7 +866,7 @@ static int abx500_pin_config_set(struct pinctrl_dev *pctldev,
|
||||||
pin, configs[i],
|
pin, configs[i],
|
||||||
(param == PIN_CONFIG_OUTPUT) ? "output " : "input",
|
(param == PIN_CONFIG_OUTPUT) ? "output " : "input",
|
||||||
(param == PIN_CONFIG_OUTPUT) ?
|
(param == PIN_CONFIG_OUTPUT) ?
|
||||||
(argument ? "high" : "low") :
|
str_high_low(argument) :
|
||||||
(argument ? "pull up" : "pull down"));
|
(argument ? "pull up" : "pull down"));
|
||||||
|
|
||||||
/* on ABx500, there is no GPIO0, so adjust the offset */
|
/* on ABx500, there is no GPIO0, so adjust the offset */
|
||||||
|
|
|
||||||
|
|
@ -28,6 +28,7 @@
|
||||||
#include <linux/seq_file.h>
|
#include <linux/seq_file.h>
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
#include <linux/spinlock.h>
|
#include <linux/spinlock.h>
|
||||||
|
#include <linux/string_choices.h>
|
||||||
#include <linux/types.h>
|
#include <linux/types.h>
|
||||||
|
|
||||||
/* Since we request GPIOs from ourself */
|
/* Since we request GPIOs from ourself */
|
||||||
|
|
@ -438,9 +439,9 @@ static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
|
||||||
* - Any spurious wake up event during switch sequence to be ignored and
|
* - Any spurious wake up event during switch sequence to be ignored and
|
||||||
* cleared
|
* cleared
|
||||||
*/
|
*/
|
||||||
static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
|
static int nmk_gpio_glitch_slpm_init(unsigned int *slpm)
|
||||||
{
|
{
|
||||||
int i;
|
int i, j, ret;
|
||||||
|
|
||||||
for (i = 0; i < NMK_MAX_BANKS; i++) {
|
for (i = 0; i < NMK_MAX_BANKS; i++) {
|
||||||
struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
|
struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
|
||||||
|
|
@ -449,11 +450,21 @@ static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
|
||||||
if (!chip)
|
if (!chip)
|
||||||
break;
|
break;
|
||||||
|
|
||||||
clk_enable(chip->clk);
|
ret = clk_enable(chip->clk);
|
||||||
|
if (ret) {
|
||||||
|
for (j = 0; j < i; j++) {
|
||||||
|
chip = nmk_gpio_chips[j];
|
||||||
|
clk_disable(chip->clk);
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
|
slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
|
||||||
writel(temp, chip->addr + NMK_GPIO_SLPC);
|
writel(temp, chip->addr + NMK_GPIO_SLPC);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
|
static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
|
||||||
|
|
@ -923,7 +934,9 @@ static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned int function,
|
||||||
|
|
||||||
slpm[nmk_chip->bank] &= ~BIT(bit);
|
slpm[nmk_chip->bank] &= ~BIT(bit);
|
||||||
}
|
}
|
||||||
nmk_gpio_glitch_slpm_init(slpm);
|
ret = nmk_gpio_glitch_slpm_init(slpm);
|
||||||
|
if (ret)
|
||||||
|
goto out_pre_slpm_init;
|
||||||
}
|
}
|
||||||
|
|
||||||
for (i = 0; i < g->grp.npins; i++) {
|
for (i = 0; i < g->grp.npins; i++) {
|
||||||
|
|
@ -940,7 +953,10 @@ static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned int function,
|
||||||
dev_dbg(npct->dev, "setting pin %d to altsetting %d\n",
|
dev_dbg(npct->dev, "setting pin %d to altsetting %d\n",
|
||||||
g->grp.pins[i], g->altsetting);
|
g->grp.pins[i], g->altsetting);
|
||||||
|
|
||||||
clk_enable(nmk_chip->clk);
|
ret = clk_enable(nmk_chip->clk);
|
||||||
|
if (ret)
|
||||||
|
goto out_glitch;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* If the pin is switching to altfunc, and there was an
|
* If the pin is switching to altfunc, and there was an
|
||||||
* interrupt installed on it which has been lazy disabled,
|
* interrupt installed on it which has been lazy disabled,
|
||||||
|
|
@ -988,6 +1004,7 @@ static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
|
||||||
struct nmk_gpio_chip *nmk_chip;
|
struct nmk_gpio_chip *nmk_chip;
|
||||||
struct gpio_chip *chip;
|
struct gpio_chip *chip;
|
||||||
unsigned int bit;
|
unsigned int bit;
|
||||||
|
int ret;
|
||||||
|
|
||||||
if (!range) {
|
if (!range) {
|
||||||
dev_err(npct->dev, "invalid range\n");
|
dev_err(npct->dev, "invalid range\n");
|
||||||
|
|
@ -1004,7 +1021,9 @@ static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
|
||||||
|
|
||||||
find_nmk_gpio_from_pin(pin, &bit);
|
find_nmk_gpio_from_pin(pin, &bit);
|
||||||
|
|
||||||
clk_enable(nmk_chip->clk);
|
ret = clk_enable(nmk_chip->clk);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
/* There is no glitch when converting any pin to GPIO */
|
/* There is no glitch when converting any pin to GPIO */
|
||||||
__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
|
__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
|
||||||
clk_disable(nmk_chip->clk);
|
clk_disable(nmk_chip->clk);
|
||||||
|
|
@ -1058,6 +1077,7 @@ static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||||
unsigned long cfg;
|
unsigned long cfg;
|
||||||
int pull, slpm, output, val, i;
|
int pull, slpm, output, val, i;
|
||||||
bool lowemi, gpiomode, sleep;
|
bool lowemi, gpiomode, sleep;
|
||||||
|
int ret;
|
||||||
|
|
||||||
nmk_chip = find_nmk_gpio_from_pin(pin, &bit);
|
nmk_chip = find_nmk_gpio_from_pin(pin, &bit);
|
||||||
if (!nmk_chip) {
|
if (!nmk_chip) {
|
||||||
|
|
@ -1106,17 +1126,19 @@ static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
||||||
slpm_pull ? pullnames[pull] : "same",
|
slpm_pull ? pullnames[pull] : "same",
|
||||||
slpm_output ? (output ? "output" : "input")
|
slpm_output ? (output ? "output" : "input")
|
||||||
: "same",
|
: "same",
|
||||||
slpm_val ? (val ? "high" : "low") : "same");
|
slpm_val ? str_high_low(val) : "same");
|
||||||
}
|
}
|
||||||
|
|
||||||
dev_dbg(nmk_chip->chip.parent,
|
dev_dbg(nmk_chip->chip.parent,
|
||||||
"pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
|
"pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
|
||||||
pin, cfg, pullnames[pull], slpmnames[slpm],
|
pin, cfg, pullnames[pull], slpmnames[slpm],
|
||||||
output ? "output " : "input",
|
output ? "output " : "input",
|
||||||
output ? (val ? "high" : "low") : "",
|
output ? str_high_low(val) : "",
|
||||||
lowemi ? "on" : "off");
|
str_on_off(lowemi));
|
||||||
|
|
||||||
clk_enable(nmk_chip->clk);
|
ret = clk_enable(nmk_chip->clk);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
if (gpiomode)
|
if (gpiomode)
|
||||||
/* No glitch when going to GPIO mode */
|
/* No glitch when going to GPIO mode */
|
||||||
__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
|
__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
|
||||||
|
|
|
||||||
|
|
@ -30,6 +30,7 @@
|
||||||
#include <linux/pinctrl/pinconf.h>
|
#include <linux/pinctrl/pinconf.h>
|
||||||
#include <linux/pinctrl/pinconf-generic.h>
|
#include <linux/pinctrl/pinconf-generic.h>
|
||||||
#include <linux/pinctrl/pinmux.h>
|
#include <linux/pinctrl/pinmux.h>
|
||||||
|
#include <linux/string_choices.h>
|
||||||
#include <linux/suspend.h>
|
#include <linux/suspend.h>
|
||||||
|
|
||||||
#include "core.h"
|
#include "core.h"
|
||||||
|
|
@ -458,7 +459,7 @@ static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
|
||||||
|
|
||||||
if (err)
|
if (err)
|
||||||
dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n",
|
dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n",
|
||||||
on ? "enable" : "disable");
|
str_enable_disable(on));
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
@ -908,12 +909,13 @@ static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int amd_gpio_suspend(struct device *dev)
|
static int amd_gpio_suspend_hibernate_common(struct device *dev, bool is_suspend)
|
||||||
{
|
{
|
||||||
struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
|
struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
|
||||||
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
|
struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
int i;
|
int i;
|
||||||
|
u32 wake_mask = is_suspend ? WAKE_SOURCE_SUSPEND : WAKE_SOURCE_HIBERNATE;
|
||||||
|
|
||||||
for (i = 0; i < desc->npins; i++) {
|
for (i = 0; i < desc->npins; i++) {
|
||||||
int pin = desc->pins[i].number;
|
int pin = desc->pins[i].number;
|
||||||
|
|
@ -925,11 +927,11 @@ static int amd_gpio_suspend(struct device *dev)
|
||||||
gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
|
gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING;
|
||||||
|
|
||||||
/* mask any interrupts not intended to be a wake source */
|
/* mask any interrupts not intended to be a wake source */
|
||||||
if (!(gpio_dev->saved_regs[i] & WAKE_SOURCE)) {
|
if (!(gpio_dev->saved_regs[i] & wake_mask)) {
|
||||||
writel(gpio_dev->saved_regs[i] & ~BIT(INTERRUPT_MASK_OFF),
|
writel(gpio_dev->saved_regs[i] & ~BIT(INTERRUPT_MASK_OFF),
|
||||||
gpio_dev->base + pin * 4);
|
gpio_dev->base + pin * 4);
|
||||||
pm_pr_dbg("Disabling GPIO #%d interrupt for suspend.\n",
|
pm_pr_dbg("Disabling GPIO #%d interrupt for %s.\n",
|
||||||
pin);
|
pin, is_suspend ? "suspend" : "hibernate");
|
||||||
}
|
}
|
||||||
|
|
||||||
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
|
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
|
||||||
|
|
@ -938,6 +940,16 @@ static int amd_gpio_suspend(struct device *dev)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int amd_gpio_suspend(struct device *dev)
|
||||||
|
{
|
||||||
|
return amd_gpio_suspend_hibernate_common(dev, true);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int amd_gpio_hibernate(struct device *dev)
|
||||||
|
{
|
||||||
|
return amd_gpio_suspend_hibernate_common(dev, false);
|
||||||
|
}
|
||||||
|
|
||||||
static int amd_gpio_resume(struct device *dev)
|
static int amd_gpio_resume(struct device *dev)
|
||||||
{
|
{
|
||||||
struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
|
struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
|
||||||
|
|
@ -961,8 +973,12 @@ static int amd_gpio_resume(struct device *dev)
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct dev_pm_ops amd_gpio_pm_ops = {
|
static const struct dev_pm_ops amd_gpio_pm_ops = {
|
||||||
SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
|
.suspend_late = amd_gpio_suspend,
|
||||||
amd_gpio_resume)
|
.resume_early = amd_gpio_resume,
|
||||||
|
.freeze_late = amd_gpio_hibernate,
|
||||||
|
.thaw_early = amd_gpio_resume,
|
||||||
|
.poweroff_late = amd_gpio_hibernate,
|
||||||
|
.restore_early = amd_gpio_resume,
|
||||||
};
|
};
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -80,10 +80,9 @@
|
||||||
#define FUNCTION_MASK GENMASK(1, 0)
|
#define FUNCTION_MASK GENMASK(1, 0)
|
||||||
#define FUNCTION_INVALID GENMASK(7, 0)
|
#define FUNCTION_INVALID GENMASK(7, 0)
|
||||||
|
|
||||||
#define WAKE_SOURCE (BIT(WAKE_CNTRL_OFF_S0I3) | \
|
#define WAKE_SOURCE_SUSPEND (BIT(WAKE_CNTRL_OFF_S0I3) | \
|
||||||
BIT(WAKE_CNTRL_OFF_S3) | \
|
BIT(WAKE_CNTRL_OFF_S3))
|
||||||
BIT(WAKE_CNTRL_OFF_S4) | \
|
#define WAKE_SOURCE_HIBERNATE BIT(WAKE_CNTRL_OFF_S4)
|
||||||
BIT(WAKECNTRL_Z_OFF))
|
|
||||||
|
|
||||||
struct amd_function {
|
struct amd_function {
|
||||||
const char *name;
|
const char *name;
|
||||||
|
|
|
||||||
|
|
@ -14,6 +14,7 @@
|
||||||
#include <linux/regmap.h>
|
#include <linux/regmap.h>
|
||||||
#include <linux/seq_file.h>
|
#include <linux/seq_file.h>
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
|
#include <linux/string_choices.h>
|
||||||
|
|
||||||
#include <linux/pinctrl/machine.h>
|
#include <linux/pinctrl/machine.h>
|
||||||
#include <linux/pinctrl/pinconf-generic.h>
|
#include <linux/pinctrl/pinconf-generic.h>
|
||||||
|
|
@ -2237,7 +2238,7 @@ static int gemini_pmx_set_mux(struct pinctrl_dev *pctldev,
|
||||||
"pin group %s could not be %s: "
|
"pin group %s could not be %s: "
|
||||||
"probably a hardware limitation\n",
|
"probably a hardware limitation\n",
|
||||||
gemini_padgroups[i],
|
gemini_padgroups[i],
|
||||||
enabled ? "enabled" : "disabled");
|
str_enabled_disabled(enabled));
|
||||||
dev_err(pmx->dev,
|
dev_err(pmx->dev,
|
||||||
"GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n",
|
"GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n",
|
||||||
before, after, expected);
|
before, after, expected);
|
||||||
|
|
@ -2245,7 +2246,7 @@ static int gemini_pmx_set_mux(struct pinctrl_dev *pctldev,
|
||||||
dev_dbg(pmx->dev,
|
dev_dbg(pmx->dev,
|
||||||
"padgroup %s %s\n",
|
"padgroup %s %s\n",
|
||||||
gemini_padgroups[i],
|
gemini_padgroups[i],
|
||||||
enabled ? "enabled" : "disabled");
|
str_enabled_disabled(enabled));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -2259,7 +2260,7 @@ static int gemini_pmx_set_mux(struct pinctrl_dev *pctldev,
|
||||||
"pin group %s could not be %s: "
|
"pin group %s could not be %s: "
|
||||||
"probably a hardware limitation\n",
|
"probably a hardware limitation\n",
|
||||||
gemini_padgroups[i],
|
gemini_padgroups[i],
|
||||||
enabled ? "enabled" : "disabled");
|
str_enabled_disabled(enabled));
|
||||||
dev_err(pmx->dev,
|
dev_err(pmx->dev,
|
||||||
"GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n",
|
"GLOBAL MISC CTRL before: %08x, after %08x, expected %08x\n",
|
||||||
before, after, expected);
|
before, after, expected);
|
||||||
|
|
@ -2267,7 +2268,7 @@ static int gemini_pmx_set_mux(struct pinctrl_dev *pctldev,
|
||||||
dev_dbg(pmx->dev,
|
dev_dbg(pmx->dev,
|
||||||
"padgroup %s %s\n",
|
"padgroup %s %s\n",
|
||||||
gemini_padgroups[i],
|
gemini_padgroups[i],
|
||||||
enabled ? "enabled" : "disabled");
|
str_enabled_disabled(enabled));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -2588,7 +2589,7 @@ static int gemini_pmx_probe(struct platform_device *pdev)
|
||||||
tmp = val;
|
tmp = val;
|
||||||
for_each_set_bit(i, &tmp, PADS_MAXBIT) {
|
for_each_set_bit(i, &tmp, PADS_MAXBIT) {
|
||||||
dev_dbg(dev, "pad group %s %s\n", gemini_padgroups[i],
|
dev_dbg(dev, "pad group %s %s\n", gemini_padgroups[i],
|
||||||
(val & BIT(i)) ? "enabled" : "disabled");
|
str_enabled_disabled(val & BIT(i)));
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Check if flash pin is set */
|
/* Check if flash pin is set */
|
||||||
|
|
|
||||||
|
|
@ -3699,7 +3699,7 @@ static void ingenic_gpio_irq_print_chip(struct irq_data *data, struct seq_file *
|
||||||
{
|
{
|
||||||
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
|
struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
|
||||||
|
|
||||||
seq_printf(p, "%s", gpio_chip->label);
|
seq_puts(p, gpio_chip->label);
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct irq_chip ingenic_gpio_irqchip = {
|
static const struct irq_chip ingenic_gpio_irqchip = {
|
||||||
|
|
|
||||||
|
|
@ -1777,7 +1777,7 @@ static const struct pinctrl_ops ocelot_pctl_ops = {
|
||||||
.dt_free_map = pinconf_generic_dt_free_map,
|
.dt_free_map = pinconf_generic_dt_free_map,
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct ocelot_match_data luton_desc = {
|
static const struct ocelot_match_data luton_desc = {
|
||||||
.desc = {
|
.desc = {
|
||||||
.name = "luton-pinctrl",
|
.name = "luton-pinctrl",
|
||||||
.pins = luton_pins,
|
.pins = luton_pins,
|
||||||
|
|
@ -1788,7 +1788,7 @@ static struct ocelot_match_data luton_desc = {
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct ocelot_match_data serval_desc = {
|
static const struct ocelot_match_data serval_desc = {
|
||||||
.desc = {
|
.desc = {
|
||||||
.name = "serval-pinctrl",
|
.name = "serval-pinctrl",
|
||||||
.pins = serval_pins,
|
.pins = serval_pins,
|
||||||
|
|
@ -1799,7 +1799,7 @@ static struct ocelot_match_data serval_desc = {
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct ocelot_match_data ocelot_desc = {
|
static const struct ocelot_match_data ocelot_desc = {
|
||||||
.desc = {
|
.desc = {
|
||||||
.name = "ocelot-pinctrl",
|
.name = "ocelot-pinctrl",
|
||||||
.pins = ocelot_pins,
|
.pins = ocelot_pins,
|
||||||
|
|
@ -1810,7 +1810,7 @@ static struct ocelot_match_data ocelot_desc = {
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct ocelot_match_data jaguar2_desc = {
|
static const struct ocelot_match_data jaguar2_desc = {
|
||||||
.desc = {
|
.desc = {
|
||||||
.name = "jaguar2-pinctrl",
|
.name = "jaguar2-pinctrl",
|
||||||
.pins = jaguar2_pins,
|
.pins = jaguar2_pins,
|
||||||
|
|
@ -1821,7 +1821,7 @@ static struct ocelot_match_data jaguar2_desc = {
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct ocelot_match_data servalt_desc = {
|
static const struct ocelot_match_data servalt_desc = {
|
||||||
.desc = {
|
.desc = {
|
||||||
.name = "servalt-pinctrl",
|
.name = "servalt-pinctrl",
|
||||||
.pins = servalt_pins,
|
.pins = servalt_pins,
|
||||||
|
|
@ -1832,7 +1832,7 @@ static struct ocelot_match_data servalt_desc = {
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct ocelot_match_data sparx5_desc = {
|
static const struct ocelot_match_data sparx5_desc = {
|
||||||
.desc = {
|
.desc = {
|
||||||
.name = "sparx5-pinctrl",
|
.name = "sparx5-pinctrl",
|
||||||
.pins = sparx5_pins,
|
.pins = sparx5_pins,
|
||||||
|
|
@ -1850,7 +1850,7 @@ static struct ocelot_match_data sparx5_desc = {
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct ocelot_match_data lan966x_desc = {
|
static const struct ocelot_match_data lan966x_desc = {
|
||||||
.desc = {
|
.desc = {
|
||||||
.name = "lan966x-pinctrl",
|
.name = "lan966x-pinctrl",
|
||||||
.pins = lan966x_pins,
|
.pins = lan966x_pins,
|
||||||
|
|
@ -1867,7 +1867,7 @@ static struct ocelot_match_data lan966x_desc = {
|
||||||
},
|
},
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct ocelot_match_data lan969x_desc = {
|
static const struct ocelot_match_data lan969x_desc = {
|
||||||
.desc = {
|
.desc = {
|
||||||
.name = "lan969x-pinctrl",
|
.name = "lan969x-pinctrl",
|
||||||
.pins = lan969x_pins,
|
.pins = lan969x_pins,
|
||||||
|
|
@ -2116,7 +2116,7 @@ static void ocelot_irq_ack(struct irq_data *data)
|
||||||
|
|
||||||
static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
|
static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
|
||||||
|
|
||||||
static struct irq_chip ocelot_level_irqchip = {
|
static const struct irq_chip ocelot_level_irqchip = {
|
||||||
.name = "gpio",
|
.name = "gpio",
|
||||||
.irq_mask = ocelot_irq_mask,
|
.irq_mask = ocelot_irq_mask,
|
||||||
.irq_ack = ocelot_irq_ack,
|
.irq_ack = ocelot_irq_ack,
|
||||||
|
|
@ -2126,7 +2126,7 @@ static struct irq_chip ocelot_level_irqchip = {
|
||||||
GPIOCHIP_IRQ_RESOURCE_HELPERS
|
GPIOCHIP_IRQ_RESOURCE_HELPERS
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct irq_chip ocelot_irqchip = {
|
static const struct irq_chip ocelot_irqchip = {
|
||||||
.name = "gpio",
|
.name = "gpio",
|
||||||
.irq_mask = ocelot_irq_mask,
|
.irq_mask = ocelot_irq_mask,
|
||||||
.irq_ack = ocelot_irq_ack,
|
.irq_ack = ocelot_irq_ack,
|
||||||
|
|
|
||||||
|
|
@ -1,7 +1,7 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0-only
|
// SPDX-License-Identifier: GPL-2.0-only
|
||||||
/*
|
/*
|
||||||
* Pinctrl driver for Rockchip SoCs
|
* Pinctrl driver for Rockchip SoCs
|
||||||
*
|
* Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd.
|
||||||
* Copyright (c) 2013 MundoReader S.L.
|
* Copyright (c) 2013 MundoReader S.L.
|
||||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||||
*
|
*
|
||||||
|
|
@ -2003,6 +2003,151 @@ static int rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#define RK3562_DRV_BITS_PER_PIN 8
|
||||||
|
#define RK3562_DRV_PINS_PER_REG 2
|
||||||
|
#define RK3562_DRV_GPIO0_OFFSET 0x20070
|
||||||
|
#define RK3562_DRV_GPIO1_OFFSET 0x200
|
||||||
|
#define RK3562_DRV_GPIO2_OFFSET 0x240
|
||||||
|
#define RK3562_DRV_GPIO3_OFFSET 0x10280
|
||||||
|
#define RK3562_DRV_GPIO4_OFFSET 0x102C0
|
||||||
|
|
||||||
|
static int rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
|
||||||
|
int pin_num, struct regmap **regmap,
|
||||||
|
int *reg, u8 *bit)
|
||||||
|
{
|
||||||
|
struct rockchip_pinctrl *info = bank->drvdata;
|
||||||
|
|
||||||
|
*regmap = info->regmap_base;
|
||||||
|
switch (bank->bank_num) {
|
||||||
|
case 0:
|
||||||
|
*reg = RK3562_DRV_GPIO0_OFFSET;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 1:
|
||||||
|
*reg = RK3562_DRV_GPIO1_OFFSET;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 2:
|
||||||
|
*reg = RK3562_DRV_GPIO2_OFFSET;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 3:
|
||||||
|
*reg = RK3562_DRV_GPIO3_OFFSET;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 4:
|
||||||
|
*reg = RK3562_DRV_GPIO4_OFFSET;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
*reg += ((pin_num / RK3562_DRV_PINS_PER_REG) * 4);
|
||||||
|
*bit = pin_num % RK3562_DRV_PINS_PER_REG;
|
||||||
|
*bit *= RK3562_DRV_BITS_PER_PIN;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define RK3562_PULL_BITS_PER_PIN 2
|
||||||
|
#define RK3562_PULL_PINS_PER_REG 8
|
||||||
|
#define RK3562_PULL_GPIO0_OFFSET 0x20020
|
||||||
|
#define RK3562_PULL_GPIO1_OFFSET 0x80
|
||||||
|
#define RK3562_PULL_GPIO2_OFFSET 0x90
|
||||||
|
#define RK3562_PULL_GPIO3_OFFSET 0x100A0
|
||||||
|
#define RK3562_PULL_GPIO4_OFFSET 0x100B0
|
||||||
|
|
||||||
|
static int rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
|
||||||
|
int pin_num, struct regmap **regmap,
|
||||||
|
int *reg, u8 *bit)
|
||||||
|
{
|
||||||
|
struct rockchip_pinctrl *info = bank->drvdata;
|
||||||
|
|
||||||
|
*regmap = info->regmap_base;
|
||||||
|
switch (bank->bank_num) {
|
||||||
|
case 0:
|
||||||
|
*reg = RK3562_PULL_GPIO0_OFFSET;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 1:
|
||||||
|
*reg = RK3562_PULL_GPIO1_OFFSET;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 2:
|
||||||
|
*reg = RK3562_PULL_GPIO2_OFFSET;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 3:
|
||||||
|
*reg = RK3562_PULL_GPIO3_OFFSET;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 4:
|
||||||
|
*reg = RK3562_PULL_GPIO4_OFFSET;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
*reg += ((pin_num / RK3562_PULL_PINS_PER_REG) * 4);
|
||||||
|
*bit = pin_num % RK3562_PULL_PINS_PER_REG;
|
||||||
|
*bit *= RK3562_PULL_BITS_PER_PIN;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#define RK3562_SMT_BITS_PER_PIN 2
|
||||||
|
#define RK3562_SMT_PINS_PER_REG 8
|
||||||
|
#define RK3562_SMT_GPIO0_OFFSET 0x20030
|
||||||
|
#define RK3562_SMT_GPIO1_OFFSET 0xC0
|
||||||
|
#define RK3562_SMT_GPIO2_OFFSET 0xD0
|
||||||
|
#define RK3562_SMT_GPIO3_OFFSET 0x100E0
|
||||||
|
#define RK3562_SMT_GPIO4_OFFSET 0x100F0
|
||||||
|
|
||||||
|
static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
|
||||||
|
int pin_num,
|
||||||
|
struct regmap **regmap,
|
||||||
|
int *reg, u8 *bit)
|
||||||
|
{
|
||||||
|
struct rockchip_pinctrl *info = bank->drvdata;
|
||||||
|
|
||||||
|
*regmap = info->regmap_base;
|
||||||
|
switch (bank->bank_num) {
|
||||||
|
case 0:
|
||||||
|
*reg = RK3562_SMT_GPIO0_OFFSET;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 1:
|
||||||
|
*reg = RK3562_SMT_GPIO1_OFFSET;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 2:
|
||||||
|
*reg = RK3562_SMT_GPIO2_OFFSET;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 3:
|
||||||
|
*reg = RK3562_SMT_GPIO3_OFFSET;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 4:
|
||||||
|
*reg = RK3562_SMT_GPIO4_OFFSET;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
*reg += ((pin_num / RK3562_SMT_PINS_PER_REG) * 4);
|
||||||
|
*bit = pin_num % RK3562_SMT_PINS_PER_REG;
|
||||||
|
*bit *= RK3562_SMT_BITS_PER_PIN;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
#define RK3568_PULL_PMU_OFFSET 0x20
|
#define RK3568_PULL_PMU_OFFSET 0x20
|
||||||
#define RK3568_PULL_GRF_OFFSET 0x80
|
#define RK3568_PULL_GRF_OFFSET 0x80
|
||||||
#define RK3568_PULL_BITS_PER_PIN 2
|
#define RK3568_PULL_BITS_PER_PIN 2
|
||||||
|
|
@ -2495,7 +2640,8 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
|
||||||
rmask_bits = RK3588_DRV_BITS_PER_PIN;
|
rmask_bits = RK3588_DRV_BITS_PER_PIN;
|
||||||
ret = strength;
|
ret = strength;
|
||||||
goto config;
|
goto config;
|
||||||
} else if (ctrl->type == RK3568) {
|
} else if (ctrl->type == RK3562 ||
|
||||||
|
ctrl->type == RK3568) {
|
||||||
rmask_bits = RK3568_DRV_BITS_PER_PIN;
|
rmask_bits = RK3568_DRV_BITS_PER_PIN;
|
||||||
ret = (1 << (strength + 1)) - 1;
|
ret = (1 << (strength + 1)) - 1;
|
||||||
goto config;
|
goto config;
|
||||||
|
|
@ -2639,6 +2785,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
|
||||||
case RK3328:
|
case RK3328:
|
||||||
case RK3368:
|
case RK3368:
|
||||||
case RK3399:
|
case RK3399:
|
||||||
|
case RK3562:
|
||||||
case RK3568:
|
case RK3568:
|
||||||
case RK3576:
|
case RK3576:
|
||||||
case RK3588:
|
case RK3588:
|
||||||
|
|
@ -2699,6 +2846,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
|
||||||
case RK3328:
|
case RK3328:
|
||||||
case RK3368:
|
case RK3368:
|
||||||
case RK3399:
|
case RK3399:
|
||||||
|
case RK3562:
|
||||||
case RK3568:
|
case RK3568:
|
||||||
case RK3576:
|
case RK3576:
|
||||||
case RK3588:
|
case RK3588:
|
||||||
|
|
@ -2810,6 +2958,7 @@ static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
|
||||||
|
|
||||||
data >>= bit;
|
data >>= bit;
|
||||||
switch (ctrl->type) {
|
switch (ctrl->type) {
|
||||||
|
case RK3562:
|
||||||
case RK3568:
|
case RK3568:
|
||||||
return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
|
return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
|
||||||
default:
|
default:
|
||||||
|
|
@ -2839,6 +2988,7 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
|
||||||
|
|
||||||
/* enable the write to the equivalent lower bits */
|
/* enable the write to the equivalent lower bits */
|
||||||
switch (ctrl->type) {
|
switch (ctrl->type) {
|
||||||
|
case RK3562:
|
||||||
case RK3568:
|
case RK3568:
|
||||||
data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
|
data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
|
||||||
rmask = data | (data >> 16);
|
rmask = data | (data >> 16);
|
||||||
|
|
@ -2965,6 +3115,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
|
||||||
case RK3328:
|
case RK3328:
|
||||||
case RK3368:
|
case RK3368:
|
||||||
case RK3399:
|
case RK3399:
|
||||||
|
case RK3562:
|
||||||
case RK3568:
|
case RK3568:
|
||||||
case RK3576:
|
case RK3576:
|
||||||
case RK3588:
|
case RK3588:
|
||||||
|
|
@ -4086,6 +4237,49 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
|
||||||
.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
|
.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static struct rockchip_pin_bank rk3562_pin_banks[] = {
|
||||||
|
PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
0x20000, 0x20008, 0x20010, 0x20018),
|
||||||
|
PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
0, 0x08, 0x10, 0x18),
|
||||||
|
PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
0x20, 0, 0, 0),
|
||||||
|
PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
0x10040, 0x10048, 0x10050, 0x10058),
|
||||||
|
PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4",
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
IOMUX_WIDTH_4BIT,
|
||||||
|
0,
|
||||||
|
0,
|
||||||
|
0x10060, 0x10068, 0, 0),
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct rockchip_pin_ctrl rk3562_pin_ctrl __maybe_unused = {
|
||||||
|
.pin_banks = rk3562_pin_banks,
|
||||||
|
.nr_banks = ARRAY_SIZE(rk3562_pin_banks),
|
||||||
|
.label = "RK3562-GPIO",
|
||||||
|
.type = RK3562,
|
||||||
|
.pull_calc_reg = rk3562_calc_pull_reg_and_bit,
|
||||||
|
.drv_calc_reg = rk3562_calc_drv_reg_and_bit,
|
||||||
|
.schmitt_calc_reg = rk3562_calc_schmitt_reg_and_bit,
|
||||||
|
};
|
||||||
|
|
||||||
static struct rockchip_pin_bank rk3568_pin_banks[] = {
|
static struct rockchip_pin_bank rk3568_pin_banks[] = {
|
||||||
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
|
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
|
||||||
IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
|
IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
|
||||||
|
|
@ -4210,6 +4404,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
|
||||||
.data = &rk3368_pin_ctrl },
|
.data = &rk3368_pin_ctrl },
|
||||||
{ .compatible = "rockchip,rk3399-pinctrl",
|
{ .compatible = "rockchip,rk3399-pinctrl",
|
||||||
.data = &rk3399_pin_ctrl },
|
.data = &rk3399_pin_ctrl },
|
||||||
|
{ .compatible = "rockchip,rk3562-pinctrl",
|
||||||
|
.data = &rk3562_pin_ctrl },
|
||||||
{ .compatible = "rockchip,rk3568-pinctrl",
|
{ .compatible = "rockchip,rk3568-pinctrl",
|
||||||
.data = &rk3568_pin_ctrl },
|
.data = &rk3568_pin_ctrl },
|
||||||
{ .compatible = "rockchip,rk3576-pinctrl",
|
{ .compatible = "rockchip,rk3576-pinctrl",
|
||||||
|
|
|
||||||
|
|
@ -1,6 +1,6 @@
|
||||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
/*
|
/*
|
||||||
* Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd.
|
* Copyright (c) 2020-2024 Rockchip Electronics Co., Ltd.
|
||||||
*
|
*
|
||||||
* Copyright (c) 2013 MundoReader S.L.
|
* Copyright (c) 2013 MundoReader S.L.
|
||||||
* Author: Heiko Stuebner <heiko@sntech.de>
|
* Author: Heiko Stuebner <heiko@sntech.de>
|
||||||
|
|
@ -196,6 +196,7 @@ enum rockchip_pinctrl_type {
|
||||||
RK3328,
|
RK3328,
|
||||||
RK3368,
|
RK3368,
|
||||||
RK3399,
|
RK3399,
|
||||||
|
RK3562,
|
||||||
RK3568,
|
RK3568,
|
||||||
RK3576,
|
RK3576,
|
||||||
RK3588,
|
RK3588,
|
||||||
|
|
|
||||||
|
|
@ -380,7 +380,7 @@ static void stmfx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
|
||||||
seq_printf(s, "input %s ", str_high_low(val));
|
seq_printf(s, "input %s ", str_high_low(val));
|
||||||
if (type)
|
if (type)
|
||||||
seq_printf(s, "with internal pull-%s ",
|
seq_printf(s, "with internal pull-%s ",
|
||||||
pupd ? "up" : "down");
|
str_up_down(pupd));
|
||||||
else
|
else
|
||||||
seq_printf(s, "%s ", pupd ? "floating" : "analog");
|
seq_printf(s, "%s ", pupd ? "floating" : "analog");
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -137,6 +137,12 @@ config PINCTRL_MSM8916
|
||||||
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
|
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
|
||||||
Qualcomm TLMM block found on the Qualcomm 8916 platform.
|
Qualcomm TLMM block found on the Qualcomm 8916 platform.
|
||||||
|
|
||||||
|
config PINCTRL_MSM8917
|
||||||
|
tristate "Qualcomm 8917 pin controller driver"
|
||||||
|
help
|
||||||
|
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
|
||||||
|
Qualcomm TLMM block found on the Qualcomm MSM8917 platform.
|
||||||
|
|
||||||
config PINCTRL_MSM8953
|
config PINCTRL_MSM8953
|
||||||
tristate "Qualcomm 8953 pin controller driver"
|
tristate "Qualcomm 8953 pin controller driver"
|
||||||
depends on ARM64 || COMPILE_TEST
|
depends on ARM64 || COMPILE_TEST
|
||||||
|
|
|
||||||
|
|
@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o
|
||||||
obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
|
obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
|
||||||
obj-$(CONFIG_PINCTRL_MSM8909) += pinctrl-msm8909.o
|
obj-$(CONFIG_PINCTRL_MSM8909) += pinctrl-msm8909.o
|
||||||
obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o
|
obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o
|
||||||
|
obj-$(CONFIG_PINCTRL_MSM8917) += pinctrl-msm8917.o
|
||||||
obj-$(CONFIG_PINCTRL_MSM8953) += pinctrl-msm8953.o
|
obj-$(CONFIG_PINCTRL_MSM8953) += pinctrl-msm8953.o
|
||||||
obj-$(CONFIG_PINCTRL_MSM8976) += pinctrl-msm8976.o
|
obj-$(CONFIG_PINCTRL_MSM8976) += pinctrl-msm8976.o
|
||||||
obj-$(CONFIG_PINCTRL_MSM8994) += pinctrl-msm8994.o
|
obj-$(CONFIG_PINCTRL_MSM8994) += pinctrl-msm8994.o
|
||||||
|
|
|
||||||
|
|
@ -233,7 +233,10 @@ enum ipq5424_functions {
|
||||||
msm_mux_sdc_clk,
|
msm_mux_sdc_clk,
|
||||||
msm_mux_sdc_cmd,
|
msm_mux_sdc_cmd,
|
||||||
msm_mux_sdc_data,
|
msm_mux_sdc_data,
|
||||||
msm_mux_spi0,
|
msm_mux_spi0_clk,
|
||||||
|
msm_mux_spi0_cs,
|
||||||
|
msm_mux_spi0_miso,
|
||||||
|
msm_mux_spi0_mosi,
|
||||||
msm_mux_spi1,
|
msm_mux_spi1,
|
||||||
msm_mux_spi10,
|
msm_mux_spi10,
|
||||||
msm_mux_spi11,
|
msm_mux_spi11,
|
||||||
|
|
@ -297,8 +300,8 @@ static const char * const qspi_clk_groups[] = {
|
||||||
"gpio5",
|
"gpio5",
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char * const spi0_groups[] = {
|
static const char * const spi0_clk_groups[] = {
|
||||||
"gpio6", "gpio7", "gpio8", "gpio9",
|
"gpio6",
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char * const pwm1_groups[] = {
|
static const char * const pwm1_groups[] = {
|
||||||
|
|
@ -315,14 +318,26 @@ static const char * const qdss_tracedata_a_groups[] = {
|
||||||
"gpio38", "gpio39",
|
"gpio38", "gpio39",
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const char * const spi0_cs_groups[] = {
|
||||||
|
"gpio7",
|
||||||
|
};
|
||||||
|
|
||||||
static const char * const cri_trng1_groups[] = {
|
static const char * const cri_trng1_groups[] = {
|
||||||
"gpio7",
|
"gpio7",
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const char * const spi0_miso_groups[] = {
|
||||||
|
"gpio8",
|
||||||
|
};
|
||||||
|
|
||||||
static const char * const cri_trng2_groups[] = {
|
static const char * const cri_trng2_groups[] = {
|
||||||
"gpio8",
|
"gpio8",
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const char * const spi0_mosi_groups[] = {
|
||||||
|
"gpio9",
|
||||||
|
};
|
||||||
|
|
||||||
static const char * const cri_trng3_groups[] = {
|
static const char * const cri_trng3_groups[] = {
|
||||||
"gpio9",
|
"gpio9",
|
||||||
};
|
};
|
||||||
|
|
@ -680,7 +695,10 @@ static const struct pinfunction ipq5424_functions[] = {
|
||||||
MSM_PIN_FUNCTION(sdc_clk),
|
MSM_PIN_FUNCTION(sdc_clk),
|
||||||
MSM_PIN_FUNCTION(sdc_cmd),
|
MSM_PIN_FUNCTION(sdc_cmd),
|
||||||
MSM_PIN_FUNCTION(sdc_data),
|
MSM_PIN_FUNCTION(sdc_data),
|
||||||
MSM_PIN_FUNCTION(spi0),
|
MSM_PIN_FUNCTION(spi0_clk),
|
||||||
|
MSM_PIN_FUNCTION(spi0_cs),
|
||||||
|
MSM_PIN_FUNCTION(spi0_miso),
|
||||||
|
MSM_PIN_FUNCTION(spi0_mosi),
|
||||||
MSM_PIN_FUNCTION(spi1),
|
MSM_PIN_FUNCTION(spi1),
|
||||||
MSM_PIN_FUNCTION(spi10),
|
MSM_PIN_FUNCTION(spi10),
|
||||||
MSM_PIN_FUNCTION(spi11),
|
MSM_PIN_FUNCTION(spi11),
|
||||||
|
|
@ -700,10 +718,10 @@ static const struct msm_pingroup ipq5424_groups[] = {
|
||||||
PINGROUP(3, sdc_data, qspi_data, pwm2, _, _, _, _, _, _),
|
PINGROUP(3, sdc_data, qspi_data, pwm2, _, _, _, _, _, _),
|
||||||
PINGROUP(4, sdc_cmd, qspi_cs, _, _, _, _, _, _, _),
|
PINGROUP(4, sdc_cmd, qspi_cs, _, _, _, _, _, _, _),
|
||||||
PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _),
|
PINGROUP(5, sdc_clk, qspi_clk, _, _, _, _, _, _, _),
|
||||||
PINGROUP(6, spi0, pwm1, _, cri_trng0, qdss_tracedata_a, _, _, _, _),
|
PINGROUP(6, spi0_clk, pwm1, _, cri_trng0, qdss_tracedata_a, _, _, _, _),
|
||||||
PINGROUP(7, spi0, pwm1, _, cri_trng1, qdss_tracedata_a, _, _, _, _),
|
PINGROUP(7, spi0_cs, pwm1, _, cri_trng1, qdss_tracedata_a, _, _, _, _),
|
||||||
PINGROUP(8, spi0, pwm1, wci_txd, wci_rxd, _, cri_trng2, qdss_tracedata_a, _, _),
|
PINGROUP(8, spi0_miso, pwm1, wci_txd, wci_rxd, _, cri_trng2, qdss_tracedata_a, _, _),
|
||||||
PINGROUP(9, spi0, pwm1, _, cri_trng3, qdss_tracedata_a, _, _, _, _),
|
PINGROUP(9, spi0_mosi, pwm1, _, cri_trng3, qdss_tracedata_a, _, _, _, _),
|
||||||
PINGROUP(10, uart0, pwm0, spi11, _, wci_txd, wci_rxd, _, qdss_tracedata_a, _),
|
PINGROUP(10, uart0, pwm0, spi11, _, wci_txd, wci_rxd, _, qdss_tracedata_a, _),
|
||||||
PINGROUP(11, uart0, pwm0, spi1, _, wci_txd, wci_rxd, _, qdss_tracedata_a, _),
|
PINGROUP(11, uart0, pwm0, spi1, _, wci_txd, wci_rxd, _, qdss_tracedata_a, _),
|
||||||
PINGROUP(12, uart0, pwm0, spi11, _, prng_rosc0, qdss_tracedata_a, _, _, _),
|
PINGROUP(12, uart0, pwm0, spi11, _, prng_rosc0, qdss_tracedata_a, _, _, _),
|
||||||
|
|
|
||||||
|
|
@ -19,6 +19,7 @@
|
||||||
#include <linux/seq_file.h>
|
#include <linux/seq_file.h>
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
#include <linux/spinlock.h>
|
#include <linux/spinlock.h>
|
||||||
|
#include <linux/string_choices.h>
|
||||||
|
|
||||||
#include <linux/pinctrl/machine.h>
|
#include <linux/pinctrl/machine.h>
|
||||||
#include <linux/pinctrl/pinconf-generic.h>
|
#include <linux/pinctrl/pinconf-generic.h>
|
||||||
|
|
@ -714,7 +715,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
|
||||||
}
|
}
|
||||||
|
|
||||||
seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in");
|
seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in");
|
||||||
seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
|
seq_printf(s, " %-4s func%d", str_high_low(val), func);
|
||||||
seq_printf(s, " %dmA", msm_regval_to_drive(drive));
|
seq_printf(s, " %dmA", msm_regval_to_drive(drive));
|
||||||
if (pctrl->soc->pull_no_keeper)
|
if (pctrl->soc->pull_no_keeper)
|
||||||
seq_printf(s, " %s", pulls_no_keeper[pull]);
|
seq_printf(s, " %s", pulls_no_keeper[pull]);
|
||||||
|
|
|
||||||
1620
drivers/pinctrl/qcom/pinctrl-msm8917.c
Normal file
1620
drivers/pinctrl/qcom/pinctrl-msm8917.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -14,6 +14,7 @@
|
||||||
#include <linux/seq_file.h>
|
#include <linux/seq_file.h>
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
#include <linux/spmi.h>
|
#include <linux/spmi.h>
|
||||||
|
#include <linux/string_choices.h>
|
||||||
#include <linux/types.h>
|
#include <linux/types.h>
|
||||||
|
|
||||||
#include <linux/pinctrl/pinconf-generic.h>
|
#include <linux/pinctrl/pinconf-generic.h>
|
||||||
|
|
@ -702,7 +703,7 @@ static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
|
||||||
else
|
else
|
||||||
seq_printf(s, " %-4s",
|
seq_printf(s, " %-4s",
|
||||||
pad->output_enabled ? "out" : "in");
|
pad->output_enabled ? "out" : "in");
|
||||||
seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
|
seq_printf(s, " %-4s", str_high_low(pad->out_value));
|
||||||
seq_printf(s, " %-7s", pmic_gpio_functions[function]);
|
seq_printf(s, " %-7s", pmic_gpio_functions[function]);
|
||||||
seq_printf(s, " vin-%d", pad->power_source);
|
seq_printf(s, " vin-%d", pad->power_source);
|
||||||
seq_printf(s, " %-27s", biases[pad->pullup]);
|
seq_printf(s, " %-27s", biases[pad->pullup]);
|
||||||
|
|
|
||||||
|
|
@ -11,6 +11,7 @@
|
||||||
#include <linux/regmap.h>
|
#include <linux/regmap.h>
|
||||||
#include <linux/seq_file.h>
|
#include <linux/seq_file.h>
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
|
#include <linux/string_choices.h>
|
||||||
#include <linux/types.h>
|
#include <linux/types.h>
|
||||||
|
|
||||||
#include <linux/pinctrl/pinconf-generic.h>
|
#include <linux/pinctrl/pinconf-generic.h>
|
||||||
|
|
@ -544,7 +545,7 @@ static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev,
|
||||||
seq_printf(s, " %d", pad->aout_level);
|
seq_printf(s, " %d", pad->aout_level);
|
||||||
if (pad->has_pullup)
|
if (pad->has_pullup)
|
||||||
seq_printf(s, " %-8s", biases[pad->pullup]);
|
seq_printf(s, " %-8s", biases[pad->pullup]);
|
||||||
seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
|
seq_printf(s, " %-4s", str_high_low(pad->out_value));
|
||||||
if (pad->dtest)
|
if (pad->dtest)
|
||||||
seq_printf(s, " dtest%d", pad->dtest);
|
seq_printf(s, " dtest%d", pad->dtest);
|
||||||
if (pad->paired)
|
if (pad->paired)
|
||||||
|
|
|
||||||
|
|
@ -13,6 +13,7 @@
|
||||||
#include <linux/regmap.h>
|
#include <linux/regmap.h>
|
||||||
#include <linux/seq_file.h>
|
#include <linux/seq_file.h>
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
|
#include <linux/string_choices.h>
|
||||||
|
|
||||||
#include <linux/pinctrl/pinconf-generic.h>
|
#include <linux/pinctrl/pinconf-generic.h>
|
||||||
#include <linux/pinctrl/pinconf.h>
|
#include <linux/pinctrl/pinconf.h>
|
||||||
|
|
@ -569,7 +570,7 @@ static void pm8xxx_gpio_dbg_show_one(struct seq_file *s,
|
||||||
seq_printf(s, " VIN%d", pin->power_source);
|
seq_printf(s, " VIN%d", pin->power_source);
|
||||||
seq_printf(s, " %-27s", biases[pin->bias]);
|
seq_printf(s, " %-27s", biases[pin->bias]);
|
||||||
seq_printf(s, " %-10s", buffer_types[pin->open_drain]);
|
seq_printf(s, " %-10s", buffer_types[pin->open_drain]);
|
||||||
seq_printf(s, " %-4s", pin->output_value ? "high" : "low");
|
seq_printf(s, " %-4s", str_high_low(pin->output_value));
|
||||||
seq_printf(s, " %-7s", strengths[pin->output_strength]);
|
seq_printf(s, " %-7s", strengths[pin->output_strength]);
|
||||||
if (pin->inverted)
|
if (pin->inverted)
|
||||||
seq_puts(s, " inverted");
|
seq_puts(s, " inverted");
|
||||||
|
|
|
||||||
|
|
@ -13,6 +13,7 @@
|
||||||
#include <linux/regmap.h>
|
#include <linux/regmap.h>
|
||||||
#include <linux/seq_file.h>
|
#include <linux/seq_file.h>
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
|
#include <linux/string_choices.h>
|
||||||
|
|
||||||
#include <linux/pinctrl/pinconf-generic.h>
|
#include <linux/pinctrl/pinconf-generic.h>
|
||||||
#include <linux/pinctrl/pinconf.h>
|
#include <linux/pinctrl/pinconf.h>
|
||||||
|
|
@ -576,8 +577,7 @@ static void pm8xxx_mpp_dbg_show_one(struct seq_file *s,
|
||||||
seq_puts(s, "out ");
|
seq_puts(s, "out ");
|
||||||
|
|
||||||
if (!pin->paired) {
|
if (!pin->paired) {
|
||||||
seq_puts(s, pin->output_value ?
|
seq_puts(s, str_high_low(pin->output_value));
|
||||||
"high" : "low");
|
|
||||||
} else {
|
} else {
|
||||||
seq_puts(s, pin->output_value ?
|
seq_puts(s, pin->output_value ?
|
||||||
"inverted" : "follow");
|
"inverted" : "follow");
|
||||||
|
|
@ -589,8 +589,7 @@ static void pm8xxx_mpp_dbg_show_one(struct seq_file *s,
|
||||||
if (pin->output) {
|
if (pin->output) {
|
||||||
seq_printf(s, "out %s ", aout_lvls[pin->aout_level]);
|
seq_printf(s, "out %s ", aout_lvls[pin->aout_level]);
|
||||||
if (!pin->paired) {
|
if (!pin->paired) {
|
||||||
seq_puts(s, pin->output_value ?
|
seq_puts(s, str_high_low(pin->output_value));
|
||||||
"high" : "low");
|
|
||||||
} else {
|
} else {
|
||||||
seq_puts(s, pin->output_value ?
|
seq_puts(s, pin->output_value ?
|
||||||
"inverted" : "follow");
|
"inverted" : "follow");
|
||||||
|
|
@ -605,8 +604,7 @@ static void pm8xxx_mpp_dbg_show_one(struct seq_file *s,
|
||||||
seq_printf(s, "dtest%d", pin->dtest);
|
seq_printf(s, "dtest%d", pin->dtest);
|
||||||
} else {
|
} else {
|
||||||
if (!pin->paired) {
|
if (!pin->paired) {
|
||||||
seq_puts(s, pin->output_value ?
|
seq_puts(s, str_high_low(pin->output_value));
|
||||||
"high" : "low");
|
|
||||||
} else {
|
} else {
|
||||||
seq_puts(s, pin->output_value ?
|
seq_puts(s, pin->output_value ?
|
||||||
"inverted" : "follow");
|
"inverted" : "follow");
|
||||||
|
|
|
||||||
|
|
@ -41,6 +41,7 @@ config PINCTRL_RENESAS
|
||||||
select PINCTRL_PFC_R8A779H0 if ARCH_R8A779H0
|
select PINCTRL_PFC_R8A779H0 if ARCH_R8A779H0
|
||||||
select PINCTRL_RZG2L if ARCH_RZG2L
|
select PINCTRL_RZG2L if ARCH_RZG2L
|
||||||
select PINCTRL_RZV2M if ARCH_R9A09G011
|
select PINCTRL_RZV2M if ARCH_R9A09G011
|
||||||
|
select PINCTRL_RZG2L if ARCH_R9A09G047
|
||||||
select PINCTRL_RZG2L if ARCH_R9A09G057
|
select PINCTRL_RZG2L if ARCH_R9A09G057
|
||||||
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
|
select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203
|
||||||
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
|
select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264
|
||||||
|
|
|
||||||
|
|
@ -26,6 +26,8 @@
|
||||||
#include <linux/pinctrl/pinctrl.h>
|
#include <linux/pinctrl/pinctrl.h>
|
||||||
#include <linux/pinctrl/pinmux.h>
|
#include <linux/pinctrl/pinmux.h>
|
||||||
|
|
||||||
|
#include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>
|
||||||
|
#include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>
|
||||||
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||||
|
|
||||||
#include "../core.h"
|
#include "../core.h"
|
||||||
|
|
@ -157,7 +159,7 @@
|
||||||
#define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */
|
#define PWPR_REGWE_B BIT(5) /* OEN Register Write Enable, known only in RZ/V2H(P) */
|
||||||
|
|
||||||
#define PM_MASK 0x03
|
#define PM_MASK 0x03
|
||||||
#define PFC_MASK 0x07
|
#define PFC_MASK 0x0f
|
||||||
#define IEN_MASK 0x01
|
#define IEN_MASK 0x01
|
||||||
#define IOLH_MASK 0x03
|
#define IOLH_MASK 0x03
|
||||||
#define SR_MASK 0x01
|
#define SR_MASK 0x01
|
||||||
|
|
@ -381,13 +383,51 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static const u64 r9a09g047_variable_pin_cfg[] = {
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 2, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 3, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 4, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 3, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 4, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 6, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 7, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 0, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PH, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 1, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS),
|
||||||
|
};
|
||||||
|
|
||||||
static const u64 r9a09g057_variable_pin_cfg[] = {
|
static const u64 r9a09g057_variable_pin_cfg[] = {
|
||||||
RZG2L_VARIABLE_PIN_CFG_PACK(11, 0, RZV2H_MPXED_PIN_FUNCS),
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 0, RZV2H_MPXED_PIN_FUNCS),
|
||||||
RZG2L_VARIABLE_PIN_CFG_PACK(11, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
RZG2L_VARIABLE_PIN_CFG_PACK(11, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
RZG2L_VARIABLE_PIN_CFG_PACK(11, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 3, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
RZG2L_VARIABLE_PIN_CFG_PACK(11, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
RZG2L_VARIABLE_PIN_CFG_PACK(11, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
RZG2L_VARIABLE_PIN_CFG_PACK(RZV2H_PB, 5, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),
|
||||||
};
|
};
|
||||||
|
|
||||||
#ifdef CONFIG_RISCV
|
#ifdef CONFIG_RISCV
|
||||||
|
|
@ -1962,6 +2002,73 @@ static const u64 r9a08g045_gpio_configs[] = {
|
||||||
RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
|
RZG2L_GPIO_PORT_PACK(6, 0x2a, RZG3S_MPXED_PIN_FUNCS(A)), /* P18 */
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const char * const rzg3e_gpio_names[] = {
|
||||||
|
"P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
|
||||||
|
"P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
|
||||||
|
"P20", "P21", "P22", "P23", "P24", "P25", "P26", "P27",
|
||||||
|
"P30", "P31", "P32", "P33", "P34", "P35", "P36", "P37",
|
||||||
|
"P40", "P41", "P42", "P43", "P44", "P45", "P46", "P47",
|
||||||
|
"P50", "P51", "P52", "P53", "P54", "P55", "P56", "P57",
|
||||||
|
"P60", "P61", "P62", "P63", "P64", "P65", "P66", "P67",
|
||||||
|
"P70", "P71", "P72", "P73", "P74", "P75", "P76", "P77",
|
||||||
|
"P80", "P81", "P82", "P83", "P84", "P85", "P86", "P87",
|
||||||
|
"", "", "", "", "", "", "", "",
|
||||||
|
"PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7",
|
||||||
|
"PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7",
|
||||||
|
"PC0", "PC1", "PC2", "PC3", "PC4", "PC5", "PC6", "PC7",
|
||||||
|
"PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
|
||||||
|
"PE0", "PE1", "PE2", "PE3", "PE4", "PE5", "PE6", "PE7",
|
||||||
|
"PF0", "PF1", "PF2", "PF3", "PF4", "PF5", "PF6", "PF7",
|
||||||
|
"PG0", "PG1", "PG2", "PG3", "PG4", "PG5", "PG6", "PG7",
|
||||||
|
"PH0", "PH1", "PH2", "PH3", "PH4", "PH5", "PH6", "PH7",
|
||||||
|
"", "", "", "", "", "", "", "",
|
||||||
|
"PJ0", "PJ1", "PJ2", "PJ3", "PJ4", "PJ5", "PJ6", "PJ7",
|
||||||
|
"PK0", "PK1", "PK2", "PK3", "PK4", "PK5", "PK6", "PK7",
|
||||||
|
"PL0", "PL1", "PL2", "PL3", "PL4", "PL5", "PL6", "PL7",
|
||||||
|
"PM0", "PM1", "PM2", "PM3", "PM4", "PM5", "PM6", "PM7",
|
||||||
|
"", "", "", "", "", "", "", "",
|
||||||
|
"", "", "", "", "", "", "", "",
|
||||||
|
"", "", "", "", "", "", "", "",
|
||||||
|
"", "", "", "", "", "", "", "",
|
||||||
|
"", "", "", "", "", "", "", "",
|
||||||
|
"PS0", "PS1", "PS2", "PS3", "PS4", "PS5", "PS6", "PS7",
|
||||||
|
};
|
||||||
|
|
||||||
|
static const u64 r9a09g047_gpio_configs[] = {
|
||||||
|
RZG2L_GPIO_PORT_PACK(8, 0x20, RZV2H_MPXED_PIN_FUNCS), /* P0 */
|
||||||
|
RZG2L_GPIO_PORT_PACK(8, 0x21, RZV2H_MPXED_PIN_FUNCS |
|
||||||
|
PIN_CFG_ELC), /* P1 */
|
||||||
|
RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_COMMON_PIN_FUNCS(RZV2H) |
|
||||||
|
PIN_CFG_NOD), /* P2 */
|
||||||
|
RZG2L_GPIO_PORT_PACK(8, 0x23, RZV2H_MPXED_PIN_FUNCS), /* P3 */
|
||||||
|
RZG2L_GPIO_PORT_PACK(6, 0x24, RZV2H_MPXED_PIN_FUNCS), /* P4 */
|
||||||
|
RZG2L_GPIO_PORT_PACK(7, 0x25, RZV2H_MPXED_PIN_FUNCS), /* P5 */
|
||||||
|
RZG2L_GPIO_PORT_PACK(7, 0x26, RZV2H_MPXED_PIN_FUNCS), /* P6 */
|
||||||
|
RZG2L_GPIO_PORT_PACK(8, 0x27, RZV2H_MPXED_PIN_FUNCS |
|
||||||
|
PIN_CFG_ELC), /* P7 */
|
||||||
|
RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */
|
||||||
|
0x0,
|
||||||
|
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */
|
||||||
|
RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS), /* PB */
|
||||||
|
RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */
|
||||||
|
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */
|
||||||
|
RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS), /* PE */
|
||||||
|
RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */
|
||||||
|
RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */
|
||||||
|
RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */
|
||||||
|
0x0,
|
||||||
|
RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */
|
||||||
|
RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */
|
||||||
|
RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS), /* PL */
|
||||||
|
RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */
|
||||||
|
0x0,
|
||||||
|
0x0,
|
||||||
|
0x0,
|
||||||
|
0x0,
|
||||||
|
0x0,
|
||||||
|
RZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS), /* PS */
|
||||||
|
};
|
||||||
|
|
||||||
static const char * const rzv2h_gpio_names[] = {
|
static const char * const rzv2h_gpio_names[] = {
|
||||||
"P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
|
"P00", "P01", "P02", "P03", "P04", "P05", "P06", "P07",
|
||||||
"P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
|
"P10", "P11", "P12", "P13", "P14", "P15", "P16", "P17",
|
||||||
|
|
@ -2085,6 +2192,8 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {
|
||||||
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
|
{ "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x1, 0, (PIN_CFG_IOLH_A | PIN_CFG_IEN |
|
||||||
PIN_CFG_SOFT_PS)) },
|
PIN_CFG_SOFT_PS)) },
|
||||||
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
|
{ "TDO", RZG2L_SINGLE_PIN_PACK(0x1, 1, (PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS)) },
|
||||||
|
{ "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x2, 0, PIN_CFG_IEN) },
|
||||||
|
{ "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x2, 1, PIN_CFG_IEN) },
|
||||||
{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
|
{ "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0x6, 0, PIN_CFG_IOLH_A | PIN_CFG_SOFT_PS) },
|
||||||
{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
|
{ "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x10, 0, (PIN_CFG_IOLH_B | PIN_CFG_IO_VMC_SD0)) },
|
||||||
{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
|
{ "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x10, 1, (PIN_CFG_IOLH_B | PIN_CFG_IEN |
|
||||||
|
|
@ -2250,6 +2359,43 @@ static struct rzg2l_dedicated_configs rzv2h_dedicated_pins[] = {
|
||||||
{ "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
|
{ "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) },
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = {
|
||||||
|
{ "WDTUDFCA", RZG2L_SINGLE_PIN_PACK(0x5, 0,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) },
|
||||||
|
{ "WDTUDFCM", RZG2L_SINGLE_PIN_PACK(0x5, 1,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD | PIN_CFG_NOD)) },
|
||||||
|
{ "SCIF_RXD", RZG2L_SINGLE_PIN_PACK(0x6, 0,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) },
|
||||||
|
{ "SCIF_TXD", RZG2L_SINGLE_PIN_PACK(0x6, 1,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_PUPD)) },
|
||||||
|
{ "SD0CLK", RZG2L_SINGLE_PIN_PACK(0x9, 0,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||||
|
{ "SD0CMD", RZG2L_SINGLE_PIN_PACK(0x9, 1,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||||
|
{ "SD0RSTN", RZG2L_SINGLE_PIN_PACK(0x9, 2,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||||
|
{ "SD0PWEN", RZG2L_SINGLE_PIN_PACK(0x9, 3,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||||
|
{ "SD0IOVS", RZG2L_SINGLE_PIN_PACK(0x9, 4,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR)) },
|
||||||
|
{ "SD0DAT0", RZG2L_SINGLE_PIN_PACK(0xa, 0,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||||
|
{ "SD0DAT1", RZG2L_SINGLE_PIN_PACK(0xa, 1,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||||
|
{ "SD0DAT2", RZG2L_SINGLE_PIN_PACK(0xa, 2,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||||
|
{ "SD0DAT3", RZG2L_SINGLE_PIN_PACK(0xa, 3,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||||
|
{ "SD0DAT4", RZG2L_SINGLE_PIN_PACK(0xa, 4,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||||
|
{ "SD0DAT5", RZG2L_SINGLE_PIN_PACK(0xa, 5,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||||
|
{ "SD0DAT6", RZG2L_SINGLE_PIN_PACK(0xa, 6,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||||
|
{ "SD0DAT7", RZG2L_SINGLE_PIN_PACK(0xa, 7,
|
||||||
|
(PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },
|
||||||
|
};
|
||||||
|
|
||||||
static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)
|
static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)
|
||||||
{
|
{
|
||||||
const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];
|
const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];
|
||||||
|
|
@ -2760,6 +2906,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
|
||||||
BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
|
BUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >
|
||||||
ARRAY_SIZE(rzg2l_gpio_names));
|
ARRAY_SIZE(rzg2l_gpio_names));
|
||||||
|
|
||||||
|
BUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT >
|
||||||
|
ARRAY_SIZE(rzg3e_gpio_names));
|
||||||
|
|
||||||
BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT >
|
BUILD_BUG_ON(ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT >
|
||||||
ARRAY_SIZE(rzv2h_gpio_names));
|
ARRAY_SIZE(rzv2h_gpio_names));
|
||||||
|
|
||||||
|
|
@ -3158,6 +3307,29 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
|
||||||
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
|
.bias_param_to_hw = &rzg2l_bias_param_to_hw,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static struct rzg2l_pinctrl_data r9a09g047_data = {
|
||||||
|
.port_pins = rzg3e_gpio_names,
|
||||||
|
.port_pin_configs = r9a09g047_gpio_configs,
|
||||||
|
.n_ports = ARRAY_SIZE(r9a09g047_gpio_configs),
|
||||||
|
.dedicated_pins = rzg3e_dedicated_pins,
|
||||||
|
.n_port_pins = ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT,
|
||||||
|
.n_dedicated_pins = ARRAY_SIZE(rzg3e_dedicated_pins),
|
||||||
|
.hwcfg = &rzv2h_hwcfg,
|
||||||
|
.variable_pin_cfg = r9a09g047_variable_pin_cfg,
|
||||||
|
.n_variable_pin_cfg = ARRAY_SIZE(r9a09g047_variable_pin_cfg),
|
||||||
|
.num_custom_params = ARRAY_SIZE(renesas_rzv2h_custom_bindings),
|
||||||
|
.custom_params = renesas_rzv2h_custom_bindings,
|
||||||
|
#ifdef CONFIG_DEBUG_FS
|
||||||
|
.custom_conf_items = renesas_rzv2h_conf_items,
|
||||||
|
#endif
|
||||||
|
.pwpr_pfc_lock_unlock = &rzv2h_pwpr_pfc_lock_unlock,
|
||||||
|
.pmc_writeb = &rzv2h_pmc_writeb,
|
||||||
|
.oen_read = &rzv2h_oen_read,
|
||||||
|
.oen_write = &rzv2h_oen_write,
|
||||||
|
.hw_to_bias_param = &rzv2h_hw_to_bias_param,
|
||||||
|
.bias_param_to_hw = &rzv2h_bias_param_to_hw,
|
||||||
|
};
|
||||||
|
|
||||||
static struct rzg2l_pinctrl_data r9a09g057_data = {
|
static struct rzg2l_pinctrl_data r9a09g057_data = {
|
||||||
.port_pins = rzv2h_gpio_names,
|
.port_pins = rzv2h_gpio_names,
|
||||||
.port_pin_configs = r9a09g057_gpio_configs,
|
.port_pin_configs = r9a09g057_gpio_configs,
|
||||||
|
|
@ -3194,6 +3366,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = {
|
||||||
.compatible = "renesas,r9a08g045-pinctrl",
|
.compatible = "renesas,r9a08g045-pinctrl",
|
||||||
.data = &r9a08g045_data,
|
.data = &r9a08g045_data,
|
||||||
},
|
},
|
||||||
|
{
|
||||||
|
.compatible = "renesas,r9a09g047-pinctrl",
|
||||||
|
.data = &r9a09g047_data,
|
||||||
|
},
|
||||||
{
|
{
|
||||||
.compatible = "renesas,r9a09g057-pinctrl",
|
.compatible = "renesas,r9a09g057-pinctrl",
|
||||||
.data = &r9a09g057_data,
|
.data = &r9a09g057_data,
|
||||||
|
|
|
||||||
|
|
@ -23,6 +23,7 @@
|
||||||
#include <linux/of_irq.h>
|
#include <linux/of_irq.h>
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
#include <linux/spinlock.h>
|
#include <linux/spinlock.h>
|
||||||
|
#include <linux/string_choices.h>
|
||||||
#include <linux/regmap.h>
|
#include <linux/regmap.h>
|
||||||
#include <linux/err.h>
|
#include <linux/err.h>
|
||||||
#include <linux/soc/samsung/exynos-pmu.h>
|
#include <linux/soc/samsung/exynos-pmu.h>
|
||||||
|
|
@ -442,7 +443,7 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
|
||||||
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
|
struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
|
||||||
unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
|
unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
|
||||||
|
|
||||||
pr_info("wake %s for irq %u (%s-%lu)\n", on ? "enabled" : "disabled",
|
pr_info("wake %s for irq %u (%s-%lu)\n", str_enabled_disabled(on),
|
||||||
irqd->irq, bank->name, irqd->hwirq);
|
irqd->irq, bank->name, irqd->hwirq);
|
||||||
|
|
||||||
if (!on)
|
if (!on)
|
||||||
|
|
@ -636,7 +637,7 @@ static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
|
||||||
if (clk_enable(b->drvdata->pclk)) {
|
if (clk_enable(b->drvdata->pclk)) {
|
||||||
dev_err(b->gpio_chip.parent,
|
dev_err(b->gpio_chip.parent,
|
||||||
"unable to enable clock for pending IRQs\n");
|
"unable to enable clock for pending IRQs\n");
|
||||||
return;
|
goto out;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -652,6 +653,7 @@ static void exynos_irq_demux_eint16_31(struct irq_desc *desc)
|
||||||
if (eintd->nr_banks)
|
if (eintd->nr_banks)
|
||||||
clk_disable(eintd->banks[0]->drvdata->pclk);
|
clk_disable(eintd->banks[0]->drvdata->pclk);
|
||||||
|
|
||||||
|
out:
|
||||||
chained_irq_exit(chip, desc);
|
chained_irq_exit(chip, desc);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1172,7 +1172,7 @@ static void samsung_banks_node_get(struct device *dev, struct samsung_pinctrl_dr
|
||||||
else
|
else
|
||||||
dev_warn(dev, "Missing node for bank %s - invalid DTB\n",
|
dev_warn(dev, "Missing node for bank %s - invalid DTB\n",
|
||||||
bank->name);
|
bank->name);
|
||||||
/* child reference dropped in samsung_drop_banks_of_node() */
|
/* child reference dropped in samsung_banks_node_put() */
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -1272,7 +1272,7 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
|
||||||
|
|
||||||
ret = platform_get_irq_optional(pdev, 0);
|
ret = platform_get_irq_optional(pdev, 0);
|
||||||
if (ret < 0 && ret != -ENXIO)
|
if (ret < 0 && ret != -ENXIO)
|
||||||
return ret;
|
goto err_put_banks;
|
||||||
if (ret > 0)
|
if (ret > 0)
|
||||||
drvdata->irq = ret;
|
drvdata->irq = ret;
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -22,6 +22,7 @@
|
||||||
#include <linux/reset.h>
|
#include <linux/reset.h>
|
||||||
#include <linux/seq_file.h>
|
#include <linux/seq_file.h>
|
||||||
#include <linux/slab.h>
|
#include <linux/slab.h>
|
||||||
|
#include <linux/string_choices.h>
|
||||||
|
|
||||||
#include <linux/pinctrl/consumer.h>
|
#include <linux/pinctrl/consumer.h>
|
||||||
#include <linux/pinctrl/machine.h>
|
#include <linux/pinctrl/machine.h>
|
||||||
|
|
@ -86,7 +87,6 @@ struct stm32_pinctrl_group {
|
||||||
|
|
||||||
struct stm32_gpio_bank {
|
struct stm32_gpio_bank {
|
||||||
void __iomem *base;
|
void __iomem *base;
|
||||||
struct clk *clk;
|
|
||||||
struct reset_control *rstc;
|
struct reset_control *rstc;
|
||||||
spinlock_t lock;
|
spinlock_t lock;
|
||||||
struct gpio_chip gpio_chip;
|
struct gpio_chip gpio_chip;
|
||||||
|
|
@ -108,6 +108,7 @@ struct stm32_pinctrl {
|
||||||
unsigned ngroups;
|
unsigned ngroups;
|
||||||
const char **grp_names;
|
const char **grp_names;
|
||||||
struct stm32_gpio_bank *banks;
|
struct stm32_gpio_bank *banks;
|
||||||
|
struct clk_bulk_data *clks;
|
||||||
unsigned nbanks;
|
unsigned nbanks;
|
||||||
const struct stm32_pinctrl_match_data *match_data;
|
const struct stm32_pinctrl_match_data *match_data;
|
||||||
struct irq_domain *domain;
|
struct irq_domain *domain;
|
||||||
|
|
@ -1217,7 +1218,7 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
|
||||||
case 0:
|
case 0:
|
||||||
val = stm32_pconf_get(bank, offset, true);
|
val = stm32_pconf_get(bank, offset, true);
|
||||||
seq_printf(s, "- %s - %s",
|
seq_printf(s, "- %s - %s",
|
||||||
val ? "high" : "low",
|
str_high_low(val),
|
||||||
biasing[bias]);
|
biasing[bias]);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
|
|
@ -1227,7 +1228,7 @@ static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
|
||||||
speed = stm32_pconf_get_speed(bank, offset);
|
speed = stm32_pconf_get_speed(bank, offset);
|
||||||
val = stm32_pconf_get(bank, offset, false);
|
val = stm32_pconf_get(bank, offset, false);
|
||||||
seq_printf(s, "- %s - %s - %s - %s %s",
|
seq_printf(s, "- %s - %s - %s - %s %s",
|
||||||
val ? "high" : "low",
|
str_high_low(val),
|
||||||
drive ? "open drain" : "push pull",
|
drive ? "open drain" : "push pull",
|
||||||
biasing[bias],
|
biasing[bias],
|
||||||
speeds[speed], "speed");
|
speeds[speed], "speed");
|
||||||
|
|
@ -1308,12 +1309,6 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode
|
||||||
if (IS_ERR(bank->base))
|
if (IS_ERR(bank->base))
|
||||||
return PTR_ERR(bank->base);
|
return PTR_ERR(bank->base);
|
||||||
|
|
||||||
err = clk_prepare_enable(bank->clk);
|
|
||||||
if (err) {
|
|
||||||
dev_err(dev, "failed to prepare_enable clk (%d)\n", err);
|
|
||||||
return err;
|
|
||||||
}
|
|
||||||
|
|
||||||
bank->gpio_chip = stm32_gpio_template;
|
bank->gpio_chip = stm32_gpio_template;
|
||||||
|
|
||||||
fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);
|
fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);
|
||||||
|
|
@ -1360,26 +1355,20 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode
|
||||||
bank->fwnode, &stm32_gpio_domain_ops,
|
bank->fwnode, &stm32_gpio_domain_ops,
|
||||||
bank);
|
bank);
|
||||||
|
|
||||||
if (!bank->domain) {
|
if (!bank->domain)
|
||||||
err = -ENODEV;
|
return -ENODEV;
|
||||||
goto err_clk;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
names = devm_kcalloc(dev, npins, sizeof(char *), GFP_KERNEL);
|
names = devm_kcalloc(dev, npins, sizeof(char *), GFP_KERNEL);
|
||||||
if (!names) {
|
if (!names)
|
||||||
err = -ENOMEM;
|
return -ENOMEM;
|
||||||
goto err_clk;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i = 0; i < npins; i++) {
|
for (i = 0; i < npins; i++) {
|
||||||
stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i);
|
stm32_pin = stm32_pctrl_get_desc_pin_from_gpio(pctl, bank, i);
|
||||||
if (stm32_pin && stm32_pin->pin.name) {
|
if (stm32_pin && stm32_pin->pin.name) {
|
||||||
names[i] = devm_kasprintf(dev, GFP_KERNEL, "%s", stm32_pin->pin.name);
|
names[i] = devm_kasprintf(dev, GFP_KERNEL, "%s", stm32_pin->pin.name);
|
||||||
if (!names[i]) {
|
if (!names[i])
|
||||||
err = -ENOMEM;
|
return -ENOMEM;
|
||||||
goto err_clk;
|
|
||||||
}
|
|
||||||
} else {
|
} else {
|
||||||
names[i] = NULL;
|
names[i] = NULL;
|
||||||
}
|
}
|
||||||
|
|
@ -1390,15 +1379,11 @@ static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode
|
||||||
err = gpiochip_add_data(&bank->gpio_chip, bank);
|
err = gpiochip_add_data(&bank->gpio_chip, bank);
|
||||||
if (err) {
|
if (err) {
|
||||||
dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
|
dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
|
||||||
goto err_clk;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
|
dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
err_clk:
|
|
||||||
clk_disable_unprepare(bank->clk);
|
|
||||||
return err;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pdev)
|
static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pdev)
|
||||||
|
|
@ -1621,6 +1606,11 @@ int stm32_pctl_probe(struct platform_device *pdev)
|
||||||
if (!pctl->banks)
|
if (!pctl->banks)
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
|
|
||||||
|
pctl->clks = devm_kcalloc(dev, banks, sizeof(*pctl->clks),
|
||||||
|
GFP_KERNEL);
|
||||||
|
if (!pctl->clks)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
i = 0;
|
i = 0;
|
||||||
for_each_gpiochip_node(dev, child) {
|
for_each_gpiochip_node(dev, child) {
|
||||||
struct stm32_gpio_bank *bank = &pctl->banks[i];
|
struct stm32_gpio_bank *bank = &pctl->banks[i];
|
||||||
|
|
@ -1632,24 +1622,27 @@ int stm32_pctl_probe(struct platform_device *pdev)
|
||||||
return -EPROBE_DEFER;
|
return -EPROBE_DEFER;
|
||||||
}
|
}
|
||||||
|
|
||||||
bank->clk = of_clk_get_by_name(np, NULL);
|
pctl->clks[i].clk = of_clk_get_by_name(np, NULL);
|
||||||
if (IS_ERR(bank->clk)) {
|
if (IS_ERR(pctl->clks[i].clk)) {
|
||||||
fwnode_handle_put(child);
|
fwnode_handle_put(child);
|
||||||
return dev_err_probe(dev, PTR_ERR(bank->clk),
|
return dev_err_probe(dev, PTR_ERR(pctl->clks[i].clk),
|
||||||
"failed to get clk\n");
|
"failed to get clk\n");
|
||||||
}
|
}
|
||||||
|
pctl->clks[i].id = "pctl";
|
||||||
i++;
|
i++;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
ret = clk_bulk_prepare_enable(banks, pctl->clks);
|
||||||
|
if (ret) {
|
||||||
|
dev_err(dev, "failed to prepare_enable clk (%d)\n", ret);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
for_each_gpiochip_node(dev, child) {
|
for_each_gpiochip_node(dev, child) {
|
||||||
ret = stm32_gpiolib_register_bank(pctl, child);
|
ret = stm32_gpiolib_register_bank(pctl, child);
|
||||||
if (ret) {
|
if (ret) {
|
||||||
fwnode_handle_put(child);
|
fwnode_handle_put(child);
|
||||||
|
goto err_register;
|
||||||
for (i = 0; i < pctl->nbanks; i++)
|
|
||||||
clk_disable_unprepare(pctl->banks[i].clk);
|
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
pctl->nbanks++;
|
pctl->nbanks++;
|
||||||
|
|
@ -1658,6 +1651,15 @@ int stm32_pctl_probe(struct platform_device *pdev)
|
||||||
dev_info(dev, "Pinctrl STM32 initialized\n");
|
dev_info(dev, "Pinctrl STM32 initialized\n");
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
err_register:
|
||||||
|
for (i = 0; i < pctl->nbanks; i++) {
|
||||||
|
struct stm32_gpio_bank *bank = &pctl->banks[i];
|
||||||
|
|
||||||
|
gpiochip_remove(&bank->gpio_chip);
|
||||||
|
}
|
||||||
|
|
||||||
|
clk_bulk_disable_unprepare(banks, pctl->clks);
|
||||||
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
|
static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
|
||||||
|
|
@ -1726,10 +1728,8 @@ static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
|
||||||
int __maybe_unused stm32_pinctrl_suspend(struct device *dev)
|
int __maybe_unused stm32_pinctrl_suspend(struct device *dev)
|
||||||
{
|
{
|
||||||
struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
|
struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
|
||||||
int i;
|
|
||||||
|
|
||||||
for (i = 0; i < pctl->nbanks; i++)
|
clk_bulk_disable(pctl->nbanks, pctl->clks);
|
||||||
clk_disable(pctl->banks[i].clk);
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
@ -1738,10 +1738,11 @@ int __maybe_unused stm32_pinctrl_resume(struct device *dev)
|
||||||
{
|
{
|
||||||
struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
|
struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
|
||||||
struct stm32_pinctrl_group *g = pctl->groups;
|
struct stm32_pinctrl_group *g = pctl->groups;
|
||||||
int i;
|
int i, ret;
|
||||||
|
|
||||||
for (i = 0; i < pctl->nbanks; i++)
|
ret = clk_bulk_enable(pctl->nbanks, pctl->clks);
|
||||||
clk_enable(pctl->banks[i].clk);
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
for (i = 0; i < pctl->ngroups; i++, g++)
|
for (i = 0; i < pctl->ngroups; i++, g++)
|
||||||
stm32_pinctrl_restore_gpio_regs(pctl, g->pin);
|
stm32_pinctrl_restore_gpio_regs(pctl, g->pin);
|
||||||
|
|
|
||||||
|
|
@ -256,72 +256,84 @@ static const struct sunxi_desc_pin a100_pins[] = {
|
||||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||||
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
|
||||||
|
SUNXI_FUNCTION(0x3, "lvds0"), /* D3P */
|
||||||
SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */
|
SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */
|
||||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),
|
||||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
|
||||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||||
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
|
||||||
|
SUNXI_FUNCTION(0x3, "lvds0"), /* D3N */
|
||||||
SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */
|
SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */
|
||||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),
|
||||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
|
||||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||||
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
|
||||||
|
SUNXI_FUNCTION(0x3, "lvds1"), /* D0P */
|
||||||
SUNXI_FUNCTION(0x4, "spi1"), /* CS */
|
SUNXI_FUNCTION(0x4, "spi1"), /* CS */
|
||||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),
|
||||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
|
||||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||||
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
|
||||||
|
SUNXI_FUNCTION(0x3, "lvds1"), /* D0N */
|
||||||
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
|
SUNXI_FUNCTION(0x4, "spi1"), /* CLK */
|
||||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),
|
||||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
|
||||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||||
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
|
||||||
|
SUNXI_FUNCTION(0x3, "lvds1"), /* D1P */
|
||||||
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
|
SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */
|
||||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)),
|
||||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
|
||||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||||
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
|
||||||
|
SUNXI_FUNCTION(0x3, "lvds1"), /* D1N */
|
||||||
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
|
SUNXI_FUNCTION(0x4, "spi1"), /* MISO */
|
||||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),
|
||||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
|
||||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||||
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
|
||||||
|
SUNXI_FUNCTION(0x3, "lvds1"), /* D2P */
|
||||||
SUNXI_FUNCTION(0x4, "uart3"), /* TX */
|
SUNXI_FUNCTION(0x4, "uart3"), /* TX */
|
||||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)),
|
||||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
|
||||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||||
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
|
||||||
|
SUNXI_FUNCTION(0x3, "lvds1"), /* D2N */
|
||||||
SUNXI_FUNCTION(0x4, "uart3"), /* RX */
|
SUNXI_FUNCTION(0x4, "uart3"), /* RX */
|
||||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)),
|
||||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
|
||||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||||
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
|
||||||
|
SUNXI_FUNCTION(0x3, "lvds1"), /* CKP */
|
||||||
SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
|
SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
|
||||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)),
|
||||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
|
||||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||||
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
|
SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
|
||||||
|
SUNXI_FUNCTION(0x3, "lvds1"), /* CKN */
|
||||||
SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
|
SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
|
||||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)),
|
||||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
|
||||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||||
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
|
SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
|
||||||
|
SUNXI_FUNCTION(0x3, "lvds1"), /* D3P */
|
||||||
SUNXI_FUNCTION(0x4, "uart4"), /* TX */
|
SUNXI_FUNCTION(0x4, "uart4"), /* TX */
|
||||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)),
|
||||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
|
||||||
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
||||||
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
||||||
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
|
SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
|
||||||
|
SUNXI_FUNCTION(0x3, "lvds1"), /* D3N */
|
||||||
SUNXI_FUNCTION(0x4, "uart4"), /* RX */
|
SUNXI_FUNCTION(0x4, "uart4"), /* RX */
|
||||||
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)),
|
||||||
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
|
||||||
|
|
|
||||||
41
include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
Normal file
41
include/dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h
Normal file
|
|
@ -0,0 +1,41 @@
|
||||||
|
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||||
|
/*
|
||||||
|
* This header provides constants for Renesas RZ/G3E family pinctrl bindings.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2024 Renesas Electronics Corp.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
|
||||||
|
#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
|
||||||
|
|
||||||
|
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||||
|
|
||||||
|
/* RZG3E_Px = Offset address of PFC_P_mn - 0x20 */
|
||||||
|
#define RZG3E_P0 0
|
||||||
|
#define RZG3E_P1 1
|
||||||
|
#define RZG3E_P2 2
|
||||||
|
#define RZG3E_P3 3
|
||||||
|
#define RZG3E_P4 4
|
||||||
|
#define RZG3E_P5 5
|
||||||
|
#define RZG3E_P6 6
|
||||||
|
#define RZG3E_P7 7
|
||||||
|
#define RZG3E_P8 8
|
||||||
|
#define RZG3E_PA 10
|
||||||
|
#define RZG3E_PB 11
|
||||||
|
#define RZG3E_PC 12
|
||||||
|
#define RZG3E_PD 13
|
||||||
|
#define RZG3E_PE 14
|
||||||
|
#define RZG3E_PF 15
|
||||||
|
#define RZG3E_PG 16
|
||||||
|
#define RZG3E_PH 17
|
||||||
|
#define RZG3E_PJ 19
|
||||||
|
#define RZG3E_PK 20
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||||||
|
#define RZG3E_PL 21
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||||||
|
#define RZG3E_PM 22
|
||||||
|
#define RZG3E_PS 28
|
||||||
|
|
||||||
|
#define RZG3E_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3E_P##b, p, f)
|
||||||
|
#define RZG3E_GPIO(port, pin) RZG2L_GPIO(RZG3E_P##port, pin)
|
||||||
|
|
||||||
|
#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__ */
|
||||||
31
include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
Normal file
31
include/dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h
Normal file
|
|
@ -0,0 +1,31 @@
|
||||||
|
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||||
|
/*
|
||||||
|
* This header provides constants for Renesas RZ/V2H family pinctrl bindings.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2024 Renesas Electronics Corp.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__
|
||||||
|
#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__
|
||||||
|
|
||||||
|
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
|
||||||
|
|
||||||
|
/* RZV2H_Px = Offset address of PFC_P_mn - 0x20 */
|
||||||
|
#define RZV2H_P0 0
|
||||||
|
#define RZV2H_P1 1
|
||||||
|
#define RZV2H_P2 2
|
||||||
|
#define RZV2H_P3 3
|
||||||
|
#define RZV2H_P4 4
|
||||||
|
#define RZV2H_P5 5
|
||||||
|
#define RZV2H_P6 6
|
||||||
|
#define RZV2H_P7 7
|
||||||
|
#define RZV2H_P8 8
|
||||||
|
#define RZV2H_P9 9
|
||||||
|
#define RZV2H_PA 10
|
||||||
|
#define RZV2H_PB 11
|
||||||
|
|
||||||
|
#define RZV2H_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZV2H_P##b, p, f)
|
||||||
|
#define RZV2H_GPIO(port, pin) RZG2L_GPIO(RZV2H_P##port, pin)
|
||||||
|
|
||||||
|
#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G057_PINCTRL_H__ */
|
||||||
Loading…
Add table
Reference in a new issue