mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Add RSPI support for RZ/V2H
Merge series from Fabrizio Castro <fabrizio.castro.jz@renesas.com>: This series adds support for the Renesas RZ/V2H RSPI IP.
This commit is contained in:
Mark Brown
commit
b71cb34617
4 changed files with 571 additions and 0 deletions
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@ -0,0 +1,96 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/renesas,rzv2h-rspi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/V2H(P) Renesas Serial Peripheral Interface (RSPI)
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maintainers:
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- Fabrizio Castro <fabrizio.castro.jz@renesas.com>
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allOf:
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- $ref: spi-controller.yaml#
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properties:
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compatible:
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const: renesas,r9a09g057-rspi # RZ/V2H(P)
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: Idle Interrupt
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- description: Error Interrupt
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- description: Communication End Interrupt
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- description: Receive Buffer Full Interrupt
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- description: Transmit Buffer Empty Interrupt
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interrupt-names:
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items:
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- const: idle
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- const: error
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- const: end
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- const: rx
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- const: tx
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clocks:
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maxItems: 3
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clock-names:
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items:
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- const: pclk
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- const: pclk_sfr
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- const: tclk
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resets:
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maxItems: 2
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reset-names:
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items:
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- const: presetn
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- const: tresetn
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- clock-names
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- resets
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- reset-names
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- power-domains
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- '#address-cells'
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- '#size-cells'
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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spi@12800800 {
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compatible = "renesas,r9a09g057-rspi";
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reg = <0x12800800 0x400>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 113 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 504 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 505 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "idle", "error", "end", "rx", "tx";
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clocks = <&cpg CPG_MOD 0x5a>,
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<&cpg CPG_MOD 0x5b>,
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<&cpg CPG_MOD 0x5c>;
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clock-names = "pclk", "pclk_sfr", "tclk";
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resets = <&cpg 0x7f>, <&cpg 0x80>;
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reset-names = "presetn", "tresetn";
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power-domains = <&cpg>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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@ -932,6 +932,14 @@ config SPI_RSPI
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help
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SPI driver for Renesas RSPI and QSPI blocks.
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config SPI_RZV2H_RSPI
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tristate "Renesas RZ/V2H RSPI controller"
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depends on ARCH_RENESAS || COMPILE_TEST
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help
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RSPI driver for the Renesas RZ/V2H Serial Peripheral Interface (RSPI).
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RSPI supports both SPI host and SPI target roles. This option only
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enables the SPI host role.
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config SPI_RZV2M_CSI
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tristate "Renesas RZ/V2M CSI controller"
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depends on ARCH_RENESAS || COMPILE_TEST
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@ -127,6 +127,7 @@ obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o
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obj-$(CONFIG_SPI_REALTEK_SNAND) += spi-realtek-rtl-snand.o
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obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o
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obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
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obj-$(CONFIG_SPI_RZV2H_RSPI) += spi-rzv2h-rspi.o
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obj-$(CONFIG_SPI_RZV2M_CSI) += spi-rzv2m-csi.o
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obj-$(CONFIG_SPI_S3C64XX) += spi-s3c64xx.o
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obj-$(CONFIG_SPI_SC18IS602) += spi-sc18is602.o
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466
drivers/spi/spi-rzv2h-rspi.c
Normal file
466
drivers/spi/spi-rzv2h-rspi.c
Normal file
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@ -0,0 +1,466 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Renesas RZ/V2H Renesas Serial Peripheral Interface (RSPI)
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*
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* Copyright (C) 2025 Renesas Electronics Corporation
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/bits.h>
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/limits.h>
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#include <linux/log2.h>
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#include <linux/math.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/reset.h>
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#include <linux/spi/spi.h>
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#include <linux/wait.h>
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/* Registers */
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#define RSPI_SPDR 0x00
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#define RSPI_SPCR 0x08
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#define RSPI_SSLP 0x10
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#define RSPI_SPBR 0x11
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#define RSPI_SPSCR 0x13
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#define RSPI_SPCMD 0x14
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#define RSPI_SPDCR2 0x44
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#define RSPI_SPSR 0x52
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#define RSPI_SPSRC 0x6a
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#define RSPI_SPFCR 0x6c
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/* Register SPCR */
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#define RSPI_SPCR_MSTR BIT(30)
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#define RSPI_SPCR_SPRIE BIT(17)
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#define RSPI_SPCR_SCKASE BIT(12)
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#define RSPI_SPCR_SPE BIT(0)
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/* Register SPBR */
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#define RSPI_SPBR_SPR_MIN 0
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#define RSPI_SPBR_SPR_MAX 255
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/* Register SPCMD */
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#define RSPI_SPCMD_SSLA GENMASK(25, 24)
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#define RSPI_SPCMD_SPB GENMASK(20, 16)
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#define RSPI_SPCMD_LSBF BIT(12)
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#define RSPI_SPCMD_SSLKP BIT(7)
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#define RSPI_SPCMD_BRDV GENMASK(3, 2)
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#define RSPI_SPCMD_CPOL BIT(1)
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#define RSPI_SPCMD_CPHA BIT(0)
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#define RSPI_SPCMD_BRDV_MIN 0
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#define RSPI_SPCMD_BRDV_MAX 3
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/* Register SPDCR2 */
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#define RSPI_SPDCR2_TTRG GENMASK(11, 8)
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#define RSPI_SPDCR2_RTRG GENMASK(3, 0)
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#define RSPI_FIFO_SIZE 16
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/* Register SPSR */
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#define RSPI_SPSR_SPRF BIT(15)
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/* Register RSPI_SPSRC */
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#define RSPI_SPSRC_CLEAR 0xfd80
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#define RSPI_RESET_NUM 2
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#define RSPI_CLK_NUM 3
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struct rzv2h_rspi_priv {
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struct reset_control_bulk_data resets[RSPI_RESET_NUM];
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struct spi_controller *controller;
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void __iomem *base;
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struct clk *tclk;
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wait_queue_head_t wait;
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unsigned int bytes_per_word;
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u32 freq;
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u16 status;
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};
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#define RZV2H_RSPI_TX(func, type) \
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static inline void rzv2h_rspi_tx_##type(struct rzv2h_rspi_priv *rspi, \
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const void *txbuf, \
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unsigned int index) { \
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type buf = 0; \
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\
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if (txbuf) \
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buf = ((type *)txbuf)[index]; \
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\
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func(buf, rspi->base + RSPI_SPDR); \
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}
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#define RZV2H_RSPI_RX(func, type) \
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static inline void rzv2h_rspi_rx_##type(struct rzv2h_rspi_priv *rspi, \
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void *rxbuf, \
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unsigned int index) { \
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type buf = func(rspi->base + RSPI_SPDR); \
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\
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if (rxbuf) \
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((type *)rxbuf)[index] = buf; \
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}
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RZV2H_RSPI_TX(writel, u32)
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RZV2H_RSPI_TX(writew, u16)
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RZV2H_RSPI_TX(writeb, u8)
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RZV2H_RSPI_RX(readl, u32)
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RZV2H_RSPI_RX(readw, u16)
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RZV2H_RSPI_RX(readl, u8)
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static void rzv2h_rspi_reg_rmw(const struct rzv2h_rspi_priv *rspi,
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int reg_offs, u32 bit_mask, u32 value)
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{
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u32 tmp;
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value <<= __ffs(bit_mask);
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tmp = (readl(rspi->base + reg_offs) & ~bit_mask) | value;
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writel(tmp, rspi->base + reg_offs);
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}
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static inline void rzv2h_rspi_spe_disable(const struct rzv2h_rspi_priv *rspi)
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{
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rzv2h_rspi_reg_rmw(rspi, RSPI_SPCR, RSPI_SPCR_SPE, 0);
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}
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static inline void rzv2h_rspi_spe_enable(const struct rzv2h_rspi_priv *rspi)
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{
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rzv2h_rspi_reg_rmw(rspi, RSPI_SPCR, RSPI_SPCR_SPE, 1);
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}
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static inline void rzv2h_rspi_clear_fifos(const struct rzv2h_rspi_priv *rspi)
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{
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writeb(1, rspi->base + RSPI_SPFCR);
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}
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static inline void rzv2h_rspi_clear_all_irqs(struct rzv2h_rspi_priv *rspi)
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{
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writew(RSPI_SPSRC_CLEAR, rspi->base + RSPI_SPSRC);
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rspi->status = 0;
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}
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static irqreturn_t rzv2h_rx_irq_handler(int irq, void *data)
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{
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struct rzv2h_rspi_priv *rspi = data;
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rspi->status = readw(rspi->base + RSPI_SPSR);
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wake_up(&rspi->wait);
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return IRQ_HANDLED;
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}
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static inline int rzv2h_rspi_wait_for_interrupt(struct rzv2h_rspi_priv *rspi,
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u32 wait_mask)
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{
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return wait_event_timeout(rspi->wait, (rspi->status & wait_mask),
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HZ) == 0 ? -ETIMEDOUT : 0;
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}
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static void rzv2h_rspi_send(struct rzv2h_rspi_priv *rspi, const void *txbuf,
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unsigned int index)
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{
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switch (rspi->bytes_per_word) {
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case 4:
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rzv2h_rspi_tx_u32(rspi, txbuf, index);
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break;
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case 2:
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rzv2h_rspi_tx_u16(rspi, txbuf, index);
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break;
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default:
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rzv2h_rspi_tx_u8(rspi, txbuf, index);
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}
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}
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static int rzv2h_rspi_receive(struct rzv2h_rspi_priv *rspi, void *rxbuf,
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unsigned int index)
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{
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int ret;
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ret = rzv2h_rspi_wait_for_interrupt(rspi, RSPI_SPSR_SPRF);
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if (ret)
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return ret;
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switch (rspi->bytes_per_word) {
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case 4:
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rzv2h_rspi_rx_u32(rspi, rxbuf, index);
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break;
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case 2:
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rzv2h_rspi_rx_u16(rspi, rxbuf, index);
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break;
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default:
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rzv2h_rspi_rx_u8(rspi, rxbuf, index);
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}
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return 0;
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}
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static int rzv2h_rspi_transfer_one(struct spi_controller *controller,
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struct spi_device *spi,
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struct spi_transfer *transfer)
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{
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struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(controller);
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unsigned int words_to_transfer, i;
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int ret = 0;
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transfer->effective_speed_hz = rspi->freq;
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words_to_transfer = transfer->len / rspi->bytes_per_word;
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for (i = 0; i < words_to_transfer; i++) {
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rzv2h_rspi_clear_all_irqs(rspi);
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rzv2h_rspi_send(rspi, transfer->tx_buf, i);
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ret = rzv2h_rspi_receive(rspi, transfer->rx_buf, i);
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if (ret)
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break;
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}
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rzv2h_rspi_clear_all_irqs(rspi);
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if (ret)
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transfer->error = SPI_TRANS_FAIL_IO;
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spi_finalize_current_transfer(controller);
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return ret;
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}
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static inline u32 rzv2h_rspi_calc_bitrate(unsigned long tclk_rate, u8 spr,
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u8 brdv)
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{
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return DIV_ROUND_UP(tclk_rate, (2 * (spr + 1) * (1 << brdv)));
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}
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static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_priv *rspi, u32 hz)
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{
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unsigned long tclk_rate;
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int spr;
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u8 brdv;
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/*
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* From the manual:
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* Bit rate = f(RSPI_n_TCLK)/(2*(n+1)*2^(N))
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*
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* Where:
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* * RSPI_n_TCLK is fixed to 200MHz on V2H
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* * n = SPR - is RSPI_SPBR.SPR (from 0 to 255)
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* * N = BRDV - is RSPI_SPCMD.BRDV (from 0 to 3)
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*/
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tclk_rate = clk_get_rate(rspi->tclk);
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for (brdv = RSPI_SPCMD_BRDV_MIN; brdv <= RSPI_SPCMD_BRDV_MAX; brdv++) {
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spr = DIV_ROUND_UP(tclk_rate, hz * (1 << (brdv + 1)));
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spr--;
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if (spr >= RSPI_SPBR_SPR_MIN && spr <= RSPI_SPBR_SPR_MAX)
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goto clock_found;
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}
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return 0;
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clock_found:
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rzv2h_rspi_reg_rmw(rspi, RSPI_SPCMD, RSPI_SPCMD_BRDV, brdv);
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writeb(spr, rspi->base + RSPI_SPBR);
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return rzv2h_rspi_calc_bitrate(tclk_rate, spr, brdv);
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}
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static int rzv2h_rspi_prepare_message(struct spi_controller *ctlr,
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struct spi_message *message)
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{
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struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr);
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const struct spi_device *spi = message->spi;
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struct spi_transfer *xfer;
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u32 speed_hz = U32_MAX;
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u8 bits_per_word;
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u32 conf32;
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u16 conf16;
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/* Make sure SPCR.SPE is 0 before amending the configuration */
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rzv2h_rspi_spe_disable(rspi);
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/* Configure the device to work in "host" mode */
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conf32 = RSPI_SPCR_MSTR;
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/* Auto-stop function */
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conf32 |= RSPI_SPCR_SCKASE;
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/* SPI receive buffer full interrupt enable */
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conf32 |= RSPI_SPCR_SPRIE;
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writel(conf32, rspi->base + RSPI_SPCR);
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/* Use SPCMD0 only */
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writeb(0x0, rspi->base + RSPI_SPSCR);
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/* Setup mode */
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conf32 = FIELD_PREP(RSPI_SPCMD_CPOL, !!(spi->mode & SPI_CPOL));
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conf32 |= FIELD_PREP(RSPI_SPCMD_CPHA, !!(spi->mode & SPI_CPHA));
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conf32 |= FIELD_PREP(RSPI_SPCMD_LSBF, !!(spi->mode & SPI_LSB_FIRST));
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conf32 |= FIELD_PREP(RSPI_SPCMD_SSLKP, 1);
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conf32 |= FIELD_PREP(RSPI_SPCMD_SSLA, spi_get_chipselect(spi, 0));
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writel(conf32, rspi->base + RSPI_SPCMD);
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if (spi->mode & SPI_CS_HIGH)
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writeb(BIT(spi_get_chipselect(spi, 0)), rspi->base + RSPI_SSLP);
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else
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writeb(0, rspi->base + RSPI_SSLP);
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/* Setup FIFO thresholds */
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conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, RSPI_FIFO_SIZE - 1);
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conf16 |= FIELD_PREP(RSPI_SPDCR2_RTRG, 0);
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writew(conf16, rspi->base + RSPI_SPDCR2);
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rzv2h_rspi_clear_fifos(rspi);
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list_for_each_entry(xfer, &message->transfers, transfer_list) {
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if (!xfer->speed_hz)
|
||||
continue;
|
||||
|
||||
speed_hz = min(xfer->speed_hz, speed_hz);
|
||||
bits_per_word = xfer->bits_per_word;
|
||||
}
|
||||
|
||||
if (speed_hz == U32_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
rspi->bytes_per_word = roundup_pow_of_two(BITS_TO_BYTES(bits_per_word));
|
||||
rzv2h_rspi_reg_rmw(rspi, RSPI_SPCMD, RSPI_SPCMD_SPB, bits_per_word - 1);
|
||||
|
||||
rspi->freq = rzv2h_rspi_setup_clock(rspi, speed_hz);
|
||||
if (!rspi->freq)
|
||||
return -EINVAL;
|
||||
|
||||
rzv2h_rspi_spe_enable(rspi);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzv2h_rspi_unprepare_message(struct spi_controller *ctlr,
|
||||
struct spi_message *message)
|
||||
{
|
||||
struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr);
|
||||
|
||||
rzv2h_rspi_spe_disable(rspi);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzv2h_rspi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_controller *controller;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct rzv2h_rspi_priv *rspi;
|
||||
struct clk_bulk_data *clks;
|
||||
unsigned long tclk_rate;
|
||||
int irq_rx, ret, i;
|
||||
|
||||
controller = devm_spi_alloc_host(dev, sizeof(*rspi));
|
||||
if (!controller)
|
||||
return -ENOMEM;
|
||||
|
||||
rspi = spi_controller_get_devdata(controller);
|
||||
platform_set_drvdata(pdev, rspi);
|
||||
|
||||
rspi->controller = controller;
|
||||
|
||||
rspi->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(rspi->base))
|
||||
return PTR_ERR(rspi->base);
|
||||
|
||||
ret = devm_clk_bulk_get_all_enabled(dev, &clks);
|
||||
if (ret != RSPI_CLK_NUM)
|
||||
return dev_err_probe(dev, ret >= 0 ? -EINVAL : ret,
|
||||
"cannot get clocks\n");
|
||||
for (i = 0; i < RSPI_CLK_NUM; i++) {
|
||||
if (!strcmp(clks[i].id, "tclk")) {
|
||||
rspi->tclk = clks[i].clk;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (!rspi->tclk)
|
||||
return dev_err_probe(dev, -EINVAL, "Failed to get tclk\n");
|
||||
|
||||
tclk_rate = clk_get_rate(rspi->tclk);
|
||||
|
||||
rspi->resets[0].id = "presetn";
|
||||
rspi->resets[1].id = "tresetn";
|
||||
ret = devm_reset_control_bulk_get_exclusive(dev, RSPI_RESET_NUM,
|
||||
rspi->resets);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "cannot get resets\n");
|
||||
|
||||
irq_rx = platform_get_irq_byname(pdev, "rx");
|
||||
if (irq_rx < 0)
|
||||
return dev_err_probe(dev, irq_rx, "cannot get IRQ 'rx'\n");
|
||||
|
||||
ret = reset_control_bulk_deassert(RSPI_RESET_NUM, rspi->resets);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to deassert resets\n");
|
||||
|
||||
init_waitqueue_head(&rspi->wait);
|
||||
|
||||
ret = devm_request_irq(dev, irq_rx, rzv2h_rx_irq_handler, 0,
|
||||
dev_name(dev), rspi);
|
||||
if (ret) {
|
||||
dev_err(dev, "cannot request `rx` IRQ\n");
|
||||
goto quit_resets;
|
||||
}
|
||||
|
||||
controller->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
|
||||
SPI_LSB_FIRST;
|
||||
controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
|
||||
controller->prepare_message = rzv2h_rspi_prepare_message;
|
||||
controller->unprepare_message = rzv2h_rspi_unprepare_message;
|
||||
controller->num_chipselect = 4;
|
||||
controller->transfer_one = rzv2h_rspi_transfer_one;
|
||||
controller->min_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate,
|
||||
RSPI_SPBR_SPR_MAX,
|
||||
RSPI_SPCMD_BRDV_MAX);
|
||||
controller->max_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate,
|
||||
RSPI_SPBR_SPR_MIN,
|
||||
RSPI_SPCMD_BRDV_MIN);
|
||||
|
||||
device_set_node(&controller->dev, dev_fwnode(dev));
|
||||
|
||||
ret = spi_register_controller(controller);
|
||||
if (ret) {
|
||||
dev_err(dev, "register controller failed\n");
|
||||
goto quit_resets;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
quit_resets:
|
||||
reset_control_bulk_assert(RSPI_RESET_NUM, rspi->resets);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void rzv2h_rspi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct rzv2h_rspi_priv *rspi = platform_get_drvdata(pdev);
|
||||
|
||||
spi_unregister_controller(rspi->controller);
|
||||
|
||||
reset_control_bulk_assert(RSPI_RESET_NUM, rspi->resets);
|
||||
}
|
||||
|
||||
static const struct of_device_id rzv2h_rspi_match[] = {
|
||||
{ .compatible = "renesas,r9a09g057-rspi" },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rzv2h_rspi_match);
|
||||
|
||||
static struct platform_driver rzv2h_rspi_drv = {
|
||||
.probe = rzv2h_rspi_probe,
|
||||
.remove = rzv2h_rspi_remove,
|
||||
.driver = {
|
||||
.name = "rzv2h_rspi",
|
||||
.of_match_table = rzv2h_rspi_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(rzv2h_rspi_drv);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");
|
||||
MODULE_DESCRIPTION("Renesas RZ/V2H(P) Serial Peripheral Interface Driver");
|
||||
Loading…
Add table
Reference in a new issue