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arm64: dts: nuvoton: Add initial ma35d1 device tree
Add initial device tree support for Nuvoton ma35d1 SoC, including cpu, clock, reset, and serial controllers. Add reference boards som-256m and iot-512m. Signed-off-by: Jacky Huang <ychuang3@nuvoton.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Jacky Huang
Arnd Bergmann
parent
15b53677e7
commit
b69af09847
4 changed files with 348 additions and 0 deletions
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_MA35) += ma35d1-iot-512m.dtb
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dtb-$(CONFIG_ARCH_MA35) += ma35d1-som-256m.dtb
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dtb-$(CONFIG_ARCH_NPCM) += nuvoton-npcm845-evb.dtb
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56
arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
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56
arch/arm64/boot/dts/nuvoton/ma35d1-iot-512m.dts
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023 Nuvoton Technology Corp.
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* Author: Shan-Chun Hung <schung@nuvoton.com>
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* Jacky huang <ychuang3@nuvoton.com>
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*/
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/dts-v1/;
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#include "ma35d1.dtsi"
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/ {
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model = "Nuvoton MA35D1-IoT";
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compatible = "nuvoton,ma35d1-iot", "nuvoton,ma35d1";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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mem: memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x20000000>; /* 512M DRAM */
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};
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clk_hxt: clock-hxt {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "clk_hxt";
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};
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};
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&uart0 {
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status = "okay";
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};
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&clk {
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assigned-clocks = <&clk CAPLL>,
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<&clk DDRPLL>,
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<&clk APLL>,
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<&clk EPLL>,
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<&clk VPLL>;
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assigned-clock-rates = <800000000>,
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<266000000>,
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<180000000>,
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<500000000>,
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<102000000>;
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nuvoton,pll-mode = "integer",
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"fractional",
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"integer",
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"integer",
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"integer";
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};
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56
arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
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arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023 Nuvoton Technology Corp.
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* Author: Shan-Chun Hung <schung@nuvoton.com>
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* Jacky huang <ychuang3@nuvoton.com>
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*/
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/dts-v1/;
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#include "ma35d1.dtsi"
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/ {
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model = "Nuvoton MA35D1-SOM";
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compatible = "nuvoton,ma35d1-som", "nuvoton,ma35d1";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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mem: memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x10000000>; /* 256M DRAM */
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};
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clk_hxt: clock-hxt {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "clk_hxt";
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};
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};
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&uart0 {
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status = "okay";
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};
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&clk {
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assigned-clocks = <&clk CAPLL>,
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<&clk DDRPLL>,
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<&clk APLL>,
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<&clk EPLL>,
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<&clk VPLL>;
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assigned-clock-rates = <800000000>,
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<266000000>,
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<180000000>,
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<500000000>,
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<102000000>;
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nuvoton,pll-mode = "integer",
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"fractional",
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"integer",
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"integer",
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"integer";
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};
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234
arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
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234
arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023 Nuvoton Technology Corp.
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* Author: Shan-Chun Hung <schung@nuvoton.com>
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* Jacky huang <ychuang3@nuvoton.com>
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
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#include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
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/ {
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compatible = "nuvoton,ma35d1";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a35";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&L2_0>;
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};
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L2_0: l2-cache {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x80000>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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gic: interrupt-controller@50801000 {
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compatible = "arm,gic-400";
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reg = <0x0 0x50801000 0 0x1000>, /* GICD */
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<0x0 0x50802000 0 0x2000>, /* GICC */
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<0x0 0x50804000 0 0x2000>, /* GICH */
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<0x0 0x50806000 0 0x2000>; /* GICV */
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
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interrupt-parent = <&gic>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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sys: system-management@40460000 {
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compatible = "nuvoton,ma35d1-reset";
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reg = <0x0 0x40460000 0x0 0x200>;
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#reset-cells = <1>;
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};
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clk: clock-controller@40460200 {
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compatible = "nuvoton,ma35d1-clk";
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reg = <0x00000000 0x40460200 0x0 0x100>;
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#clock-cells = <1>;
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clocks = <&clk_hxt>;
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};
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uart0: serial@40700000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x40700000 0x0 0x100>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART0_GATE>;
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status = "disabled";
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};
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uart1: serial@40710000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x40710000 0x0 0x100>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART1_GATE>;
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status = "disabled";
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};
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uart2: serial@40720000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x40720000 0x0 0x100>;
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART2_GATE>;
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status = "disabled";
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};
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uart3: serial@40730000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x40730000 0x0 0x100>;
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART3_GATE>;
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status = "disabled";
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};
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uart4: serial@40740000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x40740000 0x0 0x100>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART4_GATE>;
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status = "disabled";
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};
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uart5: serial@40750000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x40750000 0x0 0x100>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART5_GATE>;
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status = "disabled";
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};
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uart6: serial@40760000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x40760000 0x0 0x100>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART6_GATE>;
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status = "disabled";
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};
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uart7: serial@40770000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x40770000 0x0 0x100>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART7_GATE>;
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status = "disabled";
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};
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uart8: serial@40780000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x40780000 0x0 0x100>;
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART8_GATE>;
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status = "disabled";
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};
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uart9: serial@40790000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x40790000 0x0 0x100>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART9_GATE>;
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status = "disabled";
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};
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uart10: serial@407a0000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x407a0000 0x0 0x100>;
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interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART10_GATE>;
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status = "disabled";
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};
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uart11: serial@407b0000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x407b0000 0x0 0x100>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART11_GATE>;
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status = "disabled";
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};
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uart12: serial@407c0000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x407c0000 0x0 0x100>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART12_GATE>;
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status = "disabled";
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};
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uart13: serial@407d0000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x407d0000 0x0 0x100>;
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interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART13_GATE>;
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status = "disabled";
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};
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uart14: serial@407e0000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x407e0000 0x0 0x100>;
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interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART14_GATE>;
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status = "disabled";
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};
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uart15: serial@407f0000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x407f0000 0x0 0x100>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART15_GATE>;
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status = "disabled";
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};
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uart16: serial@40880000 {
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compatible = "nuvoton,ma35d1-uart";
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reg = <0x0 0x40880000 0x0 0x100>;
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interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk UART16_GATE>;
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status = "disabled";
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};
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};
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};
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