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drm/amdgpu: add gpu harvest support for yellow carp (v2)

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Register callback in gfxhub functions to program the bypass groups in
gc_utcl2 corresponding to harvested SA.

v2: update comments (Alex)

Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Xiaomeng Hou 2021-04-06 09:33:16 +08:00 • committed by Alex Deucher
parent 9df5b9bd8b
commit b3accd6f66
3 changed files with 48 additions and 0 deletions
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1
drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
View file

@ -34,6 +34,7 @@ struct amdgpu_gfxhub_funcs {
void (*set_fault_enable_default)(struct amdgpu_device *adev, bool value); void (*set_fault_enable_default)(struct amdgpu_device *adev, bool value);
void (*init)(struct amdgpu_device *adev); void (*init)(struct amdgpu_device *adev);
int (*get_xgmi_info)(struct amdgpu_device *adev); int (*get_xgmi_info)(struct amdgpu_device *adev);
void (*utcl2_harvest)(struct amdgpu_device *adev);
}; };
struct amdgpu_gfxhub { struct amdgpu_gfxhub {

40
drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
View file

@ -31,6 +31,9 @@
#include "soc15_common.h" #include "soc15_common.h"
#define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP 0x16f8
#define mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP_BASE_IDX 0
static const char *gfxhub_client_ids[] = { static const char *gfxhub_client_ids[] = {
"CB/DB", "CB/DB",
"Reserved", "Reserved",
@ -531,6 +534,42 @@ static int gfxhub_v2_1_get_xgmi_info(struct amdgpu_device *adev)
return 0; return 0;
} }
static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)
{
int i;
u32 tmp = 0, disabled_sa = 0;
u32 efuse_setting, vbios_setting;
u32 max_sa_mask = amdgpu_gfx_create_bitmask(
adev->gfx.config.max_sh_per_se *
adev->gfx.config.max_shader_engines);
if (adev->asic_type == CHIP_YELLOW_CARP) {
/* Get SA disabled bitmap from eFuse setting */
efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
/* Get SA disabled bitmap from VBIOS setting */
vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
disabled_sa |= efuse_setting | vbios_setting;
/* Make sure not to report harvested SAs beyond the max SA count */
disabled_sa &= max_sa_mask;
for (i = 0; disabled_sa > 0; i++) {
if (disabled_sa & 1)
tmp |= 0x3 << (i * 2);
disabled_sa >>= 1;
}
disabled_sa = tmp;
WREG32_SOC15(GC, 0, mmGCUTCL2_HARVEST_BYPASS_GROUPS_YELLOW_CARP, disabled_sa);
}
}
const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = { const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
.get_fb_location = gfxhub_v2_1_get_fb_location, .get_fb_location = gfxhub_v2_1_get_fb_location,
.get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset, .get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset,
@ -540,4 +579,5 @@ const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
.set_fault_enable_default = gfxhub_v2_1_set_fault_enable_default, .set_fault_enable_default = gfxhub_v2_1_set_fault_enable_default,
.init = gfxhub_v2_1_init, .init = gfxhub_v2_1_init,
.get_xgmi_info = gfxhub_v2_1_get_xgmi_info, .get_xgmi_info = gfxhub_v2_1_get_xgmi_info,
.utcl2_harvest = gfxhub_v2_1_utcl2_harvest,
}; };

7
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
View file

@ -1059,6 +1059,13 @@ static int gmc_v10_0_hw_init(void *handle)
/* The sequence of these two function calls matters.*/ /* The sequence of these two function calls matters.*/
gmc_v10_0_init_golden_registers(adev); gmc_v10_0_init_golden_registers(adev);
/*
* harvestable groups in gc_utcl2 need to be programmed before any GFX block
* register setup within GMC, or else system hang when harvesting SA.
*/
if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)
adev->gfxhub.funcs->utcl2_harvest(adev);
r = gmc_v10_0_gart_enable(adev); r = gmc_v10_0_gart_enable(adev);
if (r) if (r)
return r; return r;