arm64: dts: rockchip: Adjust the HDMI DDC IO driver strength for rk3588

For the RK3588 HDMI controller, the falling edge of DDC SDA and SCL
almost coincide and cannot be adjusted by HDMI registrer, resulting
in poor compatibility of DDC communication.

An improvement of the compatibility of DDC can be done by increasing
the driver strength of SCL and decreasing the driver strength of SDA
to increase the slope of the falling edge.

It should be noted that the maximum driving strength of hdmim0_tx1_scl
is only 3, which is different from that of the other IOs.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Link: https://lore.kernel.org/r/20250522020537.1884771-1-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Andy Yan 2025-05-22 10:05:24 +08:00 committed by Heiko Stuebner
parent af0f43d5d0
commit af9feb0b85
3 changed files with 48 additions and 12 deletions

View file

@ -578,14 +578,14 @@
hdmim0_tx0_scl: hdmim0-tx0-scl {
rockchip,pins =
/* hdmim0_tx0_scl */
<4 RK_PB7 5 &pcfg_pull_none>;
<4 RK_PB7 5 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim0_tx0_sda: hdmim0-tx0-sda {
rockchip,pins =
/* hdmim0_tx0_sda */
<4 RK_PC0 5 &pcfg_pull_none>;
<4 RK_PC0 5 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
@ -640,14 +640,14 @@
hdmim1_tx0_scl: hdmim1-tx0-scl {
rockchip,pins =
/* hdmim1_tx0_scl */
<0 RK_PD5 11 &pcfg_pull_none>;
<0 RK_PD5 11 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim1_tx0_sda: hdmim1-tx0-sda {
rockchip,pins =
/* hdmim1_tx0_sda */
<0 RK_PD4 11 &pcfg_pull_none>;
<0 RK_PD4 11 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
@ -668,14 +668,14 @@
hdmim1_tx1_scl: hdmim1-tx1-scl {
rockchip,pins =
/* hdmim1_tx1_scl */
<3 RK_PC6 5 &pcfg_pull_none>;
<3 RK_PC6 5 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim1_tx1_sda: hdmim1-tx1-sda {
rockchip,pins =
/* hdmim1_tx1_sda */
<3 RK_PC5 5 &pcfg_pull_none>;
<3 RK_PC5 5 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
hdmim2_rx_cec: hdmim2-rx-cec {
@ -709,14 +709,14 @@
hdmim2_tx0_scl: hdmim2-tx0-scl {
rockchip,pins =
/* hdmim2_tx0_scl */
<3 RK_PC7 5 &pcfg_pull_none>;
<3 RK_PC7 5 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim2_tx0_sda: hdmim2-tx0-sda {
rockchip,pins =
/* hdmim2_tx0_sda */
<3 RK_PD0 5 &pcfg_pull_none>;
<3 RK_PD0 5 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/
@ -730,14 +730,14 @@
hdmim2_tx1_scl: hdmim2-tx1-scl {
rockchip,pins =
/* hdmim2_tx1_scl */
<1 RK_PA4 5 &pcfg_pull_none>;
<1 RK_PA4 5 &pcfg_pull_none_drv_level_5_smt>;
};
/omit-if-no-ref/
hdmim2_tx1_sda: hdmim2-tx1-sda {
rockchip,pins =
/* hdmim2_tx1_sda */
<1 RK_PA3 5 &pcfg_pull_none>;
<1 RK_PA3 5 &pcfg_pull_none_drv_level_1_smt>;
};
/omit-if-no-ref/

View file

@ -160,14 +160,15 @@
hdmim0_tx1_scl: hdmim0-tx1-scl {
rockchip,pins =
/* hdmim0_tx1_scl */
<2 RK_PB5 4 &pcfg_pull_none>;
<2 RK_PB5 4 &pcfg_pull_none_drv_level_3_smt>;
};
/omit-if-no-ref/
hdmim0_tx1_sda: hdmim0-tx1-sda {
rockchip,pins =
/* hdmim0_tx1_sda */
<2 RK_PB4 4 &pcfg_pull_none>;
<2 RK_PB4 4 &pcfg_pull_none_drv_level_1_smt>;
};
};

View file

@ -332,6 +332,41 @@
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_1_smt: pcfg-pull-none-drv-level-1-smt {
bias-disable;
drive-strength = <1>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_2_smt: pcfg-pull-none-drv-level-2-smt {
bias-disable;
drive-strength = <2>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_3_smt: pcfg-pull-none-drv-level-3-smt {
bias-disable;
drive-strength = <3>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_4_smt: pcfg-pull-none-drv-level-4-smt {
bias-disable;
drive-strength = <4>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_pull_none_drv_level_5_smt: pcfg-pull-none-drv-level-5-smt {
bias-disable;
drive-strength = <5>;
input-schmitt-enable;
};
/omit-if-no-ref/
pcfg_output_high: pcfg-output-high {
output-high;