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arm64: dts: rockchip: Adjust the HDMI DDC IO driver strength for rk3588
For the RK3588 HDMI controller, the falling edge of DDC SDA and SCL almost coincide and cannot be adjusted by HDMI registrer, resulting in poor compatibility of DDC communication. An improvement of the compatibility of DDC can be done by increasing the driver strength of SCL and decreasing the driver strength of SDA to increase the slope of the falling edge. It should be noted that the maximum driving strength of hdmim0_tx1_scl is only 3, which is different from that of the other IOs. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250522020537.1884771-1-andyshrk@163.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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3 changed files with 48 additions and 12 deletions
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@ -578,14 +578,14 @@
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hdmim0_tx0_scl: hdmim0-tx0-scl {
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rockchip,pins =
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/* hdmim0_tx0_scl */
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<4 RK_PB7 5 &pcfg_pull_none>;
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<4 RK_PB7 5 &pcfg_pull_none_drv_level_5_smt>;
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};
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/omit-if-no-ref/
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hdmim0_tx0_sda: hdmim0-tx0-sda {
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rockchip,pins =
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/* hdmim0_tx0_sda */
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<4 RK_PC0 5 &pcfg_pull_none>;
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<4 RK_PC0 5 &pcfg_pull_none_drv_level_1_smt>;
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};
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/omit-if-no-ref/
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@ -640,14 +640,14 @@
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hdmim1_tx0_scl: hdmim1-tx0-scl {
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rockchip,pins =
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/* hdmim1_tx0_scl */
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<0 RK_PD5 11 &pcfg_pull_none>;
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<0 RK_PD5 11 &pcfg_pull_none_drv_level_5_smt>;
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};
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/omit-if-no-ref/
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hdmim1_tx0_sda: hdmim1-tx0-sda {
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rockchip,pins =
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/* hdmim1_tx0_sda */
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<0 RK_PD4 11 &pcfg_pull_none>;
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<0 RK_PD4 11 &pcfg_pull_none_drv_level_1_smt>;
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};
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/omit-if-no-ref/
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@ -668,14 +668,14 @@
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hdmim1_tx1_scl: hdmim1-tx1-scl {
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rockchip,pins =
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/* hdmim1_tx1_scl */
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<3 RK_PC6 5 &pcfg_pull_none>;
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<3 RK_PC6 5 &pcfg_pull_none_drv_level_5_smt>;
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};
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/omit-if-no-ref/
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hdmim1_tx1_sda: hdmim1-tx1-sda {
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rockchip,pins =
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/* hdmim1_tx1_sda */
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<3 RK_PC5 5 &pcfg_pull_none>;
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<3 RK_PC5 5 &pcfg_pull_none_drv_level_1_smt>;
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};
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/omit-if-no-ref/
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hdmim2_rx_cec: hdmim2-rx-cec {
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@ -709,14 +709,14 @@
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hdmim2_tx0_scl: hdmim2-tx0-scl {
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rockchip,pins =
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/* hdmim2_tx0_scl */
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<3 RK_PC7 5 &pcfg_pull_none>;
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<3 RK_PC7 5 &pcfg_pull_none_drv_level_5_smt>;
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};
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/omit-if-no-ref/
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hdmim2_tx0_sda: hdmim2-tx0-sda {
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rockchip,pins =
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/* hdmim2_tx0_sda */
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<3 RK_PD0 5 &pcfg_pull_none>;
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<3 RK_PD0 5 &pcfg_pull_none_drv_level_1_smt>;
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};
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/omit-if-no-ref/
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@ -730,14 +730,14 @@
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hdmim2_tx1_scl: hdmim2-tx1-scl {
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rockchip,pins =
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/* hdmim2_tx1_scl */
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<1 RK_PA4 5 &pcfg_pull_none>;
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<1 RK_PA4 5 &pcfg_pull_none_drv_level_5_smt>;
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};
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/omit-if-no-ref/
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hdmim2_tx1_sda: hdmim2-tx1-sda {
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rockchip,pins =
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/* hdmim2_tx1_sda */
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<1 RK_PA3 5 &pcfg_pull_none>;
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<1 RK_PA3 5 &pcfg_pull_none_drv_level_1_smt>;
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};
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/omit-if-no-ref/
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@ -160,14 +160,15 @@
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hdmim0_tx1_scl: hdmim0-tx1-scl {
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rockchip,pins =
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/* hdmim0_tx1_scl */
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<2 RK_PB5 4 &pcfg_pull_none>;
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<2 RK_PB5 4 &pcfg_pull_none_drv_level_3_smt>;
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};
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/omit-if-no-ref/
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hdmim0_tx1_sda: hdmim0-tx1-sda {
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rockchip,pins =
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/* hdmim0_tx1_sda */
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<2 RK_PB4 4 &pcfg_pull_none>;
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<2 RK_PB4 4 &pcfg_pull_none_drv_level_1_smt>;
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};
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};
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@ -332,6 +332,41 @@
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input-schmitt-enable;
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};
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/omit-if-no-ref/
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pcfg_pull_none_drv_level_1_smt: pcfg-pull-none-drv-level-1-smt {
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bias-disable;
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drive-strength = <1>;
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input-schmitt-enable;
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};
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/omit-if-no-ref/
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pcfg_pull_none_drv_level_2_smt: pcfg-pull-none-drv-level-2-smt {
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bias-disable;
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drive-strength = <2>;
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input-schmitt-enable;
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};
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/omit-if-no-ref/
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pcfg_pull_none_drv_level_3_smt: pcfg-pull-none-drv-level-3-smt {
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bias-disable;
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drive-strength = <3>;
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input-schmitt-enable;
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};
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/omit-if-no-ref/
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pcfg_pull_none_drv_level_4_smt: pcfg-pull-none-drv-level-4-smt {
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bias-disable;
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drive-strength = <4>;
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input-schmitt-enable;
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};
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/omit-if-no-ref/
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pcfg_pull_none_drv_level_5_smt: pcfg-pull-none-drv-level-5-smt {
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bias-disable;
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drive-strength = <5>;
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input-schmitt-enable;
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};
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/omit-if-no-ref/
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pcfg_output_high: pcfg-output-high {
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output-high;
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