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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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selftests/bpf: verifier/masking.c converted to inline assembly
Test verifier/masking.c automatically converted to use inline assembly. Signed-off-by: Eduard Zingerman <eddyz87@gmail.com> Link: https://lore.kernel.org/r/20230325025524.144043-30-eddyz87@gmail.com Signed-off-by: Alexei Starovoitov <ast@kernel.org>
This commit is contained in:
Eduard Zingerman
Alexei Starovoitov
parent
05e474ecbb
commit
ade3f08fc2
3 changed files with 412 additions and 322 deletions
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@ -26,6 +26,7 @@
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#include "verifier_leak_ptr.skel.h"
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#include "verifier_map_ptr.skel.h"
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#include "verifier_map_ret_val.skel.h"
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#include "verifier_masking.skel.h"
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__maybe_unused
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static void run_tests_aux(const char *skel_name, skel_elf_bytes_fn elf_bytes_factory)
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@ -74,3 +75,4 @@ void test_verifier_ld_ind(void) { RUN(verifier_ld_ind); }
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void test_verifier_leak_ptr(void) { RUN(verifier_leak_ptr); }
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void test_verifier_map_ptr(void) { RUN(verifier_map_ptr); }
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void test_verifier_map_ret_val(void) { RUN(verifier_map_ret_val); }
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void test_verifier_masking(void) { RUN(verifier_masking); }
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410
tools/testing/selftests/bpf/progs/verifier_masking.c
Normal file
410
tools/testing/selftests/bpf/progs/verifier_masking.c
Normal file
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@ -0,0 +1,410 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Converted from tools/testing/selftests/bpf/verifier/masking.c */
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#include <linux/bpf.h>
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#include <bpf/bpf_helpers.h>
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#include "bpf_misc.h"
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SEC("socket")
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__description("masking, test out of bounds 1")
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__success __success_unpriv __retval(0)
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__naked void test_out_of_bounds_1(void)
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{
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asm volatile (" \
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w1 = 5; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 5 - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test out of bounds 2")
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__success __success_unpriv __retval(0)
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__naked void test_out_of_bounds_2(void)
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{
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asm volatile (" \
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w1 = 1; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 1 - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test out of bounds 3")
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__success __success_unpriv __retval(0)
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__naked void test_out_of_bounds_3(void)
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{
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asm volatile (" \
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w1 = 0xffffffff; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 0xffffffff - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test out of bounds 4")
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__success __success_unpriv __retval(0)
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__naked void test_out_of_bounds_4(void)
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{
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asm volatile (" \
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w1 = 0xffffffff; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 1 - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test out of bounds 5")
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__success __success_unpriv __retval(0)
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__naked void test_out_of_bounds_5(void)
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{
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asm volatile (" \
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w1 = -1; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 1 - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test out of bounds 6")
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__success __success_unpriv __retval(0)
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__naked void test_out_of_bounds_6(void)
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{
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asm volatile (" \
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w1 = -1; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 0xffffffff - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test out of bounds 7")
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__success __success_unpriv __retval(0)
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__naked void test_out_of_bounds_7(void)
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{
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asm volatile (" \
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r1 = 5; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 5 - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test out of bounds 8")
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__success __success_unpriv __retval(0)
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__naked void test_out_of_bounds_8(void)
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{
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asm volatile (" \
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r1 = 1; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 1 - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test out of bounds 9")
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__success __success_unpriv __retval(0)
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__naked void test_out_of_bounds_9(void)
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{
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asm volatile (" \
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r1 = 0xffffffff; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 0xffffffff - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test out of bounds 10")
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__success __success_unpriv __retval(0)
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__naked void test_out_of_bounds_10(void)
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{
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asm volatile (" \
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r1 = 0xffffffff; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 1 - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test out of bounds 11")
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__success __success_unpriv __retval(0)
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__naked void test_out_of_bounds_11(void)
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{
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asm volatile (" \
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r1 = -1; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 1 - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test out of bounds 12")
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__success __success_unpriv __retval(0)
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__naked void test_out_of_bounds_12(void)
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{
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asm volatile (" \
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r1 = -1; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 0xffffffff - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test in bounds 1")
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__success __success_unpriv __retval(4)
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__naked void masking_test_in_bounds_1(void)
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{
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asm volatile (" \
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w1 = 4; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 5 - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test in bounds 2")
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__success __success_unpriv __retval(0)
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__naked void masking_test_in_bounds_2(void)
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{
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asm volatile (" \
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w1 = 0; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 0xffffffff - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test in bounds 3")
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__success __success_unpriv __retval(0xfffffffe)
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__naked void masking_test_in_bounds_3(void)
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{
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asm volatile (" \
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w1 = 0xfffffffe; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 0xffffffff - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test in bounds 4")
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__success __success_unpriv __retval(0xabcde)
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__naked void masking_test_in_bounds_4(void)
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{
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asm volatile (" \
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w1 = 0xabcde; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 0xabcdef - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test in bounds 5")
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__success __success_unpriv __retval(0)
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__naked void masking_test_in_bounds_5(void)
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{
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asm volatile (" \
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w1 = 0; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 1 - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test in bounds 6")
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__success __success_unpriv __retval(46)
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__naked void masking_test_in_bounds_6(void)
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{
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asm volatile (" \
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w1 = 46; \
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w2 = %[__imm_0]; \
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r2 -= r1; \
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r2 |= r1; \
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r2 = -r2; \
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r2 s>>= 63; \
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r1 &= r2; \
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r0 = r1; \
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exit; \
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" :
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: __imm_const(__imm_0, 47 - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test in bounds 7")
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__success __success_unpriv __retval(46)
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__naked void masking_test_in_bounds_7(void)
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{
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asm volatile (" \
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r3 = -46; \
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r3 *= -1; \
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w2 = %[__imm_0]; \
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r2 -= r3; \
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r2 |= r3; \
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r2 = -r2; \
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r2 s>>= 63; \
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r3 &= r2; \
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r0 = r3; \
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exit; \
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" :
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: __imm_const(__imm_0, 47 - 1)
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: __clobber_all);
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}
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SEC("socket")
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__description("masking, test in bounds 8")
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__success __success_unpriv __retval(0)
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__naked void masking_test_in_bounds_8(void)
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{
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asm volatile (" \
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r3 = -47; \
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r3 *= -1; \
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w2 = %[__imm_0]; \
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r2 -= r3; \
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r2 |= r3; \
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r2 = -r2; \
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r2 s>>= 63; \
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r3 &= r2; \
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r0 = r3; \
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exit; \
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" :
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: __imm_const(__imm_0, 47 - 1)
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: __clobber_all);
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}
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char _license[] SEC("license") = "GPL";
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|
|
@ -1,322 +0,0 @@
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{
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"masking, test out of bounds 1",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_1, 5),
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BPF_MOV32_IMM(BPF_REG_2, 5 - 1),
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BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
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BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
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BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
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BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
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BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
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BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = 0,
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},
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{
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"masking, test out of bounds 2",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_1, 1),
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BPF_MOV32_IMM(BPF_REG_2, 1 - 1),
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BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
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BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
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BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
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BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
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BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
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BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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||||
.retval = 0,
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},
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||||
{
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||||
"masking, test out of bounds 3",
|
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.insns = {
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BPF_MOV32_IMM(BPF_REG_1, 0xffffffff),
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BPF_MOV32_IMM(BPF_REG_2, 0xffffffff - 1),
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BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
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BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
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BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
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BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 0,
|
||||
},
|
||||
{
|
||||
"masking, test out of bounds 4",
|
||||
.insns = {
|
||||
BPF_MOV32_IMM(BPF_REG_1, 0xffffffff),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 1 - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 0,
|
||||
},
|
||||
{
|
||||
"masking, test out of bounds 5",
|
||||
.insns = {
|
||||
BPF_MOV32_IMM(BPF_REG_1, -1),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 1 - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 0,
|
||||
},
|
||||
{
|
||||
"masking, test out of bounds 6",
|
||||
.insns = {
|
||||
BPF_MOV32_IMM(BPF_REG_1, -1),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 0xffffffff - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 0,
|
||||
},
|
||||
{
|
||||
"masking, test out of bounds 7",
|
||||
.insns = {
|
||||
BPF_MOV64_IMM(BPF_REG_1, 5),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 5 - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 0,
|
||||
},
|
||||
{
|
||||
"masking, test out of bounds 8",
|
||||
.insns = {
|
||||
BPF_MOV64_IMM(BPF_REG_1, 1),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 1 - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 0,
|
||||
},
|
||||
{
|
||||
"masking, test out of bounds 9",
|
||||
.insns = {
|
||||
BPF_MOV64_IMM(BPF_REG_1, 0xffffffff),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 0xffffffff - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 0,
|
||||
},
|
||||
{
|
||||
"masking, test out of bounds 10",
|
||||
.insns = {
|
||||
BPF_MOV64_IMM(BPF_REG_1, 0xffffffff),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 1 - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 0,
|
||||
},
|
||||
{
|
||||
"masking, test out of bounds 11",
|
||||
.insns = {
|
||||
BPF_MOV64_IMM(BPF_REG_1, -1),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 1 - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 0,
|
||||
},
|
||||
{
|
||||
"masking, test out of bounds 12",
|
||||
.insns = {
|
||||
BPF_MOV64_IMM(BPF_REG_1, -1),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 0xffffffff - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 0,
|
||||
},
|
||||
{
|
||||
"masking, test in bounds 1",
|
||||
.insns = {
|
||||
BPF_MOV32_IMM(BPF_REG_1, 4),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 5 - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 4,
|
||||
},
|
||||
{
|
||||
"masking, test in bounds 2",
|
||||
.insns = {
|
||||
BPF_MOV32_IMM(BPF_REG_1, 0),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 0xffffffff - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 0,
|
||||
},
|
||||
{
|
||||
"masking, test in bounds 3",
|
||||
.insns = {
|
||||
BPF_MOV32_IMM(BPF_REG_1, 0xfffffffe),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 0xffffffff - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 0xfffffffe,
|
||||
},
|
||||
{
|
||||
"masking, test in bounds 4",
|
||||
.insns = {
|
||||
BPF_MOV32_IMM(BPF_REG_1, 0xabcde),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 0xabcdef - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 0xabcde,
|
||||
},
|
||||
{
|
||||
"masking, test in bounds 5",
|
||||
.insns = {
|
||||
BPF_MOV32_IMM(BPF_REG_1, 0),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 1 - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 0,
|
||||
},
|
||||
{
|
||||
"masking, test in bounds 6",
|
||||
.insns = {
|
||||
BPF_MOV32_IMM(BPF_REG_1, 46),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 47 - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_1),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_1, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 46,
|
||||
},
|
||||
{
|
||||
"masking, test in bounds 7",
|
||||
.insns = {
|
||||
BPF_MOV64_IMM(BPF_REG_3, -46),
|
||||
BPF_ALU64_IMM(BPF_MUL, BPF_REG_3, -1),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 47 - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_3),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_3),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_3, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_3),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 46,
|
||||
},
|
||||
{
|
||||
"masking, test in bounds 8",
|
||||
.insns = {
|
||||
BPF_MOV64_IMM(BPF_REG_3, -47),
|
||||
BPF_ALU64_IMM(BPF_MUL, BPF_REG_3, -1),
|
||||
BPF_MOV32_IMM(BPF_REG_2, 47 - 1),
|
||||
BPF_ALU64_REG(BPF_SUB, BPF_REG_2, BPF_REG_3),
|
||||
BPF_ALU64_REG(BPF_OR, BPF_REG_2, BPF_REG_3),
|
||||
BPF_ALU64_IMM(BPF_NEG, BPF_REG_2, 0),
|
||||
BPF_ALU64_IMM(BPF_ARSH, BPF_REG_2, 63),
|
||||
BPF_ALU64_REG(BPF_AND, BPF_REG_3, BPF_REG_2),
|
||||
BPF_MOV64_REG(BPF_REG_0, BPF_REG_3),
|
||||
BPF_EXIT_INSN(),
|
||||
},
|
||||
.result = ACCEPT,
|
||||
.retval = 0,
|
||||
},
|
||||
Loading…
Add table
Reference in a new issue