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macb: bindings doc: update sifive fu540-c000 binding
As per the discussion with Nicolas Ferre[0], rename the compatible property to a more appropriate and specific string. [0] https://lore.kernel.org/netdev/CAJ2_jOFEVZQat0Yprg4hem4jRrqkB72FKSeQj4p8P5KA-+rgww@mail.gmail.com/ Signed-off-by: Yash Shah <yash.shah@sifive.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Reviewed-by: Paul Walmsley <paul.walmsley@sifive.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -15,10 +15,10 @@ Required properties:
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Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs.
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Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs.
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Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
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Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
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Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
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Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
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Use "sifive,fu540-macb" for SiFive FU540-C000 SoC.
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Use "sifive,fu540-c000-gem" for SiFive FU540-C000 SoC.
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Or the generic form: "cdns,emac".
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Or the generic form: "cdns,emac".
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- reg: Address and length of the register set for the device
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- reg: Address and length of the register set for the device
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For "sifive,fu540-macb", second range is required to specify the
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For "sifive,fu540-c000-gem", second range is required to specify the
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address and length of the registers for GEMGXL Management block.
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address and length of the registers for GEMGXL Management block.
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- interrupts: Should contain macb interrupt
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- interrupts: Should contain macb interrupt
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- phy-mode: See ethernet.txt file in the same directory.
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- phy-mode: See ethernet.txt file in the same directory.
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