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arm64: dts: apple: s800-0-3: Add CPU caches

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Add information about CPU caches in both variants of Apple A9 SoC.

Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Link: https://lore.kernel.org/r/20250220-caches-v1-4-2c7011097768@gmail.com
Signed-off-by: Sven Peter <sven@svenpeter.dev>
This commit is contained in:
Nick Chan 2025-02-20 20:21:45 +08:00 • committed by Sven Peter
parent 93669da1d1
commit a7a38536f2
1 changed files with 13 additions and 0 deletions
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13
arch/arm64/boot/dts/apple/s800-0-3.dtsi
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@ -36,6 +36,9 @@
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
cpu1: cpu@1 {
@ -46,6 +49,16 @@
performance-domains = <&cpufreq>;
enable-method = "spin-table";
device_type = "cpu";
next-level-cache = <&l2_cache>;
i-cache-size = <0x10000>;
d-cache-size = <0x10000>;
};
l2_cache: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
cache-size = <0x300000>;
};
};