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ARM: 64-bit DT updates for v4.8

Browse source 
The 64-bit DT changes are surprisingly small this time, we only add two
 SoC platforms: the ZTE ZX296718 Set-top-box SoC and the SocioNext
 UniPhier LD11 TV SoC, each with their reference boards.
 
 There are three new machines added for existing SoC platforms:
 
 - The Marvell Armada 8040 development board is an impressive quad-core
   Cortex-A72 machine with three 10gbit ethernet interfaces
 
 - Qualcomms DragonBoard 820c single-board computer is their current
   high-end phone platform in the 96boards form factor
 
 - Rockchip: Tronsmart Orion r86 set-top-box is a popular mid-range
   Android box based on the 8-core rk3368 SoC.
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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM 64-bit DT updates from Arnd Bergmann:
 "The 64-bit DT changes are surprisingly small this time, we only add
  two SoC platforms: the ZTE ZX296718 Set-top-box SoC and the SocioNext
  UniPhier LD11 TV SoC, each with their reference boards.

  There are three new machines added for existing SoC platforms:

   - The Marvell Armada 8040 development board is an impressive
     quad-core Cortex-A72 machine with three 10gbit ethernet interfaces

   - Qualcomms DragonBoard 820c single-board computer is their current
     high-end phone platform in the 96boards form factor

   - Rockchip: Tronsmart Orion r86 set-top-box is a popular mid-range
     Android box based on the 8-core rk3368 SoC"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (91 commits)
  arm64: dts: berlin4ct: Add L2 cache topology
  arm64: dts: berlin4ct: enable all wdt nodes unconditionally
  arm64: dts: berlin4ct: switch to Cortex-A53 specific pmu nodes
  arm64: dts: Add ZTE ZX296718 SoC dts and Makefile
  arm64: dts: apm: Add DT node for APM X-Gene 2 CPU clocks
  arm64: dts: apm: Add X-Gene SoC hwmon to device tree
  arm64: dts: apm: Fix interrupt polarity for X-Gene PCIe legacy interrupts
  arm64: dts: apm: Add APM X-Gene v2 SoC PMU DTS entries
  arm64: dts: apm: Add APM X-Gene SoC PMU DTS entries
  arm64: dts: marvell: enable MSI for PCIe on Armada 7K/8K
  arm64: dts: ls2080a: Add 'dma-coherent' for ls2080a PCI nodes
  arm64: dts: rockchip: add Type-C phy for RK3399
  arm64: dts: rockchip: enable the gmac for rk3399 evb board
  arm64: dts: rockchip: add the gmac needed node for rk3399
  arm64: dts: rockchip: support the pmu node for rk3399
  arm64: dts: rockchip: change all interrupts cells to 4 on rk3399 SoCs
  arm64: dts: rockchip: add the tcpc for rk3399 power domain
  arm64: dts: rockchip: add efuse0 device node for rk3399
  arm64: dts: rockchip: configure PCIe support for rk3399-evb
  arm64: dts: rockchip: add the PCIe controller support for RK3399
  ...
This commit is contained in:
Linus Torvalds 2016-10-07 21:32:39 -07:00
commit a439f8f287
57 changed files with 4239 additions and 371 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

39
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt
View file

@ -175,38 +175,55 @@ Example:
};
-----------------------------------------------------------------------
Hisilicon HiP05 PCIe-SAS system controller
Hisilicon HiP05/HiP06 PCIe-SAS sub system controller
Required properties:
- compatible : "hisilicon,pcie-sas-subctrl", "syscon";
- reg : Register address and size
The HiP05 PCIe-SAS system controller is shared by PCIe and SAS controllers in
HiP05 Soc to implement some basic configurations.
The PCIe-SAS sub system controller is shared by PCIe and SAS controllers in
HiP05 or HiP06 Soc to implement some basic configurations.
Example:
/* for HiP05 PCIe-SAS system */
pcie_sas: system_controller@0xb0000000 {
/* for HiP05 PCIe-SAS sub system */
pcie_sas: system_controller@b0000000 {
compatible = "hisilicon,pcie-sas-subctrl", "syscon";
reg = <0xb0000000 0x10000>;
};
Hisilicon HiP05 PERISUB system controller
Hisilicon HiP05/HiP06 PERI sub system controller
Required properties:
- compatible : "hisilicon,hip05-perisubc", "syscon";
- compatible : "hisilicon,peri-subctrl", "syscon";
- reg : Register address and size
The HiP05 PERISUB system controller is shared by peripheral controllers in
HiP05 Soc to implement some basic configurations. The peripheral
The PERI sub system controller is shared by peripheral controllers in
HiP05 or HiP06 Soc to implement some basic configurations. The peripheral
controllers include mdio, ddr, iic, uart, timer and so on.
Example:
/* for HiP05 perisub-ctrl-c system */
/* for HiP05 sub peri system */
peri_c_subctrl: syscon@80000000 {
compatible = "hisilicon,hip05-perisubc", "syscon";
compatible = "hisilicon,peri-subctrl", "syscon";
reg = <0x0 0x80000000 0x0 0x10000>;
};
Hisilicon HiP05/HiP06 DSA sub system controller
Required properties:
- compatible : "hisilicon,dsa-subctrl", "syscon";
- reg : Register address and size
The DSA sub system controller is shared by peripheral controllers in
HiP05 or HiP06 Soc to implement some basic configurations.
Example:
/* for HiP05 dsa sub system */
pcie_sas: system_controller@a0000000 {
compatible = "hisilicon,dsa-subctrl", "syscon";
reg = <0xa0000000 0x10000>;
};
-----------------------------------------------------------------------
Hisilicon CPU controller

4
Documentation/devicetree/bindings/arm/rockchip.txt
View file

@ -121,3 +121,7 @@ Rockchip platforms device tree bindings
- Rockchip RK3399 evb:
Required root node properties:
- compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
- Tronsmart Orion R68 Meta
Required root node properties:
- compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";

24
Documentation/devicetree/bindings/arm/zte.txt
View file

@ -13,3 +13,27 @@ Low power management required properties:
Bus matrix required properties:
- compatible = "zte,zx-bus-matrix"
---------------------------------------
- ZX296718 SoC:
Required root node properties:
- compatible = "zte,zx296718"
ZX296718 EVB board:
- "zte,zx296718-evb"
System management required properties:
- compatible = "zte,zx296718-aon-sysctrl"
- compatible = "zte,zx296718-sysctrl"
Example:
aon_sysctrl: aon-sysctrl@116000 {
compatible = "zte,zx296718-aon-sysctrl", "syscon";
reg = <0x116000 0x1000>;
};
sysctrl: sysctrl@1463000 {
compatible = "zte,zx296718-sysctrl", "syscon";
reg = <0x1463000 0x1000>;
};

2
arch/arm64/Kconfig.platforms
View file

@ -172,6 +172,8 @@ config ARCH_TEGRA
select GENERIC_CLOCKEVENTS
select GPIOLIB
select PINCTRL
select PM
select PM_GENERIC_DOMAINS
select RESET_CONTROLLER
help
This enables support for the NVIDIA Tegra SoC family.

1
arch/arm64/boot/dts/Makefile
View file

@ -19,6 +19,7 @@ dts-dirs += socionext
dts-dirs += sprd
dts-dirs += xilinx
dts-dirs += lg
dts-dirs += zte
subdir-y := $(dts-dirs)

135
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
View file

@ -26,6 +26,8 @@
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_0>;
#clock-cells = <1>;
clocks = <&pmd0clk 0>;
};
cpu@001 {
device_type = "cpu";
@ -34,6 +36,8 @@
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_0>;
#clock-cells = <1>;
clocks = <&pmd0clk 0>;
};
cpu@100 {
device_type = "cpu";
@ -42,6 +46,8 @@
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_1>;
#clock-cells = <1>;
clocks = <&pmd1clk 0>;
};
cpu@101 {
device_type = "cpu";
@ -50,6 +56,8 @@
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_1>;
#clock-cells = <1>;
clocks = <&pmd1clk 0>;
};
cpu@200 {
device_type = "cpu";
@ -58,6 +66,8 @@
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_2>;
#clock-cells = <1>;
clocks = <&pmd2clk 0>;
};
cpu@201 {
device_type = "cpu";
@ -66,6 +76,8 @@
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_2>;
#clock-cells = <1>;
clocks = <&pmd2clk 0>;
};
cpu@300 {
device_type = "cpu";
@ -74,6 +86,8 @@
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_3>;
#clock-cells = <1>;
clocks = <&pmd3clk 0>;
};
cpu@301 {
device_type = "cpu";
@ -82,6 +96,8 @@
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
next-level-cache = <&xgene_L2_3>;
#clock-cells = <1>;
clocks = <&pmd3clk 0>;
};
xgene_L2_0: l2-cache-0 {
compatible = "cache";
@ -223,6 +239,46 @@
clock-output-names = "refclk";
};
pmdpll: pmdpll@170000f0 {
compatible = "apm,xgene-pcppll-v2-clock";
#clock-cells = <1>;
clocks = <&refclk 0>;
reg = <0x0 0x170000f0 0x0 0x10>;
clock-output-names = "pmdpll";
};
pmd0clk: pmd0clk@7e200200 {
compatible = "apm,xgene-pmd-clock";
#clock-cells = <1>;
clocks = <&pmdpll 0>;
reg = <0x0 0x7e200200 0x0 0x10>;
clock-output-names = "pmd0clk";
};
pmd1clk: pmd1clk@7e200210 {
compatible = "apm,xgene-pmd-clock";
#clock-cells = <1>;
clocks = <&pmdpll 0>;
reg = <0x0 0x7e200210 0x0 0x10>;
clock-output-names = "pmd1clk";
};
pmd2clk: pmd2clk@7e200220 {
compatible = "apm,xgene-pmd-clock";
#clock-cells = <1>;
clocks = <&pmdpll 0>;
reg = <0x0 0x7e200220 0x0 0x10>;
clock-output-names = "pmd2clk";
};
pmd3clk: pmd3clk@7e200230 {
compatible = "apm,xgene-pmd-clock";
#clock-cells = <1>;
clocks = <&pmdpll 0>;
reg = <0x0 0x7e200230 0x0 0x10>;
clock-output-names = "pmd3clk";
};
socpll: socpll@17000120 {
compatible = "apm,xgene-socpll-v2-clock";
#clock-cells = <1>;
@ -453,6 +509,64 @@
};
};
pmu: pmu@78810000 {
compatible = "apm,xgene-pmu-v2";
#address-cells = <2>;
#size-cells = <2>;
ranges;
regmap-csw = <&csw>;
regmap-mcba = <&mcba>;
regmap-mcbb = <&mcbb>;
reg = <0x0 0x78810000 0x0 0x1000>;
interrupts = <0x0 0x22 0x4>;
pmul3c@7e610000 {
compatible = "apm,xgene-pmu-l3c";
reg = <0x0 0x7e610000 0x0 0x1000>;
};
pmuiob@7e940000 {
compatible = "apm,xgene-pmu-iob";
reg = <0x0 0x7e940000 0x0 0x1000>;
};
pmucmcb@7e710000 {
compatible = "apm,xgene-pmu-mcb";
reg = <0x0 0x7e710000 0x0 0x1000>;
enable-bit-index = <0>;
};
pmucmcb@7e730000 {
compatible = "apm,xgene-pmu-mcb";
reg = <0x0 0x7e730000 0x0 0x1000>;
enable-bit-index = <1>;
};
pmucmc@7e810000 {
compatible = "apm,xgene-pmu-mc";
reg = <0x0 0x7e810000 0x0 0x1000>;
enable-bit-index = <0>;
};
pmucmc@7e850000 {
compatible = "apm,xgene-pmu-mc";
reg = <0x0 0x7e850000 0x0 0x1000>;
enable-bit-index = <1>;
};
pmucmc@7e890000 {
compatible = "apm,xgene-pmu-mc";
reg = <0x0 0x7e890000 0x0 0x1000>;
enable-bit-index = <2>;
};
pmucmc@7e8d0000 {
compatible = "apm,xgene-pmu-mc";
reg = <0x0 0x7e8d0000 0x0 0x1000>;
enable-bit-index = <3>;
};
};
mailbox: mailbox@10540000 {
compatible = "apm,xgene-slimpro-mbox";
reg = <0x0 0x10540000 0x0 0x8000>;
@ -472,6 +586,11 @@
mboxes = <&mailbox 0>;
};
hwmonslimpro {
compatible = "apm,xgene-slimpro-hwmon";
mboxes = <&mailbox 7>;
};
serial0: serial@10600000 {
device_type = "serial";
compatible = "ns16550";
@ -508,10 +627,10 @@
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x1
0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x1
0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x1
0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x1>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x4
0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x4
0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x4
0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x4>;
dma-coherent;
clocks = <&pcie0clk 0>;
msi-parent = <&v2m0>;
@ -533,10 +652,10 @@
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x1
0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x1
0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x1
0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x1>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x4
0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x4
0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x4
0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x4>;
dma-coherent;
clocks = <&pcie1clk 0>;
msi-parent = <&v2m0>;

103
arch/arm64/boot/dts/apm/apm-storm.dtsi
View file

@ -553,6 +553,64 @@
};
};
pmu: pmu@78810000 {
compatible = "apm,xgene-pmu-v2";
#address-cells = <2>;
#size-cells = <2>;
ranges;
regmap-csw = <&csw>;
regmap-mcba = <&mcba>;
regmap-mcbb = <&mcbb>;
reg = <0x0 0x78810000 0x0 0x1000>;
interrupts = <0x0 0x22 0x4>;
pmul3c@7e610000 {
compatible = "apm,xgene-pmu-l3c";
reg = <0x0 0x7e610000 0x0 0x1000>;
};
pmuiob@7e940000 {
compatible = "apm,xgene-pmu-iob";
reg = <0x0 0x7e940000 0x0 0x1000>;
};
pmucmcb@7e710000 {
compatible = "apm,xgene-pmu-mcb";
reg = <0x0 0x7e710000 0x0 0x1000>;
enable-bit-index = <0>;
};
pmucmcb@7e730000 {
compatible = "apm,xgene-pmu-mcb";
reg = <0x0 0x7e730000 0x0 0x1000>;
enable-bit-index = <1>;
};
pmucmc@7e810000 {
compatible = "apm,xgene-pmu-mc";
reg = <0x0 0x7e810000 0x0 0x1000>;
enable-bit-index = <0>;
};
pmucmc@7e850000 {
compatible = "apm,xgene-pmu-mc";
reg = <0x0 0x7e850000 0x0 0x1000>;
enable-bit-index = <1>;
};
pmucmc@7e890000 {
compatible = "apm,xgene-pmu-mc";
reg = <0x0 0x7e890000 0x0 0x1000>;
enable-bit-index = <2>;
};
pmucmc@7e8d0000 {
compatible = "apm,xgene-pmu-mc";
reg = <0x0 0x7e8d0000 0x0 0x1000>;
enable-bit-index = <3>;
};
};
pcie0: pcie@1f2b0000 {
status = "disabled";
device_type = "pci";
@ -569,10 +627,10 @@
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4
0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4
0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>;
dma-coherent;
clocks = <&pcie0clk 0>;
msi-parent = <&msi>;
@ -594,10 +652,10 @@
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1
0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4
0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4
0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>;
dma-coherent;
clocks = <&pcie1clk 0>;
msi-parent = <&msi>;
@ -619,10 +677,10 @@
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1
0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4
0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4
0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>;
dma-coherent;
clocks = <&pcie2clk 0>;
msi-parent = <&msi>;
@ -644,10 +702,10 @@
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1
0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4
0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4
0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>;
dma-coherent;
clocks = <&pcie3clk 0>;
msi-parent = <&msi>;
@ -669,10 +727,10 @@
dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1
0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4
0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4
0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>;
dma-coherent;
clocks = <&pcie4clk 0>;
msi-parent = <&msi>;
@ -697,6 +755,11 @@
mboxes = <&mailbox 0>;
};
hwmonslimpro {
compatible = "apm,xgene-slimpro-hwmon";
mboxes = <&mailbox 7>;
};
serial0: serial@1c020000 {
status = "disabled";
device_type = "serial";

8
arch/arm64/boot/dts/broadcom/ns2.dtsi
View file

@ -299,6 +299,14 @@
};
};
pwm: pwm@66010000 {
compatible = "brcm,iproc-pwm";
reg = <0x66010000 0x28>;
clocks = <&osc>;
#pwm-cells = <3>;
status = "disabled";
};
mdio_mux_iproc: mdio-mux@6602023c {
compatible = "brcm,mdio-mux-iproc";
reg = <0x6602023c 0x14>;

13
arch/arm64/boot/dts/exynos/exynos7.dtsi
View file

@ -10,6 +10,7 @@
*/
#include <dt-bindings/clock/exynos7-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "samsung,exynos7";
@ -473,10 +474,14 @@
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0xff08>,
<1 14 0xff08>,
<1 11 0xff08>,
<1 10 0xff08>;
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu_system_controller: system-controller@105c0000 {

14
arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
View file

@ -56,12 +56,14 @@
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
serial0 = &lpuart0;
serial1 = &lpuart1;
serial2 = &lpuart2;
serial3 = &lpuart3;
serial4 = &lpuart4;
serial5 = &lpuart5;
serial0 = &duart0;
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
};

8
arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
View file

@ -52,6 +52,14 @@
aliases {
crypto = &crypto;
serial0 = &duart0;
serial1 = &duart1;
serial2 = &duart2;
serial3 = &duart3;
};
chosen {
stdout-path = "serial0:115200n8";
};
};

7
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
View file

@ -247,6 +247,13 @@
bus-width = <4>;
};
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
interrupts = <0 144 0x4>;
big-endian;
};
dspi0: dspi@2100000 {
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;

3
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
View file

@ -57,6 +57,9 @@
serial1 = &serial1;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&esdhc {

4
arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
View file

@ -56,6 +56,10 @@
serial0 = &serial0;
serial1 = &serial1;
};
chosen {
stdout-path = "serial1:115200n8";
};
};
&esdhc {

18
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
View file

@ -588,6 +588,7 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -612,6 +613,7 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -636,6 +638,7 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -660,6 +663,7 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-lanes = <4>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
@ -715,4 +719,18 @@
interrupts = <0 12 4>;
};
};
ddr1: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
interrupts = <0 17 0x4>;
little-endian;
};
ddr2: memory-controller@1090000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1090000 0x0 0x1000>;
interrupts = <0 18 0x4>;
little-endian;
};
};

86
arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
View file

@ -29,16 +29,56 @@
* Reserve below regions from memory node:
*
* 0x05e0,0000 - 0x05ef,ffff: MCU firmware runtime using
* 0x05f0,1000 - 0x05f0,1fff: Reboot reason
* 0x06df,f000 - 0x06df,ffff: Mailbox message data
* 0x0740,f000 - 0x0740,ffff: MCU firmware section
* 0x21f0,0000 - 0x21ff,ffff: pstore/ramoops buffer
* 0x3e00,0000 - 0x3fff,ffff: OP-TEE
*/
memory@0 {
device_type = "memory";
reg = <0x00000000 0x00000000 0x00000000 0x05e00000>,
<0x00000000 0x05f00000 0x00000000 0x00eff000>,
<0x00000000 0x05f00000 0x00000000 0x00001000>,
<0x00000000 0x05f02000 0x00000000 0x00efd000>,
<0x00000000 0x06e00000 0x00000000 0x0060f000>,
<0x00000000 0x07410000 0x00000000 0x36bf0000>;
<0x00000000 0x07410000 0x00000000 0x1aaf0000>,
<0x00000000 0x22000000 0x00000000 0x1c000000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
ramoops@0x21f00000 {
compatible = "ramoops";
reg = <0x0 0x21f00000 0x0 0x00100000>;
record-size = <0x00020000>;
console-size = <0x00020000>;
ftrace-size = <0x00020000>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x00000000 0x08000000>;
linux,cma-default;
};
};
reboot-mode-syscon@5f01000 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x05f01000 0x0 0x00001000>;
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x0>;
mode-normal = <0x77665501>;
mode-bootloader = <0x77665500>;
mode-recovery = <0x77665502>;
};
};
soc {
@ -55,6 +95,8 @@
};
uart1: uart@f7111000 {
assigned-clocks = <&sys_ctrl HI6220_UART1_SRC>;
assigned-clock-rates = <150000000>;
status = "ok";
};
@ -372,3 +414,43 @@
&uart3 {
label = "LS-UART1";
};
&ade {
status = "ok";
};
&dsi {
status = "ok";
ports {
/* 1 for output port */
port@1 {
reg = <1>;
dsi_out0: endpoint@0 {
remote-endpoint = <&adv7533_in>;
};
};
};
};
&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
status = "ok";
adv7533: adv7533@39 {
compatible = "adi,adv7533";
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <1 2>;
pd-gpio = <&gpio0 4 0>;
adi,dsi-lanes = <4>;
port {
adv7533_in: endpoint {
remote-endpoint = <&dsi_out0>;
};
};
};
};

61
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View file

@ -262,6 +262,11 @@
#clock-cells = <1>;
};
medianoc_ade: medianoc_ade@f4520000 {
compatible = "syscon";
reg = <0x0 0xf4520000 0x0 0x4000>;
};
stub_clock: stub_clock {
compatible = "hisilicon,hi6220-stub-clk";
hisilicon,hi6220-clk-sram = <&sram>;
@ -766,6 +771,7 @@
interrupts = <0x0 0x48 0x4>;
clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
clock-names = "ciu", "biu";
resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
bus-width = <0x8>;
vmmc-supply = <&ldo19>;
pinctrl-names = "default";
@ -779,12 +785,16 @@
card-detect-delay = <200>;
hisilicon,peripheral-syscon = <&ao_ctrl>;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
reg = <0x0 0xf723e000 0x0 0x1000>;
interrupts = <0x0 0x49 0x4>;
#address-cells = <0x1>;
#size-cells = <0x0>;
clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
clock-names = "ciu", "biu";
resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
vqmmc-supply = <&ldo7>;
vmmc-supply = <&ldo10>;
bus-width = <0x4>;
@ -802,6 +812,7 @@
interrupts = <0x0 0x4a 0x4>;
clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
clock-names = "ciu", "biu";
resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
bus-width = <0x4>;
broken-cd;
pinctrl-names = "default", "idle";
@ -850,5 +861,55 @@
};
};
};
ade: ade@f4100000 {
compatible = "hisilicon,hi6220-ade";
reg = <0x0 0xf4100000 0x0 0x7800>;
reg-names = "ade_base";
hisilicon,noc-syscon = <&medianoc_ade>;
resets = <&media_ctrl MEDIA_ADE>;
interrupts = <0 115 4>; /* ldi interrupt */
clocks = <&media_ctrl HI6220_ADE_CORE>,
<&media_ctrl HI6220_CODEC_JPEG>,
<&media_ctrl HI6220_ADE_PIX_SRC>;
/*clock name*/
clock-names = "clk_ade_core",
"clk_codec_jpeg",
"clk_ade_pix";
assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
<&media_ctrl HI6220_CODEC_JPEG>;
assigned-clock-rates = <360000000>, <288000000>;
dma-coherent;
status = "disabled";
port {
ade_out: endpoint {
remote-endpoint = <&dsi_in>;
};
};
};
dsi: dsi@f4107800 {
compatible = "hisilicon,hi6220-dsi";
reg = <0x0 0xf4107800 0x0 0x100>;
clocks = <&media_ctrl HI6220_DSI_PCLK>;
clock-names = "pclk";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* 0 for input port */
port@0 {
reg = <0>;
dsi_in: endpoint {
remote-endpoint = <&ade_out>;
};
};
};
};
};
};

5
arch/arm64/boot/dts/hisilicon/hip05.dtsi
View file

@ -300,11 +300,6 @@
clock-frequency = <200000000>;
};
peri_c_subctrl: syscon@80000000 {
compatible = "hisilicon,hip05-perisubc", "syscon";
reg = < 0x0 0x80000000 0x0 0x10000>;
};
uart0: uart@80300000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x80300000 0x0 0x10000>;

180
arch/arm64/boot/dts/hisilicon/hip05_hns.dtsi
View file

@ -1,180 +0,0 @@
soc0: soc@000000000 {
#address-cells = <2>;
#size-cells = <2>;
device_type = "soc";
compatible = "simple-bus";
ranges = <0x0 0x0 0x0 0x0 0x1 0x0>;
chip-id = <0>;
soc0_mdio0: mdio@803c0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "hisilicon,hns-mdio";
reg = <0x0 0x803c0000 0x0 0x10000>;
subctrl-vbase = <&peri_c_subctrl>;
soc0_phy0: ethernet-phy@0 {
reg = <0x0>;
compatible = "ethernet-phy-ieee802.3-c22";
};
soc0_phy1: ethernet-phy@1 {
reg = <0x1>;
compatible = "ethernet-phy-ieee802.3-c22";
};
};
dsaf0: dsa@c7000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "hisilicon,hns-dsaf-v1";
mode = "6port-16rss";
interrupt-parent = <&mbigen_dsa>;
reg = <0x0 0xc5000000 0x0 0x890000
0x0 0xc7000000 0x0 0x60000
>;
reg-names = "ppe-base","dsaf-base";
subctrl-syscon = <&dsaf_subctrl>;
reset-field-offset = <0>;
interrupts = <
/* [14] ge fifo err 8 / xge 6**/
149 0x4 150 0x4 151 0x4 152 0x4
153 0x4 154 0x4 26 0x4 27 0x4
155 0x4 156 0x4 157 0x4 158 0x4 159 0x4 160 0x4
/* [12] rcb com 4*3**/
0x6 0x4 0x7 0x4 0x8 0x4 0x9 0x4
16 0x4 17 0x4 18 0x4 19 0x4
22 0x4 23 0x4 24 0x4 25 0x4
/* [8] ppe tnl 0-7***/
0x0 0x4 0x1 0x4 0x2 0x4 0x3 0x4
0x4 0x4 0x5 0x4 12 0x4 13 0x4
/* [21] dsaf event int 3+18**/
128 0x4 129 0x4 130 0x4
0x83 0x4 0x84 0x4 0x85 0x4 0x86 0x4 0x87 0x4 0x88 0x4
0x89 0x4 0x8a 0x4 0x8b 0x4 0x8c 0x4 0x8d 0x4 0x8e 0x4
0x8f 0x4 0x90 0x4 0x91 0x4 0x92 0x4 0x93 0x4 0x94 0x4
/* [4] debug rcb 2*2*/
0xe 0x1 0xf 0x1 0x14 0x1 0x15 0x1
/* [256] sevice rcb 2*128*/
0x180 0x1 0x181 0x1 0x182 0x1 0x183 0x1
0x184 0x1 0x185 0x1 0x186 0x1 0x187 0x1
0x188 0x1 0x189 0x1 0x18a 0x1 0x18b 0x1
0x18c 0x1 0x18d 0x1 0x18e 0x1 0x18f 0x1
0x190 0x1 0x191 0x1 0x192 0x1 0x193 0x1
0x194 0x1 0x195 0x1 0x196 0x1 0x197 0x1
0x198 0x1 0x199 0x1 0x19a 0x1 0x19b 0x1
0x19c 0x1 0x19d 0x1 0x19e 0x1 0x19f 0x1
0x1a0 0x1 0x1a1 0x1 0x1a2 0x1 0x1a3 0x1
0x1a4 0x1 0x1a5 0x1 0x1a6 0x1 0x1a7 0x1
0x1a8 0x1 0x1a9 0x1 0x1aa 0x1 0x1ab 0x1
0x1ac 0x1 0x1ad 0x1 0x1ae 0x1 0x1af 0x1
0x1b0 0x1 0x1b1 0x1 0x1b2 0x1 0x1b3 0x1
0x1b4 0x1 0x1b5 0x1 0x1b6 0x1 0x1b7 0x1
0x1b8 0x1 0x1b9 0x1 0x1ba 0x1 0x1bb 0x1
0x1bc 0x1 0x1bd 0x1 0x1be 0x1 0x1bf 0x1
0x1c0 0x1 0x1c1 0x1 0x1c2 0x1 0x1c3 0x1
0x1c4 0x1 0x1c5 0x1 0x1c6 0x1 0x1c7 0x1
0x1c8 0x1 0x1c9 0x1 0x1ca 0x1 0x1cb 0x1
0x1cc 0x1 0x1cd 0x1 0x1ce 0x1 0x1cf 0x1
0x1d0 0x1 0x1d1 0x1 0x1d2 0x1 0x1d3 0x1
0x1d4 0x1 0x1d5 0x1 0x1d6 0x1 0x1d7 0x1
0x1d8 0x1 0x1d9 0x1 0x1da 0x1 0x1db 0x1
0x1dc 0x1 0x1dd 0x1 0x1de 0x1 0x1df 0x1
0x1e0 0x1 0x1e1 0x1 0x1e2 0x1 0x1e3 0x1
0x1e4 0x1 0x1e5 0x1 0x1e6 0x1 0x1e7 0x1
0x1e8 0x1 0x1e9 0x1 0x1ea 0x1 0x1eb 0x1
0x1ec 0x1 0x1ed 0x1 0x1ee 0x1 0x1ef 0x1
0x1f0 0x1 0x1f1 0x1 0x1f2 0x1 0x1f3 0x1
0x1f4 0x1 0x1f5 0x1 0x1f6 0x1 0x1f7 0x1
0x1f8 0x1 0x1f9 0x1 0x1fa 0x1 0x1fb 0x1
0x1fc 0x1 0x1fd 0x1 0x1fe 0x1 0x1ff 0x1
0x200 0x1 0x201 0x1 0x202 0x1 0x203 0x1
0x204 0x1 0x205 0x1 0x206 0x1 0x207 0x1
0x208 0x1 0x209 0x1 0x20a 0x1 0x20b 0x1
0x20c 0x1 0x20d 0x1 0x20e 0x1 0x20f 0x1
0x210 0x1 0x211 0x1 0x212 0x1 0x213 0x1
0x214 0x1 0x215 0x1 0x216 0x1 0x217 0x1
0x218 0x1 0x219 0x1 0x21a 0x1 0x21b 0x1
0x21c 0x1 0x21d 0x1 0x21e 0x1 0x21f 0x1
0x220 0x1 0x221 0x1 0x222 0x1 0x223 0x1
0x224 0x1 0x225 0x1 0x226 0x1 0x227 0x1
0x228 0x1 0x229 0x1 0x22a 0x1 0x22b 0x1
0x22c 0x1 0x22d 0x1 0x22e 0x1 0x22f 0x1
0x230 0x1 0x231 0x1 0x232 0x1 0x233 0x1
0x234 0x1 0x235 0x1 0x236 0x1 0x237 0x1
0x238 0x1 0x239 0x1 0x23a 0x1 0x23b 0x1
0x23c 0x1 0x23d 0x1 0x23e 0x1 0x23f 0x1
0x240 0x1 0x241 0x1 0x242 0x1 0x243 0x1
0x244 0x1 0x245 0x1 0x246 0x1 0x247 0x1
0x248 0x1 0x249 0x1 0x24a 0x1 0x24b 0x1
0x24c 0x1 0x24d 0x1 0x24e 0x1 0x24f 0x1
0x250 0x1 0x251 0x1 0x252 0x1 0x253 0x1
0x254 0x1 0x255 0x1 0x256 0x1 0x257 0x1
0x258 0x1 0x259 0x1 0x25a 0x1 0x25b 0x1
0x25c 0x1 0x25d 0x1 0x25e 0x1 0x25f 0x1
0x260 0x1 0x261 0x1 0x262 0x1 0x263 0x1
0x264 0x1 0x265 0x1 0x266 0x1 0x267 0x1
0x268 0x1 0x269 0x1 0x26a 0x1 0x26b 0x1
0x26c 0x1 0x26d 0x1 0x26e 0x1 0x26f 0x1
0x270 0x1 0x271 0x1 0x272 0x1 0x273 0x1
0x274 0x1 0x275 0x1 0x276 0x1 0x277 0x1
0x278 0x1 0x279 0x1 0x27a 0x1 0x27b 0x1
0x27c 0x1 0x27d 0x1 0x27e 0x1 0x27f 0x1>;
buf-size = <4096>;
desc-num = <1024>;
dma-coherent;
port@0 {
reg = <0>;
serdes-syscon = <&serdes_ctrl0>;
};
port@1 {
reg = <1>;
serdes-syscon = <&serdes_ctrl0>;
};
port@4 {
reg = <4>;
phy-handle = <&soc0_phy0>;
serdes-syscon = <&serdes_ctrl1>;
};
port@5 {
reg = <5>;
phy-handle = <&soc0_phy1>;
serdes-syscon = <&serdes_ctrl1>;
};
};
eth0: ethernet@0{
compatible = "hisilicon,hns-nic-v1";
ae-handle = <&dsaf0>;
port-idx-in-ae = <0>;
local-mac-address = [00 00 00 01 00 58];
status = "disabled";
dma-coherent;
};
eth1: ethernet@1{
compatible = "hisilicon,hns-nic-v1";
ae-handle = <&dsaf0>;
port-idx-in-ae = <1>;
local-mac-address = [00 00 00 01 00 59];
status = "disabled";
dma-coherent;
};
eth2: ethernet@4{
compatible = "hisilicon,hns-nic-v1";
ae-handle = <&dsaf0>;
port-idx-in-ae = <4>;
local-mac-address = [00 00 00 01 00 5a];
status = "disabled";
dma-coherent;
};
eth3: ethernet@5{
compatible = "hisilicon,hns-nic-v1";
ae-handle = <&dsaf0>;
port-idx-in-ae = <5>;
local-mac-address = [00 00 00 01 00 5b];
status = "disabled";
dma-coherent;
};
};

28
arch/arm64/boot/dts/hisilicon/hip06-d03.dts
View file

@ -25,6 +25,34 @@
chosen { };
};
&eth0 {
status = "ok";
};
&eth1 {
status = "ok";
};
&eth2 {
status = "ok";
};
&eth3 {
status = "ok";
};
&sas0 {
status = "ok";
};
&sas1 {
status = "ok";
};
&sas2 {
status = "ok";
};
&usb_ohci {
status = "ok";
};

365
arch/arm64/boot/dts/hisilicon/hip06.dtsi
View file

@ -277,6 +277,39 @@
#interrupt-cells = <2>;
num-pins = <2>;
};
mbigen_sas1: intc_sas1 {
msi-parent = <&its_dsa 0x40000>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <128>;
};
mbigen_sas2: intc_sas2 {
msi-parent = <&its_dsa 0x40040>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <128>;
};
};
mbigen_dsa@c0080000 {
compatible = "hisilicon,mbigen-v2";
reg = <0x0 0xc0080000 0x0 0x10000>;
mbigen_dsaf0: intc_dsaf0 {
msi-parent = <&its_dsa 0x40800>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <409>;
};
mbigen_sas0: intc-sas0 {
msi-parent = <&its_dsa 0x40900>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <128>;
};
};
soc {
@ -302,6 +335,338 @@
dma-coherent;
status = "disabled";
};
peri_c_subctrl: sub_ctrl_c@60000000 {
compatible = "hisilicon,peri-subctrl","syscon";
reg = <0 0x60000000 0x0 0x10000>;
};
dsa_subctrl: dsa_subctrl@c0000000 {
compatible = "hisilicon,dsa-subctrl", "syscon";
reg = <0x0 0xc0000000 0x0 0x10000>;
};
pcie_subctl: pcie_subctl@a0000000 {
compatible = "hisilicon,pcie-sas-subctrl", "syscon";
reg = <0x0 0xa0000000 0x0 0x10000>;
};
serdes_ctrl: sds_ctrl@c2200000 {
compatible = "syscon";
reg = <0 0xc2200000 0x0 0x80000>;
};
mdio@603c0000 {
compatible = "hisilicon,hns-mdio";
reg = <0x0 0x603c0000 0x0 0x1000>;
subctrl-vbase = <&peri_c_subctrl 0x338 0xa38 0x531c 0x5a1c>;
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
};
};
dsaf0: dsa@c7000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "hisilicon,hns-dsaf-v2";
mode = "6port-16rss";
reg = <0x0 0xc5000000 0x0 0x890000
0x0 0xc7000000 0x0 0x600000>;
reg-names = "ppe-base", "dsaf-base";
interrupt-parent = <&mbigen_dsaf0>;
subctrl-syscon = <&dsa_subctrl>;
reset-field-offset = <0>;
interrupts =
<576 1>, <577 1>, <578 1>, <579 1>, <580 1>,
<581 1>, <582 1>, <583 1>, <584 1>, <585 1>,
<586 1>, <587 1>, <588 1>, <589 1>, <590 1>,
<591 1>, <592 1>, <593 1>, <594 1>, <595 1>,
<596 1>, <597 1>, <598 1>, <599 1>, <600 1>,
<960 1>, <961 1>, <962 1>, <963 1>, <964 1>,
<965 1>, <966 1>, <967 1>, <968 1>, <969 1>,
<970 1>, <971 1>, <972 1>, <973 1>, <974 1>,
<975 1>, <976 1>, <977 1>, <978 1>, <979 1>,
<980 1>, <981 1>, <982 1>, <983 1>, <984 1>,
<985 1>, <986 1>, <987 1>, <988 1>, <989 1>,
<990 1>, <991 1>, <992 1>, <993 1>, <994 1>,
<995 1>, <996 1>, <997 1>, <998 1>, <999 1>,
<1000 1>, <1001 1>, <1002 1>, <1003 1>, <1004 1>,
<1005 1>, <1006 1>, <1007 1>, <1008 1>, <1009 1>,
<1010 1>, <1011 1>, <1012 1>, <1013 1>, <1014 1>,
<1015 1>, <1016 1>, <1017 1>, <1018 1>, <1019 1>,
<1020 1>, <1021 1>, <1022 1>, <1023 1>, <1024 1>,
<1025 1>, <1026 1>, <1027 1>, <1028 1>, <1029 1>,
<1030 1>, <1031 1>, <1032 1>, <1033 1>, <1034 1>,
<1035 1>, <1036 1>, <1037 1>, <1038 1>, <1039 1>,
<1040 1>, <1041 1>, <1042 1>, <1043 1>, <1044 1>,
<1045 1>, <1046 1>, <1047 1>, <1048 1>, <1049 1>,
<1050 1>, <1051 1>, <1052 1>, <1053 1>, <1054 1>,
<1055 1>, <1056 1>, <1057 1>, <1058 1>, <1059 1>,
<1060 1>, <1061 1>, <1062 1>, <1063 1>, <1064 1>,
<1065 1>, <1066 1>, <1067 1>, <1068 1>, <1069 1>,
<1070 1>, <1071 1>, <1072 1>, <1073 1>, <1074 1>,
<1075 1>, <1076 1>, <1077 1>, <1078 1>, <1079 1>,
<1080 1>, <1081 1>, <1082 1>, <1083 1>, <1084 1>,
<1085 1>, <1086 1>, <1087 1>, <1088 1>, <1089 1>,
<1090 1>, <1091 1>, <1092 1>, <1093 1>, <1094 1>,
<1095 1>, <1096 1>, <1097 1>, <1098 1>, <1099 1>,
<1100 1>, <1101 1>, <1102 1>, <1103 1>, <1104 1>,
<1105 1>, <1106 1>, <1107 1>, <1108 1>, <1109 1>,
<1110 1>, <1111 1>, <1112 1>, <1113 1>, <1114 1>,
<1115 1>, <1116 1>, <1117 1>, <1118 1>, <1119 1>,
<1120 1>, <1121 1>, <1122 1>, <1123 1>, <1124 1>,
<1125 1>, <1126 1>, <1127 1>, <1128 1>, <1129 1>,
<1130 1>, <1131 1>, <1132 1>, <1133 1>, <1134 1>,
<1135 1>, <1136 1>, <1137 1>, <1138 1>, <1139 1>,
<1140 1>, <1141 1>, <1142 1>, <1143 1>, <1144 1>,
<1145 1>, <1146 1>, <1147 1>, <1148 1>, <1149 1>,
<1150 1>, <1151 1>, <1152 1>, <1153 1>, <1154 1>,
<1155 1>, <1156 1>, <1157 1>, <1158 1>, <1159 1>,
<1160 1>, <1161 1>, <1162 1>, <1163 1>, <1164 1>,
<1165 1>, <1166 1>, <1167 1>, <1168 1>, <1169 1>,
<1170 1>, <1171 1>, <1172 1>, <1173 1>, <1174 1>,
<1175 1>, <1176 1>, <1177 1>, <1178 1>, <1179 1>,
<1180 1>, <1181 1>, <1182 1>, <1183 1>, <1184 1>,
<1185 1>, <1186 1>, <1187 1>, <1188 1>, <1189 1>,
<1190 1>, <1191 1>, <1192 1>, <1193 1>, <1194 1>,
<1195 1>, <1196 1>, <1197 1>, <1198 1>, <1199 1>,
<1200 1>, <1201 1>, <1202 1>, <1203 1>, <1204 1>,
<1205 1>, <1206 1>, <1207 1>, <1208 1>, <1209 1>,
<1210 1>, <1211 1>, <1212 1>, <1213 1>, <1214 1>,
<1215 1>, <1216 1>, <1217 1>, <1218 1>, <1219 1>,
<1220 1>, <1221 1>, <1222 1>, <1223 1>, <1224 1>,
<1225 1>, <1226 1>, <1227 1>, <1228 1>, <1229 1>,
<1230 1>, <1231 1>, <1232 1>, <1233 1>, <1234 1>,
<1235 1>, <1236 1>, <1237 1>, <1238 1>, <1239 1>,
<1240 1>, <1241 1>, <1242 1>, <1243 1>, <1244 1>,
<1245 1>, <1246 1>, <1247 1>, <1248 1>, <1249 1>,
<1250 1>, <1251 1>, <1252 1>, <1253 1>, <1254 1>,
<1255 1>, <1256 1>, <1257 1>, <1258 1>, <1259 1>,
<1260 1>, <1261 1>, <1262 1>, <1263 1>, <1264 1>,
<1265 1>, <1266 1>, <1267 1>, <1268 1>, <1269 1>,
<1270 1>, <1271 1>, <1272 1>, <1273 1>, <1274 1>,
<1275 1>, <1276 1>, <1277 1>, <1278 1>, <1279 1>,
<1280 1>, <1281 1>, <1282 1>, <1283 1>, <1284 1>,
<1285 1>, <1286 1>, <1287 1>, <1288 1>, <1289 1>,
<1290 1>, <1291 1>, <1292 1>, <1293 1>, <1294 1>,
<1295 1>, <1296 1>, <1297 1>, <1298 1>, <1299 1>,
<1300 1>, <1301 1>, <1302 1>, <1303 1>, <1304 1>,
<1305 1>, <1306 1>, <1307 1>, <1308 1>, <1309 1>,
<1310 1>, <1311 1>, <1312 1>, <1313 1>, <1314 1>,
<1315 1>, <1316 1>, <1317 1>, <1318 1>, <1319 1>,
<1320 1>, <1321 1>, <1322 1>, <1323 1>, <1324 1>,
<1325 1>, <1326 1>, <1327 1>, <1328 1>, <1329 1>,
<1330 1>, <1331 1>, <1332 1>, <1333 1>, <1334 1>,
<1335 1>, <1336 1>, <1337 1>, <1338 1>, <1339 1>,
<1340 1>, <1341 1>, <1342 1>, <1343 1>;
desc-num = <0x400>;
buf-size = <0x1000>;
dma-coherent;
port@0 {
reg = <0>;
serdes-syscon = <&serdes_ctrl>;
port-rst-offset = <0>;
port-mode-offset = <0>;
media-type = "fiber";
};
port@1 {
reg = <1>;
serdes-syscon= <&serdes_ctrl>;
port-rst-offset = <1>;
port-mode-offset = <1>;
media-type = "fiber";
};
port@4 {
reg = <4>;
phy-handle = <&phy0>;
serdes-syscon= <&serdes_ctrl>;
port-rst-offset = <4>;
port-mode-offset = <2>;
media-type = "copper";
};
port@5 {
reg = <5>;
phy-handle = <&phy1>;
serdes-syscon= <&serdes_ctrl>;
port-rst-offset = <5>;
port-mode-offset = <3>;
media-type = "copper";
};
};
eth0: ethernet@4{
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <4>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth1: ethernet@5{
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <5>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth2: ethernet@0{
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <0>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
eth3: ethernet@1{
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <1>;
local-mac-address = [00 00 00 00 00 00];
status = "disabled";
dma-coherent;
};
sas0: sas@c3000000 {
compatible = "hisilicon,hip06-sas-v2";
reg = <0 0xc3000000 0 0x10000>;
sas-addr = [50 01 88 20 16 00 00 00];
hisilicon,sas-syscon = <&dsa_subctrl>;
ctrl-reset-reg = <0xa60>;
ctrl-reset-sts-reg = <0x5a30>;
ctrl-clock-ena-reg = <0x338>;
queue-count = <16>;
phy-count = <8>;
dma-coherent;
interrupt-parent = <&mbigen_sas0>;
interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
<69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
<75 4>,<76 4>,<77 4>,<78 4>,<79 4>,
<80 4>,<81 4>,<82 4>,<83 4>,<84 4>,
<85 4>,<86 4>,<87 4>,<88 4>,<89 4>,
<90 4>,<91 4>,<92 4>,<93 4>,<94 4>,
<95 4>,<96 4>,<97 4>,<98 4>,<99 4>,
<100 4>,<101 4>,<102 4>,<103 4>,<104 4>,
<105 4>,<106 4>,<107 4>,<108 4>,<109 4>,
<110 4>,<111 4>,<112 4>,<113 4>,<114 4>,
<115 4>,<116 4>,<117 4>,<118 4>,<119 4>,
<120 4>,<121 4>,<122 4>,<123 4>,<124 4>,
<125 4>,<126 4>,<127 4>,<128 4>,<129 4>,
<130 4>,<131 4>,<132 4>,<133 4>,<134 4>,
<135 4>,<136 4>,<137 4>,<138 4>,<139 4>,
<140 4>,<141 4>,<142 4>,<143 4>,<144 4>,
<145 4>,<146 4>,<147 4>,<148 4>,<149 4>,
<150 4>,<151 4>,<152 4>,<153 4>,<154 4>,
<155 4>,<156 4>,<157 4>,<158 4>,<159 4>,
<160 4>,<601 1>,<602 1>,<603 1>,<604 1>,
<605 1>,<606 1>,<607 1>,<608 1>,<609 1>,
<610 1>,<611 1>,<612 1>,<613 1>,<614 1>,
<615 1>,<616 1>,<617 1>,<618 1>,<619 1>,
<620 1>,<621 1>,<622 1>,<623 1>,<624 1>,
<625 1>,<626 1>,<627 1>,<628 1>,<629 1>,
<630 1>,<631 1>,<632 1>;
status = "disabled";
};
sas1: sas@a2000000 {
compatible = "hisilicon,hip06-sas-v2";
reg = <0 0xa2000000 0 0x10000>;
sas-addr = [50 01 88 20 16 00 00 00];
hisilicon,sas-syscon = <&pcie_subctl>;
am-max-trans;
ctrl-reset-reg = <0xa18>;
ctrl-reset-sts-reg = <0x5a0c>;
ctrl-clock-ena-reg = <0x318>;
queue-count = <16>;
phy-count = <8>;
dma-coherent;
interrupt-parent = <&mbigen_sas1>;
interrupts = <64 4>,<65 4>,<66 4>,<67 4>,<68 4>,
<69 4>,<70 4>,<71 4>,<72 4>,<73 4>,
<74 4>,<75 4>,<76 4>,<77 4>,<78 4>,
<79 4>,<80 4>,<81 4>,<82 4>,<83 4>,
<84 4>,<85 4>,<86 4>,<87 4>,<88 4>,
<89 4>,<90 4>,<91 4>,<92 4>,<93 4>,
<94 4>,<95 4>,<96 4>,<97 4>,<98 4>,
<99 4>,<100 4>,<101 4>,<102 4>,<103 4>,
<104 4>,<105 4>,<106 4>,<107 4>,<108 4>,
<109 4>,<110 4>,<111 4>,<112 4>,<113 4>,
<114 4>,<115 4>,<116 4>,<117 4>,<118 4>,
<119 4>,<120 4>,<121 4>,<122 4>,<123 4>,
<124 4>,<125 4>,<126 4>,<127 4>,<128 4>,
<129 4>,<130 4>,<131 4>,<132 4>,<133 4>,
<134 4>,<135 4>,<136 4>,<137 4>,<138 4>,
<139 4>,<140 4>,<141 4>,<142 4>,<143 4>,
<144 4>,<145 4>,<146 4>,<147 4>,<148 4>,
<149 4>,<150 4>,<151 4>,<152 4>,<153 4>,
<154 4>,<155 4>,<156 4>,<157 4>,<158 4>,
<159 4>,<576 1>,<577 1>,<578 1>,<579 1>,
<580 1>,<581 1>,<582 1>,<583 1>,<584 1>,
<585 1>,<586 1>,<587 1>,<588 1>,<589 1>,
<590 1>,<591 1>,<592 1>,<593 1>,<594 1>,
<595 1>,<596 1>,<597 1>,<598 1>,<599 1>,
<600 1>,<601 1>,<602 1>,<603 1>,<604 1>,
<605 1>,<606 1>,<607 1>;
status = "disabled";
};
sas2: sas@a3000000 {
compatible = "hisilicon,hip06-sas-v2";
reg = <0 0xa3000000 0 0x10000>;
sas-addr = [50 01 88 20 16 00 00 00];
hisilicon,sas-syscon = <&pcie_subctl>;
ctrl-reset-reg = <0xae0>;
ctrl-reset-sts-reg = <0x5a70>;
ctrl-clock-ena-reg = <0x3a8>;
queue-count = <16>;
phy-count = <9>;
dma-coherent;
interrupt-parent = <&mbigen_sas2>;
interrupts = <192 4>,<193 4>,<194 4>,<195 4>,<196 4>,
<197 4>,<198 4>,<199 4>,<200 4>,<201 4>,
<202 4>,<203 4>,<204 4>,<205 4>,<206 4>,
<207 4>,<208 4>,<209 4>,<210 4>,<211 4>,
<212 4>,<213 4>,<214 4>,<215 4>,<216 4>,
<217 4>,<218 4>,<219 4>,<220 4>,<221 4>,
<222 4>,<223 4>,<224 4>,<225 4>,<226 4>,
<227 4>,<228 4>,<229 4>,<230 4>,<231 4>,
<232 4>,<233 4>,<234 4>,<235 4>,<236 4>,
<237 4>,<238 4>,<239 4>,<240 4>,<241 4>,
<242 4>,<243 4>,<244 4>,<245 4>,<246 4>,
<247 4>,<248 4>,<249 4>,<250 4>,<251 4>,
<252 4>,<253 4>,<254 4>,<255 4>,<256 4>,
<257 4>,<258 4>,<259 4>,<260 4>,<261 4>,
<262 4>,<263 4>,<264 4>,<265 4>,<266 4>,
<267 4>,<268 4>,<269 4>,<270 4>,<271 4>,
<272 4>,<273 4>,<274 4>,<275 4>,<276 4>,
<277 4>,<278 4>,<279 4>,<280 4>,<281 4>,
<282 4>,<283 4>,<284 4>,<285 4>,<286 4>,
<287 4>,<608 1>,<609 1>,<610 1>,<611 1>,
<612 1>,<613 1>,<614 1>,<615 1>,<616 1>,
<617 1>,<618 1>,<619 1>,<620 1>,<621 1>,
<622 1>,<623 1>,<624 1>,<625 1>,<626 1>,
<627 1>,<628 1>,<629 1>,<630 1>,<631 1>,
<632 1>,<633 1>,<634 1>,<635 1>,<636 1>,
<637 1>,<638 1>,<639 1>;
status = "disabled";
};
};
};

1
arch/arm64/boot/dts/marvell/Makefile
View file

@ -5,6 +5,7 @@ dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-stb.dtb
# Mvebu SoC Family
dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-7040-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)

1
arch/arm64/boot/dts/marvell/armada-8020.dtsi
View file

@ -47,6 +47,7 @@
#include "armada-ap806-dual.dtsi"
#include "armada-cp110-master.dtsi"
#include "armada-cp110-slave.dtsi"
/ {
model = "Marvell Armada 8020";

150
arch/arm64/boot/dts/marvell/armada-8040-db.dts Normal file
View file

@ -0,0 +1,150 @@
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Device Tree file for Marvell Armada 8040 Development board platform
*/
#include "armada-8040.dtsi"
/ {
model = "Marvell Armada 8040 DB board";
compatible = "marvell,armada8040-db", "marvell,armada8040",
"marvell,armada-ap806-quad", "marvell,armada-ap806";
chosen {
stdout-path = "serial0:115200n8";
};
memory@00000000 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
&i2c0 {
status = "okay";
clock-frequency = <100000>;
};
&spi0 {
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "U-Boot";
reg = <0 0x200000>;
};
partition@400000 {
label = "Filesystem";
reg = <0x200000 0xce0000>;
};
};
};
};
/* Accessible over the mini-USB CON9 connector on the main board */
&uart0 {
status = "okay";
};
/* CON5 on CP0 expansion */
&cpm_pcie2 {
status = "okay";
};
&cpm_i2c0 {
status = "okay";
clock-frequency = <100000>;
};
/* CON4 on CP0 expansion */
&cpm_sata0 {
status = "okay";
};
/* CON9 on CP0 expansion */
&cpm_usb3_0 {
status = "okay";
};
/* CON10 on CP0 expansion */
&cpm_usb3_1 {
status = "okay";
};
/* CON5 on CP1 expansion */
&cps_pcie2 {
status = "okay";
};
&cps_i2c0 {
status = "okay";
clock-frequency = <100000>;
};
/* CON4 on CP1 expansion */
&cps_sata0 {
status = "okay";
};
/* CON9 on CP1 expansion */
&cps_usb3_0 {
status = "okay";
};
/* CON10 on CP1 expansion */
&cps_usb3_1 {
status = "okay";
};

1
arch/arm64/boot/dts/marvell/armada-8040.dtsi
View file

@ -47,6 +47,7 @@
#include "armada-ap806-quad.dtsi"
#include "armada-cp110-master.dtsi"
#include "armada-cp110-slave.dtsi"
/ {
model = "Marvell Armada 8040";

14
arch/arm64/boot/dts/marvell/armada-ap806.dtsi
View file

@ -128,6 +128,12 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
pmu {
compatible = "arm,cortex-a72-pmu";
interrupt-parent = <&pic>;
interrupts = <17>;
};
odmi: odmi@300000 {
compatible = "marvell,odmi-controller";
interrupt-controller;
@ -140,6 +146,14 @@
marvell,spi-base = <128>, <136>, <144>, <152>;
};
pic: interrupt-controller@3f0100 {
compatible = "marvell,armada-8k-pic";
reg = <0x3f0100 0x10>;
#interrupt-cells = <1>;
interrupt-controller;
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
xor@400000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x400000 0x1000>,

3
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
View file

@ -176,6 +176,7 @@
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
@ -201,6 +202,7 @@
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
@ -227,6 +229,7 @@
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =

249
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi Normal file
View file

@ -0,0 +1,249 @@
/*
* Copyright (C) 2016 Marvell Technology Group Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPLv2 or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/*
* Device Tree file for Marvell Armada CP110 Slave.
*/
/ {
cp110-slave {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
config-space {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf4000000 0x2000000>;
cps_syscon0: system-controller@440000 {
compatible = "marvell,cp110-system-controller0",
"syscon";
reg = <0x440000 0x1000>;
#clock-cells = <2>;
core-clock-output-names =
"cps-apll", "cps-ppv2-core", "cps-eip",
"cps-core", "cps-nand-core";
gate-clock-output-names =
"cps-audio", "cps-communit", "cps-nand",
"cps-ppv2", "cps-sdio", "cps-mg-domain",
"cps-mg-core", "cps-xor1", "cps-xor0",
"cps-gop-dp", "none", "cps-pcie_x10",
"cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
"cps-sata", "cps-sata-usb", "cps-main",
"cps-sd-mmc", "none", "none",
"cps-slow-io", "cps-usb3h0", "cps-usb3h1",
"cps-usb3dev", "cps-eip150", "cps-eip197";
};
cps_sata0: sata@540000 {
compatible = "marvell,armada-8k-ahci";
reg = <0x540000 0x30000>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 15>;
status = "disabled";
};
cps_usb3_0: usb3@500000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 22>;
status = "disabled";
};
cps_usb3_1: usb3@510000 {
compatible = "marvell,armada-8k-xhci",
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 23>;
status = "disabled";
};
cps_xor0: xor@6a0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6a0000 0x1000>,
<0x6b0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clocks = <&cps_syscon0 1 8>;
};
cps_xor1: xor@6c0000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x6c0000 0x1000>,
<0x6d0000 0x1000>;
dma-coherent;
msi-parent = <&gic_v2m0>;
clocks = <&cps_syscon0 1 7>;
};
cps_spi0: spi@700600 {
compatible = "marvell,armada-380-spi";
reg = <0x700600 0x50>;
#address-cells = <0x1>;
#size-cells = <0x0>;
cell-index = <1>;
clocks = <&cps_syscon0 0 3>;
status = "disabled";
};
cps_spi1: spi@700680 {
compatible = "marvell,armada-380-spi";
reg = <0x700680 0x50>;
#address-cells = <1>;
#size-cells = <0>;
cell-index = <2>;
clocks = <&cps_syscon0 1 21>;
status = "disabled";
};
cps_i2c0: i2c@701000 {
compatible = "marvell,mv78230-i2c";
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 21>;
status = "disabled";
};
cps_i2c1: i2c@701100 {
compatible = "marvell,mv78230-i2c";
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 21>;
status = "disabled";
};
};
cps_pcie0: pcie@f4600000 {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 0xf4600000 0 0x10000>,
<0 0xfaf00000 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
/* non-prefetchable memory */
0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cps_syscon0 1 13>;
status = "disabled";
};
cps_pcie1: pcie@f4620000 {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 0xf4620000 0 0x10000>,
<0 0xfbf00000 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
/* non-prefetchable memory */
0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cps_syscon0 1 11>;
status = "disabled";
};
cps_pcie2: pcie@f4640000 {
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
reg = <0 0xf4640000 0 0x10000>,
<0 0xfcf00000 0 0x80000>;
reg-names = "ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
dma-coherent;
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
ranges =
/* downstream I/O */
<0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
/* non-prefetchable memory */
0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cps_syscon0 1 12>;
status = "disabled";
};
};
};

12
arch/arm64/boot/dts/marvell/berlin4ct.dtsi
View file

@ -68,6 +68,7 @@
device_type = "cpu";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
@ -76,6 +77,7 @@
device_type = "cpu";
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
@ -84,6 +86,7 @@
device_type = "cpu";
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
@ -92,9 +95,14 @@
device_type = "cpu";
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
l2: cache {
compatible = "cache";
};
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
@ -115,7 +123,7 @@
};
pmu {
compatible = "arm,armv8-pmuv3";
compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
@ -279,7 +287,6 @@
reg = <0x4000 0x100>;
clocks = <&osc>;
interrupts = <1>;
status = "disabled";
};
wdt2: watchdog@5000 {
@ -287,7 +294,6 @@
reg = <0x5000 0x100>;
clocks = <&osc>;
interrupts = <2>;
status = "disabled";
};
sm_gpio0: gpio@8000 {

38
arch/arm64/boot/dts/mediatek/mt8173-evb.dts
View file

@ -42,6 +42,44 @@
gpio = <&pio 130 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "d";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi0_out>;
};
};
};
};
&cec {
status = "okay";
};
&dpi0 {
status = "okay";
};
&hdmi_phy {
status = "okay";
};
&hdmi0 {
status = "okay";
ports {
port@1 {
reg = <1>;
hdmi0_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
&i2c1 {

77
arch/arm64/boot/dts/mediatek/mt8173.dtsi
View file

@ -254,6 +254,16 @@
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
hdmi_pin: xxx {
/*hdmi htplg pin*/
pins1 {
pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
input-enable;
bias-pull-down;
};
};
i2c0_pins_a: i2c0 {
pins1 {
pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>,
@ -341,6 +351,14 @@
clock-names = "spi", "wrap";
};
cec: cec@10013000 {
compatible = "mediatek,mt8173-cec";
reg = <0 0x10013000 0 0xbc>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_CEC>;
status = "disabled";
};
vpu: vpu@10020000 {
compatible = "mediatek,mt8173-vpu";
reg = <0 0x10020000 0 0x30000>,
@ -383,6 +401,19 @@
#clock-cells = <1>;
};
hdmi_phy: hdmi-phy@10209100 {
compatible = "mediatek,mt8173-hdmi-phy";
reg = <0 0x10209100 0 0x24>;
clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
clock-names = "pll_ref";
clock-output-names = "hdmitx_dig_cts";
mediatek,ibias = <0xa>;
mediatek,ibias_up = <0x1c>;
#clock-cells = <0>;
#phy-cells = <0>;
status = "disabled";
};
mipi_tx0: mipi-dphy@10215000 {
compatible = "mediatek,mt8173-mipi-tx";
reg = <0 0x10215000 0 0x1000>;
@ -577,6 +608,14 @@
status = "disabled";
};
hdmiddc0: i2c@11012000 {
compatible = "mediatek,mt8173-hdmi-ddc";
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
reg = <0 0x11012000 0 0x1C>;
clocks = <&pericfg CLK_PERI_I2C5>;
clock-names = "ddc-i2c";
};
i2c6: i2c@11013000 {
compatible = "mediatek,mt8173-i2c";
reg = <0 0x11013000 0 0x70>,
@ -885,6 +924,12 @@
<&apmixedsys CLK_APMIXED_TVDPLL>;
clock-names = "pixel", "engine", "pll";
status = "disabled";
port {
dpi0_out: endpoint {
remote-endpoint = <&hdmi0_in>;
};
};
};
pwm0: pwm@1401e000 {
@ -942,6 +987,38 @@
clocks = <&mmsys CLK_MM_DISP_OD>;
};
hdmi0: hdmi@14025000 {
compatible = "mediatek,mt8173-hdmi";
reg = <0 0x14025000 0 0x400>;
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
<&mmsys CLK_MM_HDMI_PLLCK>,
<&mmsys CLK_MM_HDMI_AUDIO>,
<&mmsys CLK_MM_HDMI_SPDIF>;
clock-names = "pixel", "pll", "bclk", "spdif";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pin>;
phys = <&hdmi_phy>;
phy-names = "hdmi";
mediatek,syscon-hdmi = <&mmsys 0x900>;
assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
assigned-clock-parents = <&hdmi_phy>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi0_in: endpoint {
remote-endpoint = <&dpi0_out>;
};
};
};
};
larb4: larb@14027000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0 0x14027000 0 0x1000>;

120
arch/arm64/boot/dts/nvidia/tegra210-smaug.dts
View file

@ -27,6 +27,12 @@
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
host1x@50000000 {
dpaux: dpaux@545c0000 {
status = "okay";
};
};
pinmux: pinmux@700008d4 {
pinctrl-names = "boot";
pinctrl-0 = <&state_boot>;
@ -1556,6 +1562,46 @@
};
};
i2c@7000d100 {
status = "okay";
clock-frequency = <400000>;
nau8825@1a {
compatible = "nuvoton,nau8825";
reg = <0x1a>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(E, 6) IRQ_TYPE_LEVEL_LOW>;
clocks = <&tegra_car TEGRA210_CLK_CLK_OUT_2>;
clock-names = "mclk";
nuvoton,jkdet-enable;
nuvoton,jkdet-polarity = <GPIO_ACTIVE_LOW>;
nuvoton,vref-impedance = <2>;
nuvoton,micbias-voltage = <6>;
nuvoton,sar-threshold-num = <4>;
nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>;
nuvoton,sar-hysteresis = <1>;
nuvoton,sar-voltage = <0>;
nuvoton,sar-compare-time = <0>;
nuvoton,sar-sampling-time = <0>;
nuvoton,short-key-debounce = <2>;
nuvoton,jack-insert-debounce = <7>;
nuvoton,jack-eject-debounce = <7>;
status = "okay";
};
audio-codec@2d {
compatible = "realtek,rt5677";
reg = <0x2d>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(X, 0) IRQ_TYPE_LEVEL_HIGH>;
realtek,reset-gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_LOW>;
gpio-controller;
#gpio-cells = <2>;
status = "okay";
};
};
pmc@7000e400 {
nvidia,invert-interrupt;
nvidia,suspend-mode = <0>;
@ -1568,12 +1614,81 @@
status = "okay";
};
usb@70090000 {
phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
<&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>;
phy-names = "usb2-0", "usb3-0";
dvddio-pex-supply = <&avddio_1v05>;
hvddio-pex-supply = <&pp1800>;
avdd-usb-supply = <&pp3300>;
avdd-pll-utmip-supply = <&pp1800>;
avdd-pll-uerefe-supply = <&pp1050_avdd>;
dvdd-pex-pll-supply = <&avddio_1v05>;
hvdd-pex-pll-e-supply = <&pp1800>;
status = "okay";
};
padctl@7009f000 {
status = "okay";
pads {
usb2 {
status = "okay";
lanes {
usb2-0 {
nvidia,function = "xusb";
status = "okay";
};
};
};
pcie {
status = "okay";
lanes {
pcie-6 {
nvidia,function = "usb3-ss";
status = "okay";
};
};
};
};
ports {
usb2-0 {
status = "okay";
vbus-supply = <&usbc_vbus>;
mode = "otg";
};
usb3-0 {
nvidia,usb2-companion = <0>;
status = "okay";
};
};
};
sdhci@700b0600 {
bus-width = <8>;
non-removable;
status = "okay";
};
aconnect@702c0000 {
status = "okay";
dma@702e2000 {
status = "okay";
};
agic@702f9000 {
status = "okay";
};
};
clocks {
compatible = "simple-bus";
#address-cells = <1>;
@ -1646,6 +1761,11 @@
};
};
max98357a {
compatible = "maxim,max98357a";
status = "okay";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";

79
arch/arm64/boot/dts/nvidia/tegra210.dtsi
View file

@ -34,6 +34,7 @@
clock-names = "dpaux", "parent";
resets = <&tegra_car 207>;
reset-names = "dpaux";
power-domains = <&pd_sor>;
status = "disabled";
state_dpaux1_aux: pinmux-aux {
@ -108,6 +109,7 @@
clock-names = "dsi", "lp", "parent";
resets = <&tegra_car 48>;
reset-names = "dsi";
power-domains = <&pd_sor>;
nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
status = "disabled";
@ -137,6 +139,7 @@
clock-names = "dsi", "lp", "parent";
resets = <&tegra_car 82>;
reset-names = "dsi";
power-domains = <&pd_sor>;
nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
status = "disabled";
@ -178,6 +181,7 @@
pinctrl-1 = <&state_dpaux_i2c>;
pinctrl-2 = <&state_dpaux_off>;
pinctrl-names = "aux", "i2c", "off";
power-domains = <&pd_sor>;
status = "disabled";
};
@ -197,6 +201,7 @@
pinctrl-1 = <&state_dpaux1_i2c>;
pinctrl-2 = <&state_dpaux1_off>;
pinctrl-names = "aux", "i2c", "off";
power-domains = <&pd_sor>;
status = "disabled";
};
@ -209,6 +214,7 @@
clock-names = "dpaux", "parent";
resets = <&tegra_car 181>;
reset-names = "dpaux";
power-domains = <&pd_sor>;
status = "disabled";
state_dpaux_aux: pinmux-aux {
@ -325,7 +331,7 @@
};
gpio: gpio@6000d000 {
compatible = "nvidia,tegra210-gpio", "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
reg = <0x0 0x6000d000 0x0 0x1000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
@ -648,27 +654,41 @@
#power-domain-cells = <0>;
};
pd_sor: sor {
clocks = <&tegra_car TEGRA210_CLK_SOR0>,
<&tegra_car TEGRA210_CLK_SOR1>,
<&tegra_car TEGRA210_CLK_CSI>,
<&tegra_car TEGRA210_CLK_DSIA>,
<&tegra_car TEGRA210_CLK_DSIB>,
<&tegra_car TEGRA210_CLK_DPAUX>,
<&tegra_car TEGRA210_CLK_DPAUX1>,
<&tegra_car TEGRA210_CLK_MIPI_CAL>;
resets = <&tegra_car TEGRA210_CLK_SOR0>,
<&tegra_car TEGRA210_CLK_SOR1>,
<&tegra_car TEGRA210_CLK_CSI>,
<&tegra_car TEGRA210_CLK_DSIA>,
<&tegra_car TEGRA210_CLK_DSIB>,
<&tegra_car TEGRA210_CLK_DPAUX>,
<&tegra_car TEGRA210_CLK_DPAUX1>,
<&tegra_car TEGRA210_CLK_MIPI_CAL>;
#power-domain-cells = <0>;
};
pd_xusbss: xusba {
clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
clock-names = "xusb-ss";
resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
reset-names = "xusb-ss";
#power-domain-cells = <0>;
};
pd_xusbdev: xusbb {
clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
clock-names = "xusb-dev";
resets = <&tegra_car 95>;
reset-names = "xusb-dev";
#power-domain-cells = <0>;
};
pd_xusbhost: xusbc {
clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
clock-names = "xusb-host";
resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
reset-names = "xusb-host";
#power-domain-cells = <0>;
};
};
@ -948,6 +968,7 @@
reg = <0x0 0x700e3000 0x0 0x100>;
clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
clock-names = "mipi-cal";
power-domains = <&pd_sor>;
#nvidia,mipi-calibrate-cells = <1>;
};
@ -961,6 +982,50 @@
#size-cells = <1>;
ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
status = "disabled";
adma: dma@702e2000 {
compatible = "nvidia,tegra210-adma";
reg = <0x702e2000 0x2000>;
interrupt-parent = <&agic>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
clock-names = "d_audio";
status = "disabled";
};
agic: agic@702f9000 {
compatible = "nvidia,tegra210-agic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x702f9000 0x2000>,
<0x702fa000 0x2000>;
interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&tegra_car TEGRA210_CLK_APE>;
clock-names = "clk";
status = "disabled";
};
};
spi@70410000 {

1
arch/arm64/boot/dts/qcom/Makefile
View file

@ -1,5 +1,6 @@
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)

48
arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
View file

@ -24,4 +24,52 @@
bias-pull-up;
};
};
adv7533_int_active: adv533_int_active {
pinmux {
function = "gpio";
pins = "gpio31";
};
pinconf {
pins = "gpio31";
drive-strength = <16>;
bias-disable;
};
};
adv7533_int_suspend: adv7533_int_suspend {
pinmux {
function = "gpio";
pins = "gpio31";
};
pinconf {
pins = "gpio31";
drive-strength = <2>;
bias-disable;
};
};
adv7533_switch_active: adv7533_switch_active {
pinmux {
function = "gpio";
pins = "gpio32";
};
pinconf {
pins = "gpio32";
drive-strength = <16>;
bias-disable;
};
};
adv7533_switch_suspend: adv7533_switch_suspend {
pinmux {
function = "gpio";
pins = "gpio32";
};
pinconf {
pins = "gpio32";
drive-strength = <2>;
bias-disable;
};
};
};

82
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
View file

@ -63,6 +63,47 @@
/* On High speed expansion */
label = "HS-I2C2";
status = "okay";
adv_bridge: bridge@39 {
status = "okay";
compatible = "adi,adv7533";
reg = <0x39>;
interrupt-parent = <&msmgpio>;
interrupts = <31 2>;
adi,dsi-lanes = <4>;
pd-gpios = <&msmgpio 32 0>;
avdd-supply = <&pm8916_l6>;
v1p2-supply = <&pm8916_l6>;
v3p3-supply = <&pm8916_l17>;
pinctrl-names = "default","sleep";
pinctrl-0 = <&adv7533_int_active &adv7533_switch_active>;
pinctrl-1 = <&adv7533_int_suspend &adv7533_switch_suspend>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7533_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
port@1 {
reg = <1>;
adv7533_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
i2c@78ba000 {
@ -180,6 +221,36 @@
lpass@07708000 {
status = "okay";
};
mdss@1a00000 {
status = "okay";
mdp@1a01000 {
status = "okay";
};
dsi@1a98000 {
status = "okay";
vdda-supply = <&pm8916_l2>;
vddio-supply = <&pm8916_l6>;
ports {
port@1 {
endpoint {
remote-endpoint = <&adv7533_in>;
data-lanes = <0 1 2 3>;
};
};
};
};
dsi-phy@1a98300 {
status = "okay";
vddio-supply = <&pm8916_l6>;
};
};
};
usb2513 {
@ -194,6 +265,17 @@
pinctrl-names = "default";
pinctrl-0 = <&usb_id_default>;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7533_out>;
};
};
};
};
&smd_rpm_regulators {

39
arch/arm64/boot/dts/qcom/apq8096-db820c-pins.dtsi Normal file
View file

@ -0,0 +1,39 @@
/*
* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
&msmgpio {
sdc2_cd_on: sdc2_cd_on {
mux {
pins = "gpio38";
function = "gpio";
};
config {
pins = "gpio38";
bias-pull-up; /* pull up */
drive-strength = <16>; /* 16 MA */
};
};
sdc2_cd_off: sdc2_cd_off {
mux {
pins = "gpio38";
function = "gpio";
};
config {
pins = "gpio38";
bias-pull-up; /* pull up */
drive-strength = <2>; /* 2 MA */
};
};
};

21
arch/arm64/boot/dts/qcom/apq8096-db820c.dts Normal file
View file

@ -0,0 +1,21 @@
/*
* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "apq8096-db820c.dtsi"
/ {
model = "Qualcomm Technologies, Inc. DB820c";
compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
};

88
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi Normal file
View file

@ -0,0 +1,88 @@
/*
* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "msm8996.dtsi"
#include "apq8096-db820c-pins.dtsi"
/ {
aliases {
serial0 = &blsp2_uart1;
serial1 = &blsp2_uart2;
i2c0 = &blsp1_i2c2;
i2c1 = &blsp2_i2c1;
i2c2 = &blsp2_i2c0;
spi0 = &blsp1_spi0;
spi1 = &blsp2_spi5;
};
chosen {
stdout-path = "serial0:115200n8";
};
soc {
serial@75b0000 {
label = "LS-UART1";
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_uart1_2pins_default>;
pinctrl-1 = <&blsp2_uart1_2pins_sleep>;
};
serial@75b1000 {
label = "LS-UART0";
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_uart2_4pins_default>;
pinctrl-1 = <&blsp2_uart2_4pins_sleep>;
};
i2c@07577000 {
/* On Low speed expansion */
label = "LS-I2C0";
status = "okay";
};
i2c@075b6000 {
/* On Low speed expansion */
label = "LS-I2C1";
status = "okay";
};
spi@07575000 {
/* On Low speed expansion */
label = "LS-SPI0";
status = "okay";
};
i2c@075b5000 {
/* On High speed expansion */
label = "HS-I2C2";
status = "okay";
};
spi@075ba000{
/* On High speed expansion */
label = "HS-SPI1";
status = "okay";
};
sdhci@74a4900 {
/* External SD card */
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
cd-gpios = <&msmgpio 38 0x1>;
status = "okay";
};
};
};

286
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file

@ -86,6 +86,11 @@
reg = <0x0 0x89300000 0x0 0x600000>;
no-map;
};
mba_mem: mba@8ea00000 {
no-map;
reg = <0 0x8ea00000 0 0x100000>;
};
};
cpus {
@ -155,6 +160,49 @@
interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
};
thermal-zones {
cpu-thermal0 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 4>;
trips {
cpu_alert0: trip0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit0: trip1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpu-thermal1 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens 3>;
trips {
cpu_alert1: trip0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit1: trip1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@ -187,10 +235,11 @@
};
firmware {
scm {
scm: scm {
compatible = "qcom,scm";
clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "core", "bus", "iface";
#reset-cells = <1>;
};
};
@ -228,6 +277,11 @@
reg = <0x1905000 0x20000>;
};
tcsr: syscon@1937000 {
compatible = "qcom,tcsr-msm8916", "syscon";
reg = <0x1937000 0x30000>;
};
tcsr_mutex: hwlock {
compatible = "qcom,tcsr-mutex";
syscon = <&tcsr_mutex_regs 0 0x1000>;
@ -483,7 +537,7 @@
compatible = "qcom,ci-hdrc";
reg = <0x78d9000 0x400>;
dr_mode = "peripheral";
interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&usb_otg>;
status = "disabled";
};
@ -491,7 +545,7 @@
usb_host: ehci@78d9000 {
compatible = "qcom,ehci-host";
reg = <0x78d9000 0x400>;
interrupts = <GIC_SPI 134 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
usb-phy = <&usb_otg>;
status = "disabled";
};
@ -499,8 +553,8 @@
usb_otg: phy@78d9000 {
compatible = "qcom,usb-otg-snps";
reg = <0x78d9000 0x400>;
interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_BOTH>,
<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
qcom,vdd-levels = <500000 1000000 1320000>;
qcom,phy-init-sequence = <0x44 0x6B 0x24 0x13>;
@ -594,7 +648,7 @@
<0x200a000 0x002100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;
@ -609,6 +663,144 @@
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
qfprom: qfprom@5c000 {
compatible = "qcom,qfprom";
reg = <0x5c000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
tsens_caldata: caldata@d0 {
reg = <0xd0 0x8>;
};
tsens_calsel: calsel@ec {
reg = <0xec 0x4>;
};
};
tsens: thermal-sensor@4a8000 {
compatible = "qcom,msm8916-tsens";
reg = <0x4a8000 0x2000>;
nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
nvmem-cell-names = "calib", "calib_sel";
#thermal-sensor-cells = <1>;
};
mdss: mdss@1a00000 {
compatible = "qcom,mdss";
reg = <0x1a00000 0x1000>,
<0x1ac8000 0x3000>;
reg-names = "mdss_phys", "vbif_phys";
power-domains = <&gcc MDSS_GDSC>;
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>;
clock-names = "iface_clk",
"bus_clk",
"vsync_clk";
interrupts = <0 72 0>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
mdp: mdp@1a01000 {
compatible = "qcom,mdp5";
reg = <0x1a01000 0x90000>;
reg-names = "mdp_phys";
interrupt-parent = <&mdss>;
interrupts = <0 0>;
clocks = <&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_VSYNC_CLK>;
clock-names = "iface_clk",
"bus_clk",
"core_clk",
"vsync_clk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdp5_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
};
};
dsi0: dsi@1a98000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0x1a98000 0x25c>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4 0>;
assigned-clocks = <&gcc BYTE0_CLK_SRC>,
<&gcc PCLK0_CLK_SRC>;
assigned-clock-parents = <&dsi_phy0 0>,
<&dsi_phy0 1>;
clocks = <&gcc GCC_MDSS_MDP_CLK>,
<&gcc GCC_MDSS_AHB_CLK>,
<&gcc GCC_MDSS_AXI_CLK>,
<&gcc GCC_MDSS_BYTE0_CLK>,
<&gcc GCC_MDSS_PCLK0_CLK>,
<&gcc GCC_MDSS_ESC0_CLK>;
clock-names = "mdp_core_clk",
"iface_clk",
"bus_clk",
"byte_clk",
"pixel_clk",
"core_clk";
phys = <&dsi_phy0>;
phy-names = "dsi-phy";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&mdp5_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
};
};
};
};
dsi_phy0: dsi-phy@1a98300 {
compatible = "qcom,dsi-phy-28nm-lp";
reg = <0x1a98300 0xd4>,
<0x1a98500 0x280>,
<0x1a98780 0x30>;
reg-names = "dsi_pll",
"dsi_phy",
"dsi_phy_regulator";
#clock-cells = <1>;
clocks = <&gcc GCC_MDSS_AHB_CLK>;
clock-names = "iface_clk";
};
};
};
smd {
@ -657,6 +849,88 @@
};
};
};
hexagon-smp2p {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 14>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
hexagon_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
hexagon_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
wcnss-smp2p {
compatible = "qcom,smp2p";
qcom,smem = <451>, <431>;
interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
qcom,ipc = <&apcs 8 18>;
qcom,local-pid = <0>;
qcom,remote-pid = <4>;
wcnss_smp2p_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
wcnss_smp2p_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smsm {
compatible = "qcom,smsm";
#address-cells = <1>;
#size-cells = <0>;
qcom,ipc-1 = <&apcs 0 13>;
qcom,ipc-6 = <&apcs 0 19>;
apps_smsm: apps@0 {
reg = <0>;
#qcom,smem-state-cells = <1>;
};
hexagon_smsm: hexagon@1 {
reg = <1>;
interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
};
wcnss_smsm: wcnss@6 {
reg = <6>;
interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};
#include "msm8916-pins.dtsi"

94
arch/arm64/boot/dts/qcom/msm8996.dtsi
View file

@ -97,6 +97,92 @@
};
};
thermal-zones {
cpu-thermal0 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 3>;
trips {
cpu_alert0: trip0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit0: trip1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpu-thermal1 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 5>;
trips {
cpu_alert1: trip0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit1: trip1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpu-thermal2 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 8>;
trips {
cpu_alert2: trip0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit2: trip1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
cpu-thermal3 {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsens0 10>;
trips {
cpu_alert3: trip0 {
temperature = <75000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit3: trip1 {
temperature = <110000>;
hysteresis = <2000>;
type = "critical";
};
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@ -181,6 +267,12 @@
status = "disabled";
};
tsens0: thermal-sensor@4a8000 {
compatible = "qcom,msm8996-tsens";
reg = <0x4a8000 0x2000>;
#thermal-sensor-cells = <1>;
};
blsp2_uart1: serial@75b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x75b0000 0x1000>;
@ -339,7 +431,7 @@
<0x400a000 0x002100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>;
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <2>;

1
arch/arm64/boot/dts/rockchip/Makefile
View file

@ -1,5 +1,6 @@
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb

382
arch/arm64/boot/dts/rockchip/rk3368-orion-r68-meta.dts Normal file
View file

@ -0,0 +1,382 @@
/*
* Copyright (c) 2016 Matthias Brugger <mbrugger@suse.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3368.dtsi"
/ {
model = "Rockchip Orion R68";
compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368";
chosen {
stdout-path = "serial2:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
pinctrl-0 = <&emmc_reset>;
pinctrl-names = "default";
reset-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
};
ext_gmac: external-gmac-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
clock-output-names = "ext_gmac";
};
keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pwr_key>;
power {
wakeup-source;
gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
label = "GPIO Power";
linux,code = <KEY_POWER>;
};
};
leds: gpio-leds {
compatible = "gpio-leds";
red {
gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
label = "orion:red:led";
pinctrl-names = "default";
pinctrl-0 = <&led_ctl>;
default-state = "on";
};
blue {
gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
label = "orion:blue:led";
pinctrl-names = "default";
pinctrl-0 = <&stby_pwren>;
default-state = "off";
};
};
vcc_18: vcc18-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
/* supplies both host and otg */
vcc_host: vcc-host-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 4 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&host_vbus_drv>;
regulator-name = "vcc_host";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
vcc_io: vcc-io-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_io";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
vcc_lan: vcc-lan-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_lan";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_io>;
};
vcc_sd: vcc-sd-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sd";
gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_io>;
};
vcc_sys: vcc-sys-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vccio_sd: vcc-io-sd-regulator {
compatible = "regulator-fixed";
regulator-name= "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_io>;
};
vccio_wl: vccio-wl-regulator {
compatible = "regulator-fixed";
regulator-name = "vccio_wl";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_io>;
};
vdd_10: vdd-10-regulator {
compatible = "regulator-fixed";
regulator-name = "vdd_10";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
};
&emmc {
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
keep-power-in-suspend;
mmc-pwrseq = <&emmc_pwrseq>;
mmc-hs200-1_2v;
mmc-hs200-1_8v;
non-removable;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_MAC>;
assigned-clock-parents = <&ext_gmac>;
clock_in_out = "input";
phy-supply = <&vcc_lan>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 12 0>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 1000000>;
tx_delay = <0x30>;
rx_delay = <0x10>;
status = "ok";
};
&i2c0 {
status = "okay";
vdd_cpu: syr827@40 {
compatible = "silergy,syr827";
reg = <0x40>;
fcs,suspend-voltage-selector = <1>;
regulator-name = "vdd_cpu";
regulator-enable-ramp-delay = <300>;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1500000>;
regulator-ramp-delay = <8000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
hym8563: hym8563@51 {
compatible = "haoyu,hym8563";
reg = <0x51>;
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "xin32k";
/* rtc_int is not connected */
};
};
&pinctrl {
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
bias-disable;
drive-strength = <8>;
};
pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
bias-pull-up;
drive-strength = <8>;
};
emmc {
emmc_bus8: emmc-bus8 {
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<1 19 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<1 20 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<1 21 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<1 22 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<1 23 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<1 24 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,
<1 25 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
};
emmc-clk {
rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
};
emmc-cmd {
rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
};
emmc_reset: emmc-reset {
rockchip,pins = <2 3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
keys {
pwr_key: pwr-key {
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
leds {
stby_pwren: stby-pwren {
rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>;
};
led_ctl: led-ctl {
rockchip,pins = <3 29 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
};
sdmmc_cmd: sdmmc-cmd {
rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
};
sdmmc_cd: sdmmc-cd {
rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
};
sdmmc_bus1: sdmmc-bus1 {
rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
};
sdmmc_bus4: sdmmc-bus4 {
rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
<2 6 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
<2 7 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
<2 8 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
};
};
usb {
host_vbus_drv: host-vbus-drv {
rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&saradc {
vref-supply = <&vcc_18>;
status = "okay";
};
&sdmmc {
bus-width = <4>;
clock-frequency = <50000000>;
clock-freq-min-max = <400000 50000000>;
cap-sd-highspeed;
card-detect-delay = <200>;
keep-power-in-suspend;
num-slots = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
vmmc-supply = <&vcc_sd>;
vqmmc-supply = <&vccio_sd>;
status = "okay";
};
&uart2 {
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&uart4_xfer>;
status = "okay";
};
&usb_host0_ehci {
status = "okay";
};
&usb_otg {
status = "okay";
};
&wdt {
status = "okay";
};

1
arch/arm64/boot/dts/rockchip/rk3368-r88.dts
View file

@ -248,7 +248,6 @@
&sdio0 {
assigned-clocks = <&cru SCLK_SDIO0>;
assigned-clock-parents = <&cru PLL_CPLL>;
broken-cd;
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;

10
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View file

@ -45,6 +45,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,boot-mode.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@ -641,6 +642,15 @@
compatible = "rockchip,rk3368-pmu-io-voltage-domain";
status = "disabled";
};
reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x200>;
mode-normal = <BOOT_NORMAL>;
mode-recovery = <BOOT_RECOVERY>;
mode-bootloader = <BOOT_FASTBOOT>;
mode-loader = <BOOT_BL_DOWNLOAD>;
};
};
cru: clock-controller@ff760000 {

87
arch/arm64/boot/dts/rockchip/rk3399-evb.dts
View file

@ -49,6 +49,13 @@
compatible = "rockchip,rk3399-evb", "rockchip,rk3399",
"google,rk3399evb-rev2";
clkin_gmac: external-gmac-clock {
compatible = "fixed-clock";
clock-frequency = <125000000>;
clock-output-names = "clkin_gmac";
#clock-cells = <0>;
};
vdd_center: vdd-center {
compatible = "pwm-regulator";
pwms = <&pwm3 0 25000 0>;
@ -69,18 +76,61 @@
regulator-max-microvolt = <3300000>;
};
vcc5v0_sys: vcc5v0-sys {
compatible = "regulator-fixed";
regulator-name = "vcc5v0_sys";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vcc5v0_host_en>;
regulator-name = "vcc5v0_host";
vin-supply = <&vcc5v0_sys>;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
vcc_phy: vcc-phy-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_phy";
regulator-always-on;
regulator-boot-on;
};
};
&emmc_phy {
status = "okay";
};
&gmac {
assigned-clocks = <&cru SCLK_RMII_SRC>;
assigned-clock-parents = <&clkin_gmac>;
clock_in_out = "input";
phy-supply = <&vcc_phy>;
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&rgmii_pins>;
snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
snps,reset-delays-us = <0 10000 50000>;
tx_delay = <0x28>;
rx_delay = <0x11>;
status = "okay";
};
&pwm0 {
status = "okay";
};
@ -101,6 +151,36 @@
status = "okay";
};
&pcie_phy {
status = "disabled";
};
&pcie0 {
ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
num-lanes = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_clkreqn>;
status = "disabled";
};
&u2phy0 {
status = "okay";
};
&u2phy0_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&u2phy1 {
status = "okay";
};
&u2phy1_host {
phy-supply = <&vcc5v0_host>;
status = "okay";
};
&uart2 {
status = "okay";
};
@ -133,4 +213,11 @@
<1 18 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
usb2 {
vcc5v0_host_en: vcc5v0-host-en {
rockchip,pins =
<4 25 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};

607
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View file

@ -45,6 +45,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/power/rk3399-power.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@ -152,6 +153,16 @@
};
};
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
};
pmu_a72 {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
@ -159,10 +170,10 @@
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
};
xin24m: xin24m {
@ -181,8 +192,8 @@
dmac_bus: dma-controller@ff6d0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff6d0000 0x0 0x4000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC0_PERILP>;
clock-names = "apb_pclk";
@ -191,19 +202,39 @@
dmac_peri: dma-controller@ff6e0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0xff6e0000 0x0 0x4000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
#dma-cells = <1>;
clocks = <&cru ACLK_DMAC1_PERILP>;
clock-names = "apb_pclk";
};
};
gmac: ethernet@fe300000 {
compatible = "rockchip,rk3399-gmac";
reg = <0x0 0xfe300000 0x0 0x10000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "macirq";
clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
<&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
<&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
<&cru PCLK_GMAC>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_ref",
"clk_mac_refout", "aclk_mac",
"pclk_mac";
power-domains = <&power RK3399_PD_GMAC>;
resets = <&cru SRST_A_GMAC>;
reset-names = "stmmaceth";
rockchip,grf = <&grf>;
status = "disabled";
};
sdio0: dwmmc@fe310000 {
compatible = "rockchip,rk3399-dw-mshc",
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe310000 0x0 0x4000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
@ -216,7 +247,7 @@
compatible = "rockchip,rk3399-dw-mshc",
"rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe320000 0x0 0x4000>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
clock-freq-min-max = <400000 150000000>;
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
@ -228,7 +259,7 @@
sdhci: sdhci@fe330000 {
compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
reg = <0x0 0xfe330000 0x0 0x10000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
arasan,soc-ctl-syscon = <&grf>;
assigned-clocks = <&cru SCLK_EMMC>;
assigned-clock-rates = <200000000>;
@ -241,19 +272,60 @@
status = "disabled";
};
pcie0: pcie@f8000000 {
compatible = "rockchip,rk3399-pcie";
reg = <0x0 0xf8000000 0x0 0x2000000>,
<0x0 0xfd000000 0x0 0x1000000>;
reg-names = "axi-base", "apb-base";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
bus-range = <0x0 0x1>;
clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
clock-names = "aclk", "aclk-perf",
"hclk", "pm";
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "sys", "legacy", "client";
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
<0 0 0 2 &pcie0_intc 1>,
<0 0 0 3 &pcie0_intc 2>,
<0 0 0 4 &pcie0_intc 3>;
msi-map = <0x0 &its 0x0 0x1000>;
phys = <&pcie_phy>;
phy-names = "pcie-phy";
ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
<&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
status = "disabled";
pcie0_intc: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
usb_host0_ehci: usb@fe380000 {
compatible = "generic-ehci";
reg = <0x0 0xfe380000 0x0 0x20000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
clock-names = "hclk_host0", "hclk_host0_arb";
phys = <&u2phy0_host>;
phy-names = "usb";
status = "disabled";
};
usb_host0_ohci: usb@fe3a0000 {
compatible = "generic-ohci";
reg = <0x0 0xfe3a0000 0x0 0x20000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
clock-names = "hclk_host0", "hclk_host0_arb";
status = "disabled";
@ -262,16 +334,18 @@
usb_host1_ehci: usb@fe3c0000 {
compatible = "generic-ehci";
reg = <0x0 0xfe3c0000 0x0 0x20000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
clock-names = "hclk_host1", "hclk_host1_arb";
phys = <&u2phy1_host>;
phy-names = "usb";
status = "disabled";
};
usb_host1_ohci: usb@fe3e0000 {
compatible = "generic-ohci";
reg = <0x0 0xfe3e0000 0x0 0x20000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
clock-names = "hclk_host1", "hclk_host1_arb";
status = "disabled";
@ -279,7 +353,7 @@
gic: interrupt-controller@fee00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@ -290,12 +364,34 @@
<0x0 0xfff00000 0 0x10000>, /* GICC */
<0x0 0xfff10000 0 0x10000>, /* GICH */
<0x0 0xfff20000 0 0x10000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
its: interrupt-controller@fee20000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0xfee20000 0x0 0x20000>;
};
ppi-partitions {
ppi_cluster0: interrupt-partition-0 {
affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
};
ppi_cluster1: interrupt-partition-1 {
affinity = <&cpu_b0 &cpu_b1>;
};
};
};
saradc: saradc@ff100000 {
compatible = "rockchip,rk3399-saradc";
reg = <0x0 0xff100000 0x0 0x100>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
#io-channel-cells = <1>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
resets = <&cru SRST_P_SARADC>;
reset-names = "saradc-apb";
status = "disabled";
};
i2c1: i2c@ff110000 {
@ -305,7 +401,7 @@
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
#address-cells = <1>;
@ -320,7 +416,7 @@
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_xfer>;
#address-cells = <1>;
@ -335,7 +431,7 @@
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c3_xfer>;
#address-cells = <1>;
@ -350,7 +446,7 @@
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c5_xfer>;
#address-cells = <1>;
@ -365,7 +461,7 @@
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c6_xfer>;
#address-cells = <1>;
@ -380,7 +476,7 @@
assigned-clock-rates = <200000000>;
clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c7_xfer>;
#address-cells = <1>;
@ -393,7 +489,7 @@
reg = <0x0 0xff180000 0x0 0x100>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@ -406,7 +502,7 @@
reg = <0x0 0xff190000 0x0 0x100>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@ -419,7 +515,7 @@
reg = <0x0 0xff1a0000 0x0 0x100>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@ -432,7 +528,7 @@
reg = <0x0 0xff1b0000 0x0 0x100>;
clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@ -445,7 +541,7 @@
reg = <0x0 0xff1c0000 0x0 0x1000>;
clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
#address-cells = <1>;
@ -458,7 +554,7 @@
reg = <0x0 0xff1d0000 0x0 0x1000>;
clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
#address-cells = <1>;
@ -471,7 +567,7 @@
reg = <0x0 0xff1e0000 0x0 0x1000>;
clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
#address-cells = <1>;
@ -484,7 +580,7 @@
reg = <0x0 0xff1f0000 0x0 0x1000>;
clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
#address-cells = <1>;
@ -497,7 +593,7 @@
reg = <0x0 0xff200000 0x0 0x1000>;
clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
#address-cells = <1>;
@ -577,7 +673,7 @@
tsadc: tsadc@ff260000 {
compatible = "rockchip,rk3399-tsadc";
reg = <0x0 0xff260000 0x0 0x100>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
assigned-clocks = <&cru SCLK_TSADC>;
assigned-clock-rates = <750000>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
@ -594,6 +690,203 @@
status = "disabled";
};
qos_gmac: qos@ffa5c000 {
compatible = "syscon";
reg = <0x0 0xffa5c000 0x0 0x20>;
};
qos_hdcp: qos@ffa90000 {
compatible = "syscon";
reg = <0x0 0xffa90000 0x0 0x20>;
};
qos_iep: qos@ffa98000 {
compatible = "syscon";
reg = <0x0 0xffa98000 0x0 0x20>;
};
qos_isp0_m0: qos@ffaa0000 {
compatible = "syscon";
reg = <0x0 0xffaa0000 0x0 0x20>;
};
qos_isp0_m1: qos@ffaa0080 {
compatible = "syscon";
reg = <0x0 0xffaa0080 0x0 0x20>;
};
qos_isp1_m0: qos@ffaa8000 {
compatible = "syscon";
reg = <0x0 0xffaa8000 0x0 0x20>;
};
qos_isp1_m1: qos@ffaa8080 {
compatible = "syscon";
reg = <0x0 0xffaa8080 0x0 0x20>;
};
qos_rga_r: qos@ffab0000 {
compatible = "syscon";
reg = <0x0 0xffab0000 0x0 0x20>;
};
qos_rga_w: qos@ffab0080 {
compatible = "syscon";
reg = <0x0 0xffab0080 0x0 0x20>;
};
qos_video_m0: qos@ffab8000 {
compatible = "syscon";
reg = <0x0 0xffab8000 0x0 0x20>;
};
qos_video_m1_r: qos@ffac0000 {
compatible = "syscon";
reg = <0x0 0xffac0000 0x0 0x20>;
};
qos_video_m1_w: qos@ffac0080 {
compatible = "syscon";
reg = <0x0 0xffac0080 0x0 0x20>;
};
qos_vop_big_r: qos@ffac8000 {
compatible = "syscon";
reg = <0x0 0xffac8000 0x0 0x20>;
};
qos_vop_big_w: qos@ffac8080 {
compatible = "syscon";
reg = <0x0 0xffac8080 0x0 0x20>;
};
qos_vop_little: qos@ffad0000 {
compatible = "syscon";
reg = <0x0 0xffad0000 0x0 0x20>;
};
qos_gpu: qos@ffae0000 {
compatible = "syscon";
reg = <0x0 0xffae0000 0x0 0x20>;
};
pmu: power-management@ff310000 {
compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
reg = <0x0 0xff310000 0x0 0x1000>;
/*
* Note: RK3399 supports 6 voltage domains including VD_CORE_L,
* VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
* Some of the power domains are grouped together for every
* voltage domain.
* The detail contents as below.
*/
power: power-controller {
compatible = "rockchip,rk3399-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* These power domains are grouped by VD_CENTER */
pd_iep@RK3399_PD_IEP {
reg = <RK3399_PD_IEP>;
clocks = <&cru ACLK_IEP>,
<&cru HCLK_IEP>;
pm_qos = <&qos_iep>;
};
pd_rga@RK3399_PD_RGA {
reg = <RK3399_PD_RGA>;
clocks = <&cru ACLK_RGA>,
<&cru HCLK_RGA>;
pm_qos = <&qos_rga_r>,
<&qos_rga_w>;
};
pd_vcodec@RK3399_PD_VCODEC {
reg = <RK3399_PD_VCODEC>;
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
pm_qos = <&qos_video_m0>;
};
pd_vdu@RK3399_PD_VDU {
reg = <RK3399_PD_VDU>;
clocks = <&cru ACLK_VDU>,
<&cru HCLK_VDU>;
pm_qos = <&qos_video_m1_r>,
<&qos_video_m1_w>;
};
/* These power domains are grouped by VD_GPU */
pd_gpu@RK3399_PD_GPU {
reg = <RK3399_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
};
/* These power domains are grouped by VD_LOGIC */
pd_gmac@RK3399_PD_GMAC {
reg = <RK3399_PD_GMAC>;
clocks = <&cru ACLK_GMAC>;
pm_qos = <&qos_gmac>;
};
pd_vio@RK3399_PD_VIO {
reg = <RK3399_PD_VIO>;
#address-cells = <1>;
#size-cells = <0>;
pd_hdcp@RK3399_PD_HDCP {
reg = <RK3399_PD_HDCP>;
clocks = <&cru ACLK_HDCP>,
<&cru HCLK_HDCP>,
<&cru PCLK_HDCP>;
pm_qos = <&qos_hdcp>;
};
pd_isp0@RK3399_PD_ISP0 {
reg = <RK3399_PD_ISP0>;
clocks = <&cru ACLK_ISP0>,
<&cru HCLK_ISP0>;
pm_qos = <&qos_isp0_m0>,
<&qos_isp0_m1>;
};
pd_isp1@RK3399_PD_ISP1 {
reg = <RK3399_PD_ISP1>;
clocks = <&cru ACLK_ISP1>,
<&cru HCLK_ISP1>;
pm_qos = <&qos_isp1_m0>,
<&qos_isp1_m1>;
};
pd_tcpc0@RK3399_PD_TCPC0 {
reg = <RK3399_PD_TCPD0>;
clocks = <&cru SCLK_UPHY0_TCPDCORE>,
<&cru SCLK_UPHY0_TCPDPHY_REF>;
};
pd_tcpc1@RK3399_PD_TCPC1 {
reg = <RK3399_PD_TCPD1>;
clocks = <&cru SCLK_UPHY1_TCPDCORE>,
<&cru SCLK_UPHY1_TCPDPHY_REF>;
};
pd_vo@RK3399_PD_VO {
reg = <RK3399_PD_VO>;
#address-cells = <1>;
#size-cells = <0>;
pd_vopb@RK3399_PD_VOPB {
reg = <RK3399_PD_VOPB>;
clocks = <&cru ACLK_VOP0>,
<&cru HCLK_VOP0>;
pm_qos = <&qos_vop_big_r>,
<&qos_vop_big_w>;
};
pd_vopl@RK3399_PD_VOPL {
reg = <RK3399_PD_VOPL>;
clocks = <&cru ACLK_VOP1>,
<&cru HCLK_VOP1>;
pm_qos = <&qos_vop_little>;
};
};
};
};
};
pmugrf: syscon@ff320000 {
compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xff320000 0x0 0x1000>;
@ -611,7 +904,7 @@
reg = <0x0 0xff350000 0x0 0x1000>;
clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
clock-names = "spiclk", "apb_pclk";
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
#address-cells = <1>;
@ -624,7 +917,7 @@
reg = <0x0 0xff370000 0x0 0x100>;
clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
clock-names = "baudclk", "apb_pclk";
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
reg-shift = <2>;
reg-io-width = <4>;
pinctrl-names = "default";
@ -639,7 +932,7 @@
assigned-clock-rates = <200000000>;
clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
#address-cells = <1>;
@ -654,7 +947,7 @@
assigned-clock-rates = <200000000>;
clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c4_xfer>;
#address-cells = <1>;
@ -669,7 +962,7 @@
assigned-clock-rates = <200000000>;
clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
clock-names = "i2c", "pclk";
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c8_xfer>;
#address-cells = <1>;
@ -721,6 +1014,35 @@
status = "disabled";
};
efuse0: efuse@ff690000 {
compatible = "rockchip,rk3399-efuse";
reg = <0x0 0xff690000 0x0 0x80>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&cru PCLK_EFUSE1024NS>;
clock-names = "pclk_efuse";
/* Data cells */
cpub_leakage: cpu-leakage@17 {
reg = <0x17 0x1>;
};
gpu_leakage: gpu-leakage@18 {
reg = <0x18 0x1>;
};
center_leakage: center-leakage@19 {
reg = <0x19 0x1>;
};
cpul_leakage: cpu-leakage@1a {
reg = <0x1a 0x1>;
};
logic_leakage: logic-leakage@1b {
reg = <0x1b 0x1>;
};
wafer_info: wafer-info@1c {
reg = <0x1c 0x1>;
};
};
pmucru: pmu-clock-controller@ff750000 {
compatible = "rockchip,rk3399-pmucru";
reg = <0x0 0xff750000 0x0 0x1000>;
@ -741,7 +1063,7 @@
<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
<&cru PCLK_PERIHP>,
<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
<&cru PCLK_PERILP0>,
<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
assigned-clock-rates =
<594000000>, <800000000>,
@ -749,7 +1071,7 @@
<150000000>, <75000000>,
<37500000>,
<100000000>, <100000000>,
<50000000>,
<50000000>, <600000000>,
<100000000>, <50000000>;
};
@ -764,6 +1086,40 @@
status = "disabled";
};
u2phy0: usb2-phy@e450 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe450 0x10>;
clocks = <&cru SCLK_USB2PHY0_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
clock-output-names = "clk_usbphy0_480m";
status = "disabled";
u2phy0_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "linestate";
status = "disabled";
};
};
u2phy1: usb2-phy@e460 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe460 0x10>;
clocks = <&cru SCLK_USB2PHY1_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
clock-output-names = "clk_usbphy1_480m";
status = "disabled";
u2phy1_host: host-port {
#phy-cells = <0>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "linestate";
status = "disabled";
};
};
emmc_phy: phy@f780 {
compatible = "rockchip,rk3399-emmc-phy";
reg = <0xf780 0x24>;
@ -772,19 +1128,85 @@
#phy-cells = <0>;
status = "disabled";
};
pcie_phy: pcie-phy {
compatible = "rockchip,rk3399-pcie-phy";
clocks = <&cru SCLK_PCIEPHY_REF>;
clock-names = "refclk";
#phy-cells = <0>;
resets = <&cru SRST_PCIEPHY>;
reset-names = "phy";
status = "disabled";
};
};
watchdog@ff840000 {
tcphy0: phy@ff7c0000 {
compatible = "rockchip,rk3399-typec-phy";
reg = <0x0 0xff7c0000 0x0 0x40000>;
clocks = <&cru SCLK_UPHY0_TCPDCORE>,
<&cru SCLK_UPHY0_TCPDPHY_REF>;
clock-names = "tcpdcore", "tcpdphy-ref";
assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
assigned-clock-rates = <50000000>;
resets = <&cru SRST_UPHY0>,
<&cru SRST_UPHY0_PIPE_L00>,
<&cru SRST_P_UPHY0_TCPHY>;
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
rockchip,grf = <&grf>;
rockchip,typec-conn-dir = <0xe580 0 16>;
rockchip,usb3tousb2-en = <0xe580 3 19>;
rockchip,external-psm = <0xe588 14 30>;
rockchip,pipe-status = <0xe5c0 0 0>;
status = "disabled";
tcphy0_dp: dp-port {
#phy-cells = <0>;
};
tcphy0_usb3: usb3-port {
#phy-cells = <0>;
};
};
tcphy1: phy@ff800000 {
compatible = "rockchip,rk3399-typec-phy";
reg = <0x0 0xff800000 0x0 0x40000>;
clocks = <&cru SCLK_UPHY1_TCPDCORE>,
<&cru SCLK_UPHY1_TCPDPHY_REF>;
clock-names = "tcpdcore", "tcpdphy-ref";
assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
assigned-clock-rates = <50000000>;
resets = <&cru SRST_UPHY1>,
<&cru SRST_UPHY1_PIPE_L00>,
<&cru SRST_P_UPHY1_TCPHY>;
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
rockchip,grf = <&grf>;
rockchip,typec-conn-dir = <0xe58c 0 16>;
rockchip,usb3tousb2-en = <0xe58c 3 19>;
rockchip,external-psm = <0xe594 14 30>;
rockchip,pipe-status = <0xe5c0 16 16>;
status = "disabled";
tcphy1_dp: dp-port {
#phy-cells = <0>;
};
tcphy1_usb3: usb3-port {
#phy-cells = <0>;
};
};
watchdog@ff848000 {
compatible = "snps,dw-wdt";
reg = <0x0 0xff840000 0x0 0x100>;
reg = <0x0 0xff848000 0x0 0x100>;
clocks = <&cru PCLK_WDT>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
};
rktimer: rktimer@ff850000 {
compatible = "rockchip,rk3399-timer";
reg = <0x0 0xff850000 0x0 0x1000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
clock-names = "pclk", "timer";
};
@ -792,7 +1214,7 @@
spdif: spdif@ff870000 {
compatible = "rockchip,rk3399-spdif";
reg = <0x0 0xff870000 0x0 0x1000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dmac_bus 7>;
dma-names = "tx";
clock-names = "mclk", "hclk";
@ -806,7 +1228,7 @@
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff880000 0x0 0x1000>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dmac_bus 0>, <&dmac_bus 1>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
@ -819,7 +1241,7 @@
i2s1: i2s@ff890000 {
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff890000 0x0 0x1000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dmac_bus 2>, <&dmac_bus 3>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
@ -832,7 +1254,7 @@
i2s2: i2s@ff8a0000 {
compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff8a0000 0x0 0x1000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
dmas = <&dmac_bus 4>, <&dmac_bus 5>;
dma-names = "tx", "rx";
clock-names = "i2s_clk", "i2s_hclk";
@ -852,7 +1274,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff720000 0x0 0x100>;
clocks = <&pmucru PCLK_GPIO0_PMU>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
gpio-controller;
#gpio-cells = <0x2>;
@ -865,7 +1287,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff730000 0x0 0x100>;
clocks = <&pmucru PCLK_GPIO1_PMU>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
gpio-controller;
#gpio-cells = <0x2>;
@ -878,7 +1300,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff780000 0x0 0x100>;
clocks = <&cru PCLK_GPIO2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
gpio-controller;
#gpio-cells = <0x2>;
@ -891,7 +1313,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff788000 0x0 0x100>;
clocks = <&cru PCLK_GPIO3>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
gpio-controller;
#gpio-cells = <0x2>;
@ -904,7 +1326,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x0 0xff790000 0x0 0x100>;
clocks = <&cru PCLK_GPIO4>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
gpio-controller;
#gpio-cells = <0x2>;
@ -955,6 +1377,72 @@
drive-strength = <13>;
};
clock {
clk_32k: clk-32k {
rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
};
};
gmac {
rgmii_pins: rgmii-pins {
rockchip,pins =
/* mac_txclk */
<3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_rxclk */
<3 14 RK_FUNC_1 &pcfg_pull_none>,
/* mac_mdio */
<3 13 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txen */
<3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_clk */
<3 11 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxdv */
<3 9 RK_FUNC_1 &pcfg_pull_none>,
/* mac_mdc */
<3 8 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxd1 */
<3 7 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxd0 */
<3 6 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd1 */
<3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_txd0 */
<3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_rxd3 */
<3 3 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxd2 */
<3 2 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd3 */
<3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_txd2 */
<3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
};
rmii_pins: rmii-pins {
rockchip,pins =
/* mac_mdio */
<3 13 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txen */
<3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_clk */
<3 11 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxer */
<3 10 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxdv */
<3 9 RK_FUNC_1 &pcfg_pull_none>,
/* mac_mdc */
<3 8 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxd1 */
<3 7 RK_FUNC_1 &pcfg_pull_none>,
/* mac_rxd0 */
<3 6 RK_FUNC_1 &pcfg_pull_none>,
/* mac_txd1 */
<3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
/* mac_txd0 */
<3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins =
@ -1326,5 +1814,18 @@
<1 14 RK_FUNC_1 &pcfg_pull_none>;
};
};
pcie {
pcie_clkreqn: pci-clkreqn {
rockchip,pins =
<2 26 RK_FUNC_2 &pcfg_pull_none>;
};
pcie_clkreqnb: pci-clkreqnb {
rockchip,pins =
<4 24 RK_FUNC_1 &pcfg_pull_none>;
};
};
};
};

4
arch/arm64/boot/dts/socionext/Makefile
View file

@ -1,4 +1,6 @@
dtb-$(CONFIG_ARCH_UNIPHIER) += uniphier-ph1-ld20-ref.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ld11-ref.dtb \
uniphier-ld20-ref.dtb
always := $(dtb-y)
clean-files := *.dtb

100
arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts Normal file
View file

@ -0,0 +1,100 @@
/*
* Device Tree Source for UniPhier LD11 Reference Board
*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
/include/ "uniphier-ld11.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
model = "UniPhier LD11 Reference Board";
compatible = "socionext,uniphier-ld11-ref", "socionext,uniphier-ld11";
memory {
device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
aliases {
serial0 = &serial0;
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
};
};
&ethsc {
interrupts = <0 48 4>;
};
&serial0 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};
&usb2 {
status = "okay";
};

338
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi Normal file
View file

@ -0,0 +1,338 @@
/*
* Device Tree Source for UniPhier LD11 SoC
*
* Copyright (C) 2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
/ {
compatible = "socionext,uniphier-ld11";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x000>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
reg = <0 0x001>;
enable-method = "spin-table";
cpu-release-addr = <0 0x80000000>;
};
};
clocks {
refclk: ref {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 4>,
<1 14 4>,
<1 11 4>,
<1 10 4>;
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
interrupts = <0 33 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
};
serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
interrupts = <0 35 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
};
serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
interrupts = <0 37 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
};
serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
interrupts = <0 177 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
};
i2c0: i2c@58780000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 41 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
clock-frequency = <100000>;
};
i2c1: i2c@58781000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 42 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
clock-frequency = <100000>;
};
i2c2: i2c@58782000 {
compatible = "socionext,uniphier-fi2c";
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 4>;
clocks = <&peri_clk 6>;
clock-frequency = <400000>;
};
i2c3: i2c@58783000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 44 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
clock-frequency = <100000>;
};
i2c4: i2c@58784000 {
compatible = "socionext,uniphier-fi2c";
status = "disabled";
reg = <0x58784000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 45 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&peri_clk 8>;
clock-frequency = <100000>;
};
i2c5: i2c@58785000 {
compatible = "socionext,uniphier-fi2c";
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 25 4>;
clocks = <&peri_clk 9>;
clock-frequency = <400000>;
};
system_bus: system-bus@58c00000 {
compatible = "socionext,uniphier-system-bus";
status = "disabled";
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_system_bus>;
};
smpctrl@59800000 {
compatible = "socionext,uniphier-smpctrl";
reg = <0x59801000 0x400>;
};
perictrl@59820000 {
compatible = "socionext,uniphier-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
peri_clk: clock {
compatible = "socionext,uniphier-ld11-peri-clock";
#clock-cells = <1>;
};
peri_rst: reset {
compatible = "socionext,uniphier-ld11-peri-reset";
#reset-cells = <1>;
};
};
usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
interrupts = <0 243 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>;
};
usb1: usb@5a810100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
interrupts = <0 244 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>;
};
usb2: usb@5a820100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
interrupts = <0 245 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>;
};
mioctrl@5b3e0000 {
compatible = "socionext,uniphier-mioctrl",
"simple-mfd", "syscon";
reg = <0x5b3e0000 0x800>;
mio_clk: clock {
compatible = "socionext,uniphier-ld11-mio-clock";
#clock-cells = <1>;
};
mio_rst: reset {
compatible = "socionext,uniphier-ld11-mio-reset";
#reset-cells = <1>;
resets = <&sys_rst 7>;
};
};
soc-glue@5f800000 {
compatible = "socionext,uniphier-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
pinctrl: pinctrl {
compatible = "socionext,uniphier-ld11-pinctrl";
};
};
gic: interrupt-controller@5fe00000 {
compatible = "arm,gic-v3";
reg = <0x5fe00000 0x10000>, /* GICD */
<0x5fe40000 0x80000>; /* GICR */
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <1 9 4>;
};
sysctrl@61840000 {
compatible = "socionext,uniphier-ld11-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
sys_clk: clock {
compatible = "socionext,uniphier-ld11-clock";
#clock-cells = <1>;
};
sys_rst: reset {
compatible = "socionext,uniphier-ld11-reset";
#reset-cells = <1>;
};
};
};
};
/include/ "uniphier-pinctrl.dtsi"

11
arch/arm64/boot/dts/socionext/uniphier-ph1-ld20-ref.dts → arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
View file

@ -1,7 +1,8 @@
/*
* Device Tree Source for UniPhier PH1-LD20 Reference Board
* Device Tree Source for UniPhier LD20 Reference Board
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -43,13 +44,13 @@
*/
/dts-v1/;
/include/ "uniphier-ph1-ld20.dtsi"
/include/ "uniphier-ld20.dtsi"
/include/ "uniphier-ref-daughter.dtsi"
/include/ "uniphier-support-card.dtsi"
/ {
model = "UniPhier PH1-LD20 Reference Board";
compatible = "socionext,ph1-ld20-ref", "socionext,ph1-ld20";
model = "UniPhier LD20 Reference Board";
compatible = "socionext,uniphier-ld20-ref", "socionext,uniphier-ld20";
memory {
device_type = "memory";

94
arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi → arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
View file

@ -1,7 +1,8 @@
/*
* Device Tree Source for UniPhier PH1-LD20 SoC
* Device Tree Source for UniPhier LD20 SoC
*
* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
* Copyright (C) 2015-2016 Socionext Inc.
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
@ -45,7 +46,7 @@
/memreserve/ 0x80000000 0x00000008; /* cpu-release-addr */
/ {
compatible = "socionext,ph1-ld20";
compatible = "socionext,uniphier-ld20";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
@ -113,18 +114,6 @@
#clock-cells = <0>;
clock-frequency = <25000000>;
};
uart_clk: uart_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <58820000>;
};
i2c_clk: i2c_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
timer {
@ -148,7 +137,7 @@
interrupts = <0 33 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&uart_clk>;
clocks = <&peri_clk 0>;
};
serial1: serial@54006900 {
@ -158,7 +147,7 @@
interrupts = <0 35 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&uart_clk>;
clocks = <&peri_clk 1>;
};
serial2: serial@54006a00 {
@ -168,7 +157,7 @@
interrupts = <0 37 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&uart_clk>;
clocks = <&peri_clk 2>;
};
serial3: serial@54006b00 {
@ -178,7 +167,7 @@
interrupts = <0 177 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&uart_clk>;
clocks = <&peri_clk 3>;
};
i2c0: i2c@58780000 {
@ -190,7 +179,7 @@
interrupts = <0 41 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 4>;
clock-frequency = <100000>;
};
@ -203,7 +192,7 @@
interrupts = <0 42 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 5>;
clock-frequency = <100000>;
};
@ -213,7 +202,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 43 4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 6>;
clock-frequency = <400000>;
};
@ -226,7 +215,7 @@
interrupts = <0 44 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 7>;
clock-frequency = <100000>;
};
@ -239,7 +228,7 @@
interrupts = <0 45 4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 8>;
clock-frequency = <100000>;
};
@ -249,7 +238,7 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <0 25 4>;
clocks = <&i2c_clk>;
clocks = <&peri_clk 9>;
clock-frequency = <400000>;
};
@ -259,6 +248,8 @@
reg = <0x58c00000 0x400>;
#address-cells = <2>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_system_bus>;
};
smpctrl@59800000 {
@ -266,12 +257,45 @@
reg = <0x59801000 0x400>;
};
mioctrl@59810000 {
compatible = "socionext,uniphier-mioctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x800>;
mio_clk: clock {
compatible = "socionext,uniphier-ld20-mio-clock";
#clock-cells = <1>;
};
mio_rst: reset {
compatible = "socionext,uniphier-ld20-mio-reset";
#reset-cells = <1>;
};
};
perictrl@59820000 {
compatible = "socionext,uniphier-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
peri_clk: clock {
compatible = "socionext,uniphier-ld20-peri-clock";
#clock-cells = <1>;
};
peri_rst: reset {
compatible = "socionext,uniphier-ld20-peri-reset";
#reset-cells = <1>;
};
};
soc-glue@5f800000 {
compatible = "simple-mfd", "syscon";
compatible = "socionext,uniphier-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
pinctrl: pinctrl {
compatible = "socionext,uniphier-ld20-pinctrl";
compatible = "socionext,uniphier-ld20-pinctrl";
};
};
@ -283,6 +307,22 @@
#interrupt-cells = <3>;
interrupts = <1 9 4>;
};
sysctrl@61840000 {
compatible = "socionext,uniphier-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x4000>;
sys_clk: clock {
compatible = "socionext,uniphier-ld20-clock";
#clock-cells = <1>;
};
sys_rst: reset {
compatible = "socionext,uniphier-ld20-reset";
#reset-cells = <1>;
};
};
};
};

2
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
View file

@ -29,7 +29,7 @@
memory {
device_type = "memory";
reg = <0x0 0x0 0x40000000>;
reg = <0x0 0x0 0x0 0x40000000>;
};
};

100
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View file

@ -14,7 +14,7 @@
/ {
compatible = "xlnx,zynqmp";
#address-cells = <2>;
#size-cells = <1>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
@ -51,6 +51,7 @@
pmu {
compatible = "arm,armv8-pmuv3";
interrupt-parent = <&gic>;
interrupts = <0 143 4>,
<0 144 4>,
<0 145 4>,
@ -75,15 +76,15 @@
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
ranges;
ranges = <0 0 0 0 0xffffffff>;
gic: interrupt-controller@f9010000 {
compatible = "arm,gic-400", "arm,cortex-a15-gic";
#interrupt-cells = <3>;
reg = <0x0 0xf9010000 0x10000>,
<0x0 0xf902f000 0x2000>,
<0x0 0xf9020000 0x20000>,
<0x0 0xf9040000 0x20000>,
<0x0 0xf906f000 0x2000>;
<0x0 0xf9060000 0x20000>;
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <1 9 0xf04>;
@ -93,14 +94,14 @@
amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
#size-cells = <2>;
ranges;
can0: can@ff060000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clock-names = "can_clk", "pclk";
reg = <0x0 0xff060000 0x1000>;
reg = <0x0 0xff060000 0x0 0x1000>;
interrupts = <0 23 4>;
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
@ -111,7 +112,7 @@
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clock-names = "can_clk", "pclk";
reg = <0x0 0xff070000 0x1000>;
reg = <0x0 0xff070000 0x0 0x1000>;
interrupts = <0 24 4>;
interrupt-parent = <&gic>;
tx-fifo-depth = <0x40>;
@ -123,7 +124,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 57 4>, <0 57 4>;
reg = <0x0 0xff0b0000 0x1000>;
reg = <0x0 0xff0b0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
@ -134,7 +135,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 59 4>, <0 59 4>;
reg = <0x0 0xff0c0000 0x1000>;
reg = <0x0 0xff0c0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
@ -145,7 +146,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 61 4>, <0 61 4>;
reg = <0x0 0xff0d0000 0x1000>;
reg = <0x0 0xff0d0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
@ -156,7 +157,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 63 4>, <0 63 4>;
reg = <0x0 0xff0e0000 0x1000>;
reg = <0x0 0xff0e0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
@ -170,7 +171,7 @@
interrupts = <0 16 4>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0xff0a0000 0x1000>;
reg = <0x0 0xff0a0000 0x0 0x1000>;
};
i2c0: i2c@ff020000 {
@ -178,7 +179,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 17 4>;
reg = <0x0 0xff020000 0x1000>;
reg = <0x0 0xff020000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
};
@ -188,15 +189,54 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 18 4>;
reg = <0x0 0xff030000 0x1000>;
reg = <0x0 0xff030000 0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
};
pcie: pcie@fd0e0000 {
compatible = "xlnx,nwl-pcie-2.11";
status = "disabled";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
msi-controller;
device_type = "pci";
interrupt-parent = <&gic>;
interrupts = <0 118 4>,
<0 117 4>,
<0 116 4>,
<0 115 4>, /* MSI_1 [63...32] */
<0 114 4>; /* MSI_0 [31...0] */
interrupt-names = "misc", "dummy", "intx",
"msi1", "msi0";
msi-parent = <&pcie>;
reg = <0x0 0xfd0e0000 0x0 0x1000>,
<0x0 0xfd480000 0x0 0x1000>,
<0x80 0x00000000 0x0 0x1000000>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x00000000 0xe0000000 0x00000000
0xe0000000 0x00000000 0x10000000
/* non-prefetchable memory */
0x43000000 0x00000006 0x00000000 0x00000006
0x00000000 0x00000002 0x00000000>;
/* prefetchable memory */
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
sata: ahci@fd0c0000 {
compatible = "ceva,ahci-1v84";
status = "disabled";
reg = <0x0 0xfd0c0000 0x2000>;
reg = <0x0 0xfd0c0000 0x0 0x2000>;
interrupt-parent = <&gic>;
interrupts = <0 133 4>;
};
@ -206,7 +246,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 48 4>;
reg = <0x0 0xff160000 0x1000>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
};
@ -215,13 +255,13 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 49 4>;
reg = <0x0 0xff170000 0x1000>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
};
smmu: smmu@fd800000 {
compatible = "arm,mmu-500";
reg = <0x0 0xfd800000 0x20000>;
reg = <0x0 0xfd800000 0x0 0x20000>;
#global-interrupts = <1>;
interrupt-parent = <&gic>;
interrupts = <0 157 4>,
@ -236,7 +276,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 19 4>;
reg = <0x0 0xff040000 0x1000>;
reg = <0x0 0xff040000 0x0 0x1000>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
@ -247,7 +287,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 20 4>;
reg = <0x0 0xff050000 0x1000>;
reg = <0x0 0xff050000 0x0 0x1000>;
clock-names = "ref_clk", "pclk";
#address-cells = <1>;
#size-cells = <0>;
@ -258,7 +298,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
reg = <0x0 0xff110000 0x1000>;
reg = <0x0 0xff110000 0x0 0x1000>;
timer-width = <32>;
};
@ -267,7 +307,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
reg = <0x0 0xff120000 0x1000>;
reg = <0x0 0xff120000 0x0 0x1000>;
timer-width = <32>;
};
@ -276,7 +316,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
reg = <0x0 0xff130000 0x1000>;
reg = <0x0 0xff130000 0x0 0x1000>;
timer-width = <32>;
};
@ -285,7 +325,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
reg = <0x0 0xff140000 0x1000>;
reg = <0x0 0xff140000 0x0 0x1000>;
timer-width = <32>;
};
@ -294,7 +334,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 21 4>;
reg = <0x0 0xff000000 0x1000>;
reg = <0x0 0xff000000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
};
@ -303,7 +343,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 22 4>;
reg = <0x0 0xff010000 0x1000>;
reg = <0x0 0xff010000 0x0 0x1000>;
clock-names = "uart_clk", "pclk";
};
@ -312,7 +352,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 65 4>;
reg = <0x0 0xfe200000 0x40000>;
reg = <0x0 0xfe200000 0x0 0x40000>;
clock-names = "clk_xin", "clk_ahb";
};
@ -321,7 +361,7 @@
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 70 4>;
reg = <0x0 0xfe300000 0x40000>;
reg = <0x0 0xfe300000 0x0 0x40000>;
clock-names = "clk_xin", "clk_ahb";
};
@ -329,8 +369,8 @@
compatible = "cdns,wdt-r1p2";
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 52 1>;
reg = <0x0 0xfd4d0000 0x1000>;
interrupts = <0 113 1>;
reg = <0x0 0xfd4d0000 0x0 0x1000>;
timeout-sec = <10>;
};
};

5
arch/arm64/boot/dts/zte/Makefile Normal file
View file

@ -0,0 +1,5 @@
dtb-$(CONFIG_ARCH_ZX) += zx296718-evb.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
clean-files := *.dtb

64
arch/arm64/boot/dts/zte/zx296718-evb.dts Normal file
View file

@ -0,0 +1,64 @@
/*
* Copyright 2016 ZTE Corporation.
* Copyright 2016 Linaro Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "zx296718.dtsi"
/ {
model = "ZTE zx296718 evaluation board";
compatible = "zte,zx296718-evb", "zte,zx296718";
chosen {
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x40000000>;
};
};
&uart0 {
status = "okay";
};

292
arch/arm64/boot/dts/zte/zx296718.dtsi Normal file
View file

@ -0,0 +1,292 @@
/*
* Copyright 2016 ZTE Corporation.
* Copyright 2016 Linaro Ltd.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "zte,zx296718";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
serial0 = &uart0;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
};
};
clk24k: clk-24k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000>;
clock-output-names = "rtcclk";
};
osc32k: clk-osc32k {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32000>;
clock-output-names = "osc32k";
};
osc12m: clk-osc12m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <12000000>;
clock-output-names = "osc12m";
};
osc24m: clk-osc24m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "osc24m";
};
osc25m: clk-osc25m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "osc25m";
};
osc60m: clk-osc60m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <60000000>;
clock-output-names = "osc60m";
};
osc99m: clk-osc99m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <99000000>;
clock-output-names = "osc99m";
};
osc125m: clk-osc125m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
clock-output-names = "osc125m";
};
osc198m: clk-osc198m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <198000000>;
clock-output-names = "osc198m";
};
pll_audio: clk-pll-884m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <884000000>;
clock-output-names = "pll_audio";
};
pll_ddr: clk-pll-932m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <932000000>;
clock-output-names = "pll_ddr";
};
pll_hsic: clk-pll-960m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <960000000>;
clock-output-names = "pll_hsic";
};
pll_mac: clk-pll-1000m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000000>;
clock-output-names = "pll_mac";
};
pll_vga: clk-pll-1073m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1073000000>;
clock-output-names = "pll_vga";
};
pll_mm0: clk-pll-1188m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1188000000>;
clock-output-names = "pll_mm0";
};
pll_mm1: clk-pll-1296m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1296000000>;
clock-output-names = "pll_mm1";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@2a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
#redistributor-regions = <6>;
redistributor-stride = <0x0 0x40000>;
interrupt-controller;
reg = <0x02a00000 0x10000>,
<0x02b00000 0x20000>,
<0x02b20000 0x20000>,
<0x02b40000 0x20000>,
<0x02b60000 0x20000>,
<0x02b80000 0x20000>,
<0x02ba0000 0x20000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
aon_sysctrl: aon-sysctrl@116000 {
compatible = "zte,zx296718-aon-sysctrl", "syscon";
reg = <0x116000 0x1000>;
};
uart0: uart@11f000 {
compatible = "arm,pl011", "arm,primecell";
arm,primecell-periphid = <0x001feffe>;
reg = <0x11f000 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24m>;
clock-names = "apb_pclk";
status = "disabled";
};
dma: dma-controller@1460000 {
compatible = "zte,zx296702-dma";
reg = <0x01460000 0x1000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24m>;
clock-names = "dmaclk";
#dma-cells = <1>;
dma-channels = <32>;
dma-requests = <32>;
};
sysctrl: sysctrl@1463000 {
compatible = "zte,zx296718-sysctrl", "syscon";
reg = <0x1463000 0x1000>;
};
};
};