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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00
net: stmmac: configure SerDes according to the interface mode
Intel platform will configure the SerDes through PMC API based on the provided interface mode. This patch adds several new functions below:- - intel_tsn_lane_is_available(): This new function reads FIA lane ownership registers and common lane registers through IPC commands to know which lane the mGbE port is assigned to. - intel_mac_finish(): To configure the SerDes based on the assigned lane and latest interface mode, it sends IPC command to the PMC through PMC driver/API. The PMC acts as a proxy for R/W on behalf of the driver. - intel_set_reg_access(): Set the register access to the available TSN interface. Signed-off-by: Choong Yong Liang <yong.liang.choong@linux.intel.com> Link: https://patch.msgid.link/20250227121522.1802832-6-yong.liang.choong@linux.intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Choong Yong Liang
Jakub Kicinski
parent
e654cfc718
commit
a42f6b3f1c
3 changed files with 204 additions and 5 deletions
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@ -307,6 +307,7 @@ config DWMAC_INTEL
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default X86
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depends on X86 && STMMAC_ETH && PCI
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depends on COMMON_CLK
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depends on ACPI
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help
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This selects the Intel platform specific bus support for the
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stmmac driver. This driver is used for Intel Quark/EHL/TGL.
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@ -5,15 +5,30 @@
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#include <linux/clk-provider.h>
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#include <linux/pci.h>
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#include <linux/dmi.h>
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#include <linux/platform_data/x86/intel_pmc_ipc.h>
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#include "dwmac-intel.h"
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#include "dwmac4.h"
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#include "stmmac.h"
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#include "stmmac_ptp.h"
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struct pmc_serdes_regs {
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u8 index;
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u32 val;
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};
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struct pmc_serdes_reg_info {
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const struct pmc_serdes_regs *regs;
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u8 num_regs;
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};
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struct intel_priv_data {
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int mdio_adhoc_addr; /* mdio address for serdes & etc */
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unsigned long crossts_adj;
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bool is_pse;
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const int *tsn_lane_regs;
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int max_tsn_lane_regs;
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struct pmc_serdes_reg_info pid_1g;
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struct pmc_serdes_reg_info pid_2p5g;
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};
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/* This struct is used to associate PCI Function of MAC controller on a board,
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@ -35,6 +50,44 @@ struct stmmac_pci_info {
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int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
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};
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static const struct pmc_serdes_regs pid_modphy3_1g_regs[] = {
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{ PID_MODPHY3_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_1G },
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{ PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_1G },
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{ PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_1G },
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{ PID_MODPHY3_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_1G },
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{ PID_MODPHY3_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_1G },
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{}
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};
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static const struct pmc_serdes_regs pid_modphy3_2p5g_regs[] = {
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{ PID_MODPHY3_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_2P5G },
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{ PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_2P5G },
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{ PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_2P5G },
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{ PID_MODPHY3_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_2P5G },
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{ PID_MODPHY3_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G },
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{}
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};
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static const struct pmc_serdes_regs pid_modphy1_1g_regs[] = {
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{ PID_MODPHY1_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_1G },
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{ PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_1G },
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{ PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_1G },
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{ PID_MODPHY1_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_1G },
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{ PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_1G },
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{}
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};
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static const struct pmc_serdes_regs pid_modphy1_2p5g_regs[] = {
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{ PID_MODPHY1_B_MODPHY_PCR_LCPLL_DWORD0, B_MODPHY_PCR_LCPLL_DWORD0_2P5G },
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{ PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD2, N_MODPHY_PCR_LCPLL_DWORD2_2P5G },
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{ PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD7, N_MODPHY_PCR_LCPLL_DWORD7_2P5G },
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{ PID_MODPHY1_N_MODPHY_PCR_LPPLL_DWORD10, N_MODPHY_PCR_LPPLL_DWORD10_2P5G },
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{ PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30, N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G },
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{}
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};
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static const int ehl_tsn_lane_regs[] = {7, 8, 9, 10, 11};
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static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
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const struct dmi_system_id *dmi_list)
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{
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@ -93,7 +146,7 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
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data &= ~SERDES_RATE_MASK;
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data &= ~SERDES_PCLK_MASK;
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if (priv->plat->max_speed == 2500)
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if (priv->plat->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
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data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT |
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SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT;
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else
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@ -415,6 +468,95 @@ static void intel_mgbe_pse_crossts_adj(struct intel_priv_data *intel_priv,
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}
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}
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static int intel_tsn_lane_is_available(struct net_device *ndev,
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struct intel_priv_data *intel_priv)
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{
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struct stmmac_priv *priv = netdev_priv(ndev);
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struct pmc_ipc_cmd tmp = {};
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struct pmc_ipc_rbuf rbuf = {};
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int ret = 0, i, j;
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const int max_fia_regs = 5;
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tmp.cmd = IPC_SOC_REGISTER_ACCESS;
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tmp.sub_cmd = IPC_SOC_SUB_CMD_READ;
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for (i = 0; i < max_fia_regs; i++) {
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tmp.wbuf[0] = R_PCH_FIA_15_PCR_LOS1_REG_BASE + i;
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ret = intel_pmc_ipc(&tmp, &rbuf);
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if (ret < 0) {
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netdev_info(priv->dev, "Failed to read from PMC.\n");
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return ret;
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}
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for (j = 0; j <= intel_priv->max_tsn_lane_regs; j++)
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if ((rbuf.buf[0] >>
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(4 * (intel_priv->tsn_lane_regs[j] % 8)) &
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B_PCH_FIA_PCR_L0O) == 0xB)
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return ret;
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}
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return ret;
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}
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static int intel_set_reg_access(const struct pmc_serdes_regs *regs, int max_regs)
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{
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int ret = 0, i;
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for (i = 0; i < max_regs; i++) {
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struct pmc_ipc_cmd tmp = {};
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struct pmc_ipc_rbuf rbuf = {};
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tmp.cmd = IPC_SOC_REGISTER_ACCESS;
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tmp.sub_cmd = IPC_SOC_SUB_CMD_WRITE;
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tmp.wbuf[0] = (u32)regs[i].index;
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tmp.wbuf[1] = regs[i].val;
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ret = intel_pmc_ipc(&tmp, &rbuf);
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if (ret < 0)
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return ret;
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}
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return ret;
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}
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static int intel_mac_finish(struct net_device *ndev,
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void *intel_data,
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unsigned int mode,
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phy_interface_t interface)
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{
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struct intel_priv_data *intel_priv = intel_data;
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struct stmmac_priv *priv = netdev_priv(ndev);
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const struct pmc_serdes_regs *regs;
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int max_regs = 0;
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int ret = 0;
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ret = intel_tsn_lane_is_available(ndev, intel_priv);
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if (ret < 0) {
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netdev_info(priv->dev, "No TSN lane available to set the registers.\n");
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return ret;
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}
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if (interface == PHY_INTERFACE_MODE_2500BASEX) {
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regs = intel_priv->pid_2p5g.regs;
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max_regs = intel_priv->pid_2p5g.num_regs;
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} else {
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regs = intel_priv->pid_1g.regs;
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max_regs = intel_priv->pid_1g.num_regs;
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}
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ret = intel_set_reg_access(regs, max_regs);
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if (ret < 0)
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return ret;
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priv->plat->phy_interface = interface;
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intel_serdes_powerdown(ndev, intel_priv);
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intel_serdes_powerup(ndev, intel_priv);
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return ret;
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}
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static void common_default_data(struct plat_stmmacenet_data *plat)
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{
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plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
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@ -624,6 +766,8 @@ static int intel_mgbe_common_data(struct pci_dev *pdev,
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static int ehl_common_data(struct pci_dev *pdev,
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struct plat_stmmacenet_data *plat)
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{
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struct intel_priv_data *intel_priv = plat->bsp_priv;
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plat->rx_queues_to_use = 8;
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plat->tx_queues_to_use = 8;
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plat->flags |= STMMAC_FLAG_USE_PHY_WOL;
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@ -639,20 +783,29 @@ static int ehl_common_data(struct pci_dev *pdev,
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plat->safety_feat_cfg->prtyen = 0;
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plat->safety_feat_cfg->tmouten = 0;
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intel_priv->tsn_lane_regs = ehl_tsn_lane_regs;
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intel_priv->max_tsn_lane_regs = ARRAY_SIZE(ehl_tsn_lane_regs);
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return intel_mgbe_common_data(pdev, plat);
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}
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static int ehl_sgmii_data(struct pci_dev *pdev,
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struct plat_stmmacenet_data *plat)
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{
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struct intel_priv_data *intel_priv = plat->bsp_priv;
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plat->bus_id = 1;
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plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
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plat->speed_mode_2500 = intel_speed_mode_2500;
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plat->serdes_powerup = intel_serdes_powerup;
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plat->serdes_powerdown = intel_serdes_powerdown;
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plat->mac_finish = intel_mac_finish;
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plat->clk_ptp_rate = 204800000;
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intel_priv->pid_1g.regs = pid_modphy3_1g_regs;
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intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy3_1g_regs);
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intel_priv->pid_2p5g.regs = pid_modphy3_2p5g_regs;
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intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy3_2p5g_regs);
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return ehl_common_data(pdev, plat);
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}
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@ -705,10 +858,18 @@ static struct stmmac_pci_info ehl_pse0_rgmii1g_info = {
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static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
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struct plat_stmmacenet_data *plat)
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{
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struct intel_priv_data *intel_priv = plat->bsp_priv;
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plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
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plat->speed_mode_2500 = intel_speed_mode_2500;
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plat->serdes_powerup = intel_serdes_powerup;
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plat->serdes_powerdown = intel_serdes_powerdown;
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plat->mac_finish = intel_mac_finish;
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intel_priv->pid_1g.regs = pid_modphy1_1g_regs;
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intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy1_1g_regs);
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intel_priv->pid_2p5g.regs = pid_modphy1_2p5g_regs;
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intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy1_2p5g_regs);
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return ehl_pse0_common_data(pdev, plat);
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}
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@ -746,10 +907,18 @@ static struct stmmac_pci_info ehl_pse1_rgmii1g_info = {
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static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
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struct plat_stmmacenet_data *plat)
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{
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struct intel_priv_data *intel_priv = plat->bsp_priv;
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plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
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plat->speed_mode_2500 = intel_speed_mode_2500;
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plat->serdes_powerup = intel_serdes_powerup;
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plat->serdes_powerdown = intel_serdes_powerdown;
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plat->mac_finish = intel_mac_finish;
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intel_priv->pid_1g.regs = pid_modphy1_1g_regs;
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intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy1_1g_regs);
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intel_priv->pid_2p5g.regs = pid_modphy1_2p5g_regs;
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intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy1_2p5g_regs);
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return ehl_pse1_common_data(pdev, plat);
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}
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@ -50,4 +50,33 @@
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#define PCH_PTP_CLK_FREQ_19_2MHZ (GMAC_GPO0)
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#define PCH_PTP_CLK_FREQ_200MHZ (0)
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/* Modphy Register index */
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#define R_PCH_FIA_15_PCR_LOS1_REG_BASE 8
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#define R_PCH_FIA_15_PCR_LOS2_REG_BASE 9
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#define R_PCH_FIA_15_PCR_LOS3_REG_BASE 10
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#define R_PCH_FIA_15_PCR_LOS4_REG_BASE 11
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#define R_PCH_FIA_15_PCR_LOS5_REG_BASE 12
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#define B_PCH_FIA_PCR_L0O GENMASK(3, 0)
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#define PID_MODPHY1_B_MODPHY_PCR_LCPLL_DWORD0 13
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#define PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD2 14
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#define PID_MODPHY1_N_MODPHY_PCR_LCPLL_DWORD7 15
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#define PID_MODPHY1_N_MODPHY_PCR_LPPLL_DWORD10 16
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#define PID_MODPHY1_N_MODPHY_PCR_CMN_ANA_DWORD30 17
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#define PID_MODPHY3_B_MODPHY_PCR_LCPLL_DWORD0 18
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#define PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD2 19
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#define PID_MODPHY3_N_MODPHY_PCR_LCPLL_DWORD7 20
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#define PID_MODPHY3_N_MODPHY_PCR_LPPLL_DWORD10 21
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#define PID_MODPHY3_N_MODPHY_PCR_CMN_ANA_DWORD30 22
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#define B_MODPHY_PCR_LCPLL_DWORD0_1G 0x46AAAA41
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#define N_MODPHY_PCR_LCPLL_DWORD2_1G 0x00000139
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#define N_MODPHY_PCR_LCPLL_DWORD7_1G 0x002A0003
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#define N_MODPHY_PCR_LPPLL_DWORD10_1G 0x00170008
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#define N_MODPHY_PCR_CMN_ANA_DWORD30_1G 0x0000D4AC
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#define B_MODPHY_PCR_LCPLL_DWORD0_2P5G 0x58555551
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#define N_MODPHY_PCR_LCPLL_DWORD2_2P5G 0x0000012D
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#define N_MODPHY_PCR_LCPLL_DWORD7_2P5G 0x001F0003
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#define N_MODPHY_PCR_LPPLL_DWORD10_2P5G 0x00170008
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#define N_MODPHY_PCR_CMN_ANA_DWORD30_2P5G 0x8200ACAC
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#endif /* __DWMAC_INTEL_H__ */
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