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clk: tegra: Initialize PLL_C to sane rate on Tegra30

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If the bootloader does not touch PLL_C it will stay in its reset state,
failing to lock when enabled. This leads to consumers of this clock to
fail probing. Fix this by always programming the PLL with a sane rate,
which allows it to lock, at startup.

Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Lucas Stach 2016-02-29 21:46:06 +01:00 • committed by Thierry Reding
parent 926655f929
commit a02cc84a31
1 changed files with 1 additions and 0 deletions
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drivers/clk/tegra/clk-tegra30.c
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@ -1372,6 +1372,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
{ TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 },
{ TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 },
{ TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
{ TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
{ TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 },
{ TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 },
{ TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 },