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KVM: arm64: Extend masking facility to arbitrary registers
We currently only use the masking (RES0/RES1) facility for VNCR registers, as they are memory-based and thus easy to sanitise. But we could apply the same thing to other registers if we: - split the sanitisation from __VNCR_START__ - apply the sanitisation when reading from a HW register This involves a new "marker" in the vcpu_sysreg enum, which defines the point at which the sanitisation applies (the VNCR registers being of course after this marker). Whle we are at it, rename kvm_vcpu_sanitise_vncr_reg() to kvm_vcpu_apply_reg_masks(), which is vaguely more explicit, and harden set_sysreg_masks() against setting masks for random registers... Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Joey Gouly <joey.gouly@arm.com> Link: https://lore.kernel.org/r/20241023145345.1613824-10-maz@kernel.org Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
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a016202009
3 changed files with 24 additions and 10 deletions
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@ -374,7 +374,7 @@ struct kvm_arch {
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u64 ctr_el0;
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/* Masks for VNCR-baked sysregs */
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/* Masks for VNCR-backed and general EL2 sysregs */
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struct kvm_sysreg_masks *sysreg_masks;
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/*
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@ -408,6 +408,9 @@ struct kvm_vcpu_fault_info {
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r = __VNCR_START__ + ((VNCR_ ## r) / 8), \
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__after_##r = __MAX__(__before_##r - 1, r)
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#define MARKER(m) \
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m, __after_##m = m - 1
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enum vcpu_sysreg {
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__INVALID_SYSREG__, /* 0 is reserved as an invalid value */
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MPIDR_EL1, /* MultiProcessor Affinity Register */
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@ -494,7 +497,11 @@ enum vcpu_sysreg {
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CNTHV_CTL_EL2,
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CNTHV_CVAL_EL2,
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__VNCR_START__, /* Any VNCR-capable reg goes after this point */
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/* Anything from this can be RES0/RES1 sanitised */
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MARKER(__SANITISED_REG_START__),
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/* Any VNCR-capable reg goes after this point */
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MARKER(__VNCR_START__),
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VNCR(SCTLR_EL1),/* System Control Register */
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VNCR(ACTLR_EL1),/* Auxiliary Control Register */
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@ -554,7 +561,7 @@ struct kvm_sysreg_masks {
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struct {
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u64 res0;
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u64 res1;
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} mask[NR_SYS_REGS - __VNCR_START__];
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} mask[NR_SYS_REGS - __SANITISED_REG_START__];
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};
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struct kvm_cpu_context {
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@ -1002,13 +1009,13 @@ static inline u64 *___ctxt_sys_reg(const struct kvm_cpu_context *ctxt, int r)
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#define ctxt_sys_reg(c,r) (*__ctxt_sys_reg(c,r))
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u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *, enum vcpu_sysreg);
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u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *, enum vcpu_sysreg, u64);
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#define __vcpu_sys_reg(v,r) \
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(*({ \
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const struct kvm_cpu_context *ctxt = &(v)->arch.ctxt; \
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u64 *__r = __ctxt_sys_reg(ctxt, (r)); \
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if (vcpu_has_nv((v)) && (r) >= __VNCR_START__) \
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*__r = kvm_vcpu_sanitise_vncr_reg((v), (r)); \
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if (vcpu_has_nv((v)) && (r) >= __SANITISED_REG_START__) \
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*__r = kvm_vcpu_apply_reg_masks((v), (r), *__r);\
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__r; \
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}))
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@ -933,15 +933,15 @@ static void limit_nv_id_regs(struct kvm *kvm)
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kvm_set_vm_id_reg(kvm, SYS_ID_AA64DFR0_EL1, val);
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}
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u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg sr)
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u64 kvm_vcpu_apply_reg_masks(const struct kvm_vcpu *vcpu,
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enum vcpu_sysreg sr, u64 v)
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{
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u64 v = ctxt_sys_reg(&vcpu->arch.ctxt, sr);
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struct kvm_sysreg_masks *masks;
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masks = vcpu->kvm->arch.sysreg_masks;
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if (masks) {
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sr -= __VNCR_START__;
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sr -= __SANITISED_REG_START__;
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v &= ~masks->mask[sr].res0;
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v |= masks->mask[sr].res1;
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@ -952,7 +952,11 @@ u64 kvm_vcpu_sanitise_vncr_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg sr)
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static void set_sysreg_masks(struct kvm *kvm, int sr, u64 res0, u64 res1)
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{
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int i = sr - __VNCR_START__;
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int i = sr - __SANITISED_REG_START__;
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BUILD_BUG_ON(!__builtin_constant_p(sr));
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BUILD_BUG_ON(sr < __SANITISED_REG_START__);
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BUILD_BUG_ON(sr >= NR_SYS_REGS);
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kvm->arch.sysreg_masks->mask[i].res0 = res0;
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kvm->arch.sysreg_masks->mask[i].res1 = res1;
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@ -189,6 +189,9 @@ u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
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/* Get the current version of the EL1 counterpart. */
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WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val));
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if (reg >= __SANITISED_REG_START__)
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val = kvm_vcpu_apply_reg_masks(vcpu, reg, val);
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return val;
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}
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