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ARM: OMAP4: hwmod data: Update AESS data with memory bank area
Add AESS memory bank data in hwmod in order to provide memory address information to the driver. This version also changes the AESS main clock to use a non-CLKCTRL-based functional clock. These are being removed from the clock data, since they should be handled by the IP block integration code. Without this change, the kernel crashes during boot. Thanks to Tony Lindgren for reporting this during a test merge. Signed-off-by: Sebastien Guiriec <s-guiriec@ti.com> [paul@pwsan.com: updated to change the AESS main_clk] Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
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c02060d869
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1 changed files with 43 additions and 1 deletions
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@ -349,7 +349,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
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.clkdm_name = "abe_clkdm",
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.mpu_irqs = omap44xx_aess_irqs,
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.sdma_reqs = omap44xx_aess_sdma_reqs,
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.main_clk = "aess_fck",
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.main_clk = "aess_fclk",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
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@ -4250,6 +4250,27 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
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static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
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{
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.name = "dmem",
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.pa_start = 0x40180000,
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.pa_end = 0x4018ffff
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},
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{
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.name = "cmem",
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.pa_start = 0x401a0000,
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.pa_end = 0x401a1fff
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},
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{
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.name = "smem",
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.pa_start = 0x401c0000,
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.pa_end = 0x401c5fff
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},
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{
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.name = "pmem",
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.pa_start = 0x401e0000,
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.pa_end = 0x401e1fff
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},
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{
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.name = "mpu",
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.pa_start = 0x401f1000,
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.pa_end = 0x401f13ff,
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.flags = ADDR_TYPE_RT
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@ -4268,6 +4289,27 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
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static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
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{
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.name = "dmem_dma",
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.pa_start = 0x49080000,
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.pa_end = 0x4908ffff
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},
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{
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.name = "cmem_dma",
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.pa_start = 0x490a0000,
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.pa_end = 0x490a1fff
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},
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{
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.name = "smem_dma",
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.pa_start = 0x490c0000,
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.pa_end = 0x490c5fff
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},
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{
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.name = "pmem_dma",
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.pa_start = 0x490e0000,
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.pa_end = 0x490e1fff
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},
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{
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.name = "dma",
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.pa_start = 0x490f1000,
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.pa_end = 0x490f13ff,
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.flags = ADDR_TYPE_RT
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