Linux 4.12-rc5

2025-08-05 16:54:27 +00:00 · 2017-06-28 13:34:15 -04:00 · 2017-06-28 13:34:15 -04:00 · 9a1d168e1b
commit 9a1d168e1b
parent bb2a8b0cd1 32c1431eea
1219 changed files with 13283 additions and 6898 deletions
--- a/Documentation/acpi/acpi-lid.txt
+++ b/Documentation/acpi/acpi-lid.txt
@ -59,20 +59,28 @@ button driver uses the following 3 modes in order not to trigger issues.
 If the userspace hasn't been prepared to ignore the unreliable "opened"
 events and the unreliable initial state notification, Linux users can use
 the following kernel parameters to handle the possible issues:
-A. button.lid_init_state=open:
+A. button.lid_init_state=method:
   When this option is specified, the ACPI button driver reports the
   initial lid state using the returning value of the _LID control method
   and whether the "opened"/"closed" events are paired fully relies on the
   firmware implementation.
   This option can be used to fix some platforms where the returning value
   of the _LID control method is reliable but the initial lid state
   notification is missing.
   This option is the default behavior during the period the userspace
   isn't ready to handle the buggy AML tables.
 B. button.lid_init_state=open:
   When this option is specified, the ACPI button driver always reports the
   initial lid state as "opened" and whether the "opened"/"closed" events
   are paired fully relies on the firmware implementation.
   This may fix some platforms where the returning value of the _LID
   control method is not reliable and the initial lid state notification is
   missing.
   This option is the default behavior during the period the userspace
   isn't ready to handle the buggy AML tables.
 If the userspace has been prepared to ignore the unreliable "opened" events
 and the unreliable initial state notification, Linux users should always
 use the following kernel parameter:
-B. button.lid_init_state=ignore:
+C. button.lid_init_state=ignore:
   When this option is specified, the ACPI button driver never reports the
   initial lid state and there is a compensation mechanism implemented to
   ensure that the reliable "closed" notifications can always be delievered
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@ -866,6 +866,15 @@
 	dscc4.setup=	[NET]
 	dt_cpu_ftrs=	[PPC]
 			Format: {"off" | "known"}
 			Control how the dt_cpu_ftrs device-tree binding is
 			used for CPU feature discovery and setup (if it
 			exists).
 			off: Do not use it, fall back to legacy cpu table.
 			known: Do not pass through unknown features to guests
 			or userspace, only those that the kernel is aware of.
 	dump_apple_properties	[X86]
 			Dump name and content of EFI device properties on
 			x86 Macs.  Useful for driver authors to determine
--- a/Documentation/admin-guide/pm/cpufreq.rst
+++ b/Documentation/admin-guide/pm/cpufreq.rst
@ -1,4 +1,5 @@
 .. |struct cpufreq_policy| replace:: :c:type:`struct cpufreq_policy <cpufreq_policy>`
 .. |intel_pstate| replace:: :doc:`intel_pstate <intel_pstate>`
 =======================
 CPU Performance Scaling
@ -75,7 +76,7 @@ feedback registers, as that information is typically specific to the hardware
 interface it comes from and may not be easily represented in an abstract,
 platform-independent way.  For this reason, ``CPUFreq`` allows scaling drivers
 to bypass the governor layer and implement their own performance scaling
-algorithms.  That is done by the ``intel_pstate`` scaling driver.
+algorithms.  That is done by the |intel_pstate| scaling driver.
 ``CPUFreq`` Policy Objects
@ -174,13 +175,13 @@ necessary to restart the scaling governor so that it can take the new online CPU
 into account.  That is achieved by invoking the governor's ``->stop`` and
 ``->start()`` callbacks, in this order, for the entire policy.
-As mentioned before, the ``intel_pstate`` scaling driver bypasses the scaling
+As mentioned before, the |intel_pstate| scaling driver bypasses the scaling
 governor layer of ``CPUFreq`` and provides its own P-state selection algorithms.
-Consequently, if ``intel_pstate`` is used, scaling governors are not attached to
+Consequently, if |intel_pstate| is used, scaling governors are not attached to
 new policy objects.  Instead, the driver's ``->setpolicy()`` callback is invoked
 to register per-CPU utilization update callbacks for each policy.  These
 callbacks are invoked by the CPU scheduler in the same way as for scaling
-governors, but in the ``intel_pstate`` case they both determine the P-state to
+governors, but in the |intel_pstate| case they both determine the P-state to
 use and change the hardware configuration accordingly in one go from scheduler
 context.
@ -257,7 +258,7 @@ are the following:
 ``scaling_available_governors``
 	List of ``CPUFreq`` scaling governors present in the kernel that can
-	be attached to this policy or (if the ``intel_pstate`` scaling driver is
+	be attached to this policy or (if the |intel_pstate| scaling driver is
 	in use) list of scaling algorithms provided by the driver that can be
 	applied to this policy.
@ -274,7 +275,7 @@ are the following:
 	the CPU is actually running at (due to hardware design and other
 	limitations).
-	Some scaling drivers (e.g. ``intel_pstate``) attempt to provide
+	Some scaling drivers (e.g. |intel_pstate|) attempt to provide
 	information more precisely reflecting the current CPU frequency through
 	this attribute, but that still may not be the exact current CPU
 	frequency as seen by the hardware at the moment.
@ -284,13 +285,13 @@ are the following:
 ``scaling_governor``
 	The scaling governor currently attached to this policy or (if the
-	``intel_pstate`` scaling driver is in use) the scaling algorithm
+	|intel_pstate| scaling driver is in use) the scaling algorithm
 	provided by the driver that is currently applied to this policy.
 	This attribute is read-write and writing to it will cause a new scaling
 	governor to be attached to this policy or a new scaling algorithm
 	provided by the scaling driver to be applied to it (in the
-	``intel_pstate`` case), as indicated by the string written to this
+	|intel_pstate| case), as indicated by the string written to this
 	attribute (which must be one of the names listed by the
 	``scaling_available_governors`` attribute described above).
@ -619,7 +620,7 @@ This file is located under :file:`/sys/devices/system/cpu/cpufreq/` and controls
 the "boost" setting for the whole system.  It is not present if the underlying
 scaling driver does not support the frequency boost mechanism (or supports it,
 but provides a driver-specific interface for controlling it, like
-``intel_pstate``).
+|intel_pstate|).
 If the value in this file is 1, the frequency boost mechanism is enabled.  This
 means that either the hardware can be put into states in which it is able to
--- a/Documentation/admin-guide/pm/index.rst
+++ b/Documentation/admin-guide/pm/index.rst
@ -6,6 +6,7 @@ Power Management
   :maxdepth: 2
   cpufreq
   intel_pstate
 .. only::  subproject and html
--- a/Documentation/admin-guide/pm/intel_pstate.rst
+++ b/Documentation/admin-guide/pm/intel_pstate.rst
@ -0,0 +1,755 @@
 ===============================================
 ``intel_pstate`` CPU Performance Scaling Driver
 ===============================================
 ::
 Copyright (c) 2017 Intel Corp., Rafael J. Wysocki <rafael.j.wysocki@intel.com>
 General Information
 ===================
 ``intel_pstate`` is a part of the
 :doc:`CPU performance scaling subsystem <cpufreq>` in the Linux kernel
 (``CPUFreq``).  It is a scaling driver for the Sandy Bridge and later
 generations of Intel processors.  Note, however, that some of those processors
 may not be supported.  [To understand ``intel_pstate`` it is necessary to know
 how ``CPUFreq`` works in general, so this is the time to read :doc:`cpufreq` if
 you have not done that yet.]
 For the processors supported by ``intel_pstate``, the P-state concept is broader
 than just an operating frequency or an operating performance point (see the
 `LinuxCon Europe 2015 presentation by Kristen Accardi <LCEU2015_>`_ for more
 information about that).  For this reason, the representation of P-states used
 by ``intel_pstate`` internally follows the hardware specification (for details
 refer to `Intel® 64 and IA-32 Architectures Software Developer’s Manual
 Volume 3: System Programming Guide <SDM_>`_).  However, the ``CPUFreq`` core
 uses frequencies for identifying operating performance points of CPUs and
 frequencies are involved in the user space interface exposed by it, so
 ``intel_pstate`` maps its internal representation of P-states to frequencies too
 (fortunately, that mapping is unambiguous).  At the same time, it would not be
 practical for ``intel_pstate`` to supply the ``CPUFreq`` core with a table of
 available frequencies due to the possible size of it, so the driver does not do
 that.  Some functionality of the core is limited by that.
 Since the hardware P-state selection interface used by ``intel_pstate`` is
 available at the logical CPU level, the driver always works with individual
 CPUs.  Consequently, if ``intel_pstate`` is in use, every ``CPUFreq`` policy
 object corresponds to one logical CPU and ``CPUFreq`` policies are effectively
 equivalent to CPUs.  In particular, this means that they become "inactive" every
 time the corresponding CPU is taken offline and need to be re-initialized when
 it goes back online.
 ``intel_pstate`` is not modular, so it cannot be unloaded, which means that the
 only way to pass early-configuration-time parameters to it is via the kernel
 command line.  However, its configuration can be adjusted via ``sysfs`` to a
 great extent.  In some configurations it even is possible to unregister it via
 ``sysfs`` which allows another ``CPUFreq`` scaling driver to be loaded and
 registered (see `below <status_attr_>`_).
 Operation Modes
 ===============
 ``intel_pstate`` can operate in three different modes: in the active mode with
 or without hardware-managed P-states support and in the passive mode.  Which of
 them will be in effect depends on what kernel command line options are used and
 on the capabilities of the processor.
 Active Mode
 -----------
 This is the default operation mode of ``intel_pstate``.  If it works in this
 mode, the ``scaling_driver`` policy attribute in ``sysfs`` for all ``CPUFreq``
 policies contains the string "intel_pstate".
 In this mode the driver bypasses the scaling governors layer of ``CPUFreq`` and
 provides its own scaling algorithms for P-state selection.  Those algorithms
 can be applied to ``CPUFreq`` policies in the same way as generic scaling
 governors (that is, through the ``scaling_governor`` policy attribute in
 ``sysfs``).  [Note that different P-state selection algorithms may be chosen for
 different policies, but that is not recommended.]
 They are not generic scaling governors, but their names are the same as the
 names of some of those governors.  Moreover, confusingly enough, they generally
 do not work in the same way as the generic governors they share the names with.
 For example, the ``powersave`` P-state selection algorithm provided by
 ``intel_pstate`` is not a counterpart of the generic ``powersave`` governor
 (roughly, it corresponds to the ``schedutil`` and ``ondemand`` governors).
 There are two P-state selection algorithms provided by ``intel_pstate`` in the
 active mode: ``powersave`` and ``performance``.  The way they both operate
 depends on whether or not the hardware-managed P-states (HWP) feature has been
 enabled in the processor and possibly on the processor model.
 Which of the P-state selection algorithms is used by default depends on the
 :c:macro:`CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE` kernel configuration option.
 Namely, if that option is set, the ``performance`` algorithm will be used by
 default, and the other one will be used by default if it is not set.
 Active Mode With HWP
 ~~~~~~~~~~~~~~~~~~~~
 If the processor supports the HWP feature, it will be enabled during the
 processor initialization and cannot be disabled after that.  It is possible
 to avoid enabling it by passing the ``intel_pstate=no_hwp`` argument to the
 kernel in the command line.
 If the HWP feature has been enabled, ``intel_pstate`` relies on the processor to
 select P-states by itself, but still it can give hints to the processor's
 internal P-state selection logic.  What those hints are depends on which P-state
 selection algorithm has been applied to the given policy (or to the CPU it
 corresponds to).
 Even though the P-state selection is carried out by the processor automatically,
 ``intel_pstate`` registers utilization update callbacks with the CPU scheduler
 in this mode.  However, they are not used for running a P-state selection
 algorithm, but for periodic updates of the current CPU frequency information to
 be made available from the ``scaling_cur_freq`` policy attribute in ``sysfs``.
 HWP + ``performance``
 .....................
 In this configuration ``intel_pstate`` will write 0 to the processor's
 Energy-Performance Preference (EPP) knob (if supported) or its
 Energy-Performance Bias (EPB) knob (otherwise), which means that the processor's
 internal P-state selection logic is expected to focus entirely on performance.
 This will override the EPP/EPB setting coming from the ``sysfs`` interface
 (see `Energy vs Performance Hints`_ below).
 Also, in this configuration the range of P-states available to the processor's
 internal P-state selection logic is always restricted to the upper boundary
 (that is, the maximum P-state that the driver is allowed to use).
 HWP + ``powersave``
 ...................
 In this configuration ``intel_pstate`` will set the processor's
 Energy-Performance Preference (EPP) knob (if supported) or its
 Energy-Performance Bias (EPB) knob (otherwise) to whatever value it was
 previously set to via ``sysfs`` (or whatever default value it was
 set to by the platform firmware).  This usually causes the processor's
 internal P-state selection logic to be less performance-focused.
 Active Mode Without HWP
 ~~~~~~~~~~~~~~~~~~~~~~~
 This is the default operation mode for processors that do not support the HWP
 feature.  It also is used by default with the ``intel_pstate=no_hwp`` argument
 in the kernel command line.  However, in this mode ``intel_pstate`` may refuse
 to work with the given processor if it does not recognize it.  [Note that
 ``intel_pstate`` will never refuse to work with any processor with the HWP
 feature enabled.]
 In this mode ``intel_pstate`` registers utilization update callbacks with the
 CPU scheduler in order to run a P-state selection algorithm, either
 ``powersave`` or ``performance``, depending on the ``scaling_cur_freq`` policy
 setting in ``sysfs``.  The current CPU frequency information to be made
 available from the ``scaling_cur_freq`` policy attribute in ``sysfs`` is
 periodically updated by those utilization update callbacks too.
 ``performance``
 ...............
 Without HWP, this P-state selection algorithm is always the same regardless of
 the processor model and platform configuration.
 It selects the maximum P-state it is allowed to use, subject to limits set via
 ``sysfs``, every time the P-state selection computations are carried out by the
 driver's utilization update callback for the given CPU (that does not happen
 more often than every 10 ms), but the hardware configuration will not be changed
 if the new P-state is the same as the current one.
 This is the default P-state selection algorithm if the
 :c:macro:`CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE` kernel configuration option
 is set.
 ``powersave``
 .............
 Without HWP, this P-state selection algorithm generally depends on the
 processor model and/or the system profile setting in the ACPI tables and there
 are two variants of it.
 One of them is used with processors from the Atom line and (regardless of the
 processor model) on platforms with the system profile in the ACPI tables set to
 "mobile" (laptops mostly), "tablet", "appliance PC", "desktop", or
 "workstation".  It is also used with processors supporting the HWP feature if
 that feature has not been enabled (that is, with the ``intel_pstate=no_hwp``
 argument in the kernel command line).  It is similar to the algorithm
 implemented by the generic ``schedutil`` scaling governor except that the
 utilization metric used by it is based on numbers coming from feedback
 registers of the CPU.  It generally selects P-states proportional to the
 current CPU utilization, so it is referred to as the "proportional" algorithm.
 The second variant of the ``powersave`` P-state selection algorithm, used in all
 of the other cases (generally, on processors from the Core line, so it is
 referred to as the "Core" algorithm), is based on the values read from the APERF
 and MPERF feedback registers and the previously requested target P-state.
 It does not really take CPU utilization into account explicitly, but as a rule
 it causes the CPU P-state to ramp up very quickly in response to increased
 utilization which is generally desirable in server environments.
 Regardless of the variant, this algorithm is run by the driver's utilization
 update callback for the given CPU when it is invoked by the CPU scheduler, but
 not more often than every 10 ms (that can be tweaked via ``debugfs`` in `this
 particular case <Tuning Interface in debugfs_>`_).  Like in the ``performance``
 case, the hardware configuration is not touched if the new P-state turns out to
 be the same as the current one.
 This is the default P-state selection algorithm if the
 :c:macro:`CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE` kernel configuration option
 is not set.
 Passive Mode
 ------------
 This mode is used if the ``intel_pstate=passive`` argument is passed to the
 kernel in the command line (it implies the ``intel_pstate=no_hwp`` setting too).
 Like in the active mode without HWP support, in this mode ``intel_pstate`` may
 refuse to work with the given processor if it does not recognize it.
 If the driver works in this mode, the ``scaling_driver`` policy attribute in
 ``sysfs`` for all ``CPUFreq`` policies contains the string "intel_cpufreq".
 Then, the driver behaves like a regular ``CPUFreq`` scaling driver.  That is,
 it is invoked by generic scaling governors when necessary to talk to the
 hardware in order to change the P-state of a CPU (in particular, the
 ``schedutil`` governor can invoke it directly from scheduler context).
 While in this mode, ``intel_pstate`` can be used with all of the (generic)
 scaling governors listed by the ``scaling_available_governors`` policy attribute
 in ``sysfs`` (and the P-state selection algorithms described above are not
 used).  Then, it is responsible for the configuration of policy objects
 corresponding to CPUs and provides the ``CPUFreq`` core (and the scaling
 governors attached to the policy objects) with accurate information on the
 maximum and minimum operating frequencies supported by the hardware (including
 the so-called "turbo" frequency ranges).  In other words, in the passive mode
 the entire range of available P-states is exposed by ``intel_pstate`` to the
 ``CPUFreq`` core.  However, in this mode the driver does not register
 utilization update callbacks with the CPU scheduler and the ``scaling_cur_freq``
 information comes from the ``CPUFreq`` core (and is the last frequency selected
 by the current scaling governor for the given policy).
 .. _turbo:
 Turbo P-states Support
 ======================
 In the majority of cases, the entire range of P-states available to
 ``intel_pstate`` can be divided into two sub-ranges that correspond to
 different types of processor behavior, above and below a boundary that
 will be referred to as the "turbo threshold" in what follows.
 The P-states above the turbo threshold are referred to as "turbo P-states" and
 the whole sub-range of P-states they belong to is referred to as the "turbo
 range".  These names are related to the Turbo Boost technology allowing a
 multicore processor to opportunistically increase the P-state of one or more
 cores if there is enough power to do that and if that is not going to cause the
 thermal envelope of the processor package to be exceeded.
 Specifically, if software sets the P-state of a CPU core within the turbo range
 (that is, above the turbo threshold), the processor is permitted to take over
 performance scaling control for that core and put it into turbo P-states of its
 choice going forward.  However, that permission is interpreted differently by
 different processor generations.  Namely, the Sandy Bridge generation of
 processors will never use any P-states above the last one set by software for
 the given core, even if it is within the turbo range, whereas all of the later
 processor generations will take it as a license to use any P-states from the
 turbo range, even above the one set by software.  In other words, on those
 processors setting any P-state from the turbo range will enable the processor
 to put the given core into all turbo P-states up to and including the maximum
 supported one as it sees fit.
 One important property of turbo P-states is that they are not sustainable.  More
 precisely, there is no guarantee that any CPUs will be able to stay in any of
 those states indefinitely, because the power distribution within the processor
 package may change over time  or the thermal envelope it was designed for might
 be exceeded if a turbo P-state was used for too long.
 In turn, the P-states below the turbo threshold generally are sustainable.  In
 fact, if one of them is set by software, the processor is not expected to change
 it to a lower one unless in a thermal stress or a power limit violation
 situation (a higher P-state may still be used if it is set for another CPU in
 the same package at the same time, for example).
 Some processors allow multiple cores to be in turbo P-states at the same time,
 but the maximum P-state that can be set for them generally depends on the number
 of cores running concurrently.  The maximum turbo P-state that can be set for 3
 cores at the same time usually is lower than the analogous maximum P-state for
 2 cores, which in turn usually is lower than the maximum turbo P-state that can
 be set for 1 core.  The one-core maximum turbo P-state is thus the maximum
 supported one overall.
 The maximum supported turbo P-state, the turbo threshold (the maximum supported
 non-turbo P-state) and the minimum supported P-state are specific to the
 processor model and can be determined by reading the processor's model-specific
 registers (MSRs).  Moreover, some processors support the Configurable TDP
 (Thermal Design Power) feature and, when that feature is enabled, the turbo
 threshold effectively becomes a configurable value that can be set by the
 platform firmware.
 Unlike ``_PSS`` objects in the ACPI tables, ``intel_pstate`` always exposes
 the entire range of available P-states, including the whole turbo range, to the
 ``CPUFreq`` core and (in the passive mode) to generic scaling governors.  This
 generally causes turbo P-states to be set more often when ``intel_pstate`` is
 used relative to ACPI-based CPU performance scaling (see `below <acpi-cpufreq_>`_
 for more information).
 Moreover, since ``intel_pstate`` always knows what the real turbo threshold is
 (even if the Configurable TDP feature is enabled in the processor), its
 ``no_turbo`` attribute in ``sysfs`` (described `below <no_turbo_attr_>`_) should
 work as expected in all cases (that is, if set to disable turbo P-states, it
 always should prevent ``intel_pstate`` from using them).
 Processor Support
 =================
 To handle a given processor ``intel_pstate`` requires a number of different
 pieces of information on it to be known, including:
 * The minimum supported P-state.
 * The maximum supported `non-turbo P-state <turbo_>`_.
 * Whether or not turbo P-states are supported at all.
 * The maximum supported `one-core turbo P-state <turbo_>`_ (if turbo P-states
   are supported).
 * The scaling formula to translate the driver's internal representation
   of P-states into frequencies and the other way around.
 Generally, ways to obtain that information are specific to the processor model
 or family.  Although it often is possible to obtain all of it from the processor
 itself (using model-specific registers), there are cases in which hardware
 manuals need to be consulted to get to it too.
 For this reason, there is a list of supported processors in ``intel_pstate`` and
 the driver initialization will fail if the detected processor is not in that
 list, unless it supports the `HWP feature <Active Mode_>`_.  [The interface to
 obtain all of the information listed above is the same for all of the processors
 supporting the HWP feature, which is why they all are supported by
 ``intel_pstate``.]
 User Space Interface in ``sysfs``
 =================================
 Global Attributes
 -----------------
 ``intel_pstate`` exposes several global attributes (files) in ``sysfs`` to
 control its functionality at the system level.  They are located in the
 ``/sys/devices/system/cpu/cpufreq/intel_pstate/`` directory and affect all
 CPUs.
 Some of them are not present if the ``intel_pstate=per_cpu_perf_limits``
 argument is passed to the kernel in the command line.
 ``max_perf_pct``
 	Maximum P-state the driver is allowed to set in percent of the
 	maximum supported performance level (the highest supported `turbo
 	P-state <turbo_>`_).
 	This attribute will not be exposed if the
 	``intel_pstate=per_cpu_perf_limits`` argument is present in the kernel
 	command line.
 ``min_perf_pct``
 	Minimum P-state the driver is allowed to set in percent of the
 	maximum supported performance level (the highest supported `turbo
 	P-state <turbo_>`_).
 	This attribute will not be exposed if the
 	``intel_pstate=per_cpu_perf_limits`` argument is present in the kernel
 	command line.
 ``num_pstates``
 	Number of P-states supported by the processor (between 0 and 255
 	inclusive) including both turbo and non-turbo P-states (see
 	`Turbo P-states Support`_).
 	The value of this attribute is not affected by the ``no_turbo``
 	setting described `below <no_turbo_attr_>`_.
 	This attribute is read-only.
 ``turbo_pct``
 	Ratio of the `turbo range <turbo_>`_ size to the size of the entire
 	range of supported P-states, in percent.
 	This attribute is read-only.
 .. _no_turbo_attr:
 ``no_turbo``
 	If set (equal to 1), the driver is not allowed to set any turbo P-states
 	(see `Turbo P-states Support`_).  If unset (equalt to 0, which is the
 	default), turbo P-states can be set by the driver.
 	[Note that ``intel_pstate`` does not support the general ``boost``
 	attribute (supported by some other scaling drivers) which is replaced
 	by this one.]
 	This attrubute does not affect the maximum supported frequency value
 	supplied to the ``CPUFreq`` core and exposed via the policy interface,
 	but it affects the maximum possible value of per-policy P-state	limits
 	(see `Interpretation of Policy Attributes`_ below for details).
 .. _status_attr:
 ``status``
 	Operation mode of the driver: "active", "passive" or "off".
 	"active"
 		The driver is functional and in the `active mode
 		<Active Mode_>`_.
 	"passive"
 		The driver is functional and in the `passive mode
 		<Passive Mode_>`_.
 	"off"
 		The driver is not functional (it is not registered as a scaling
 		driver with the ``CPUFreq`` core).
 	This attribute can be written to in order to change the driver's
 	operation mode or to unregister it.  The string written to it must be
 	one of the possible values of it and, if successful, the write will
 	cause the driver to switch over to the operation mode represented by
 	that string - or to be unregistered in the "off" case.  [Actually,
 	switching over from the active mode to the passive mode or the other
 	way around causes the driver to be unregistered and registered again
 	with a different set of callbacks, so all of its settings (the global
 	as well as the per-policy ones) are then reset to their default
 	values, possibly depending on the target operation mode.]
 	That only is supported in some configurations, though (for example, if
 	the `HWP feature is enabled in the processor <Active Mode With HWP_>`_,
 	the operation mode of the driver cannot be changed), and if it is not
 	supported in the current configuration, writes to this attribute with
 	fail with an appropriate error.
 Interpretation of Policy Attributes
 -----------------------------------
 The interpretation of some ``CPUFreq`` policy attributes described in
 :doc:`cpufreq` is special with ``intel_pstate`` as the current scaling driver
 and it generally depends on the driver's `operation mode <Operation Modes_>`_.
 First of all, the values of the ``cpuinfo_max_freq``, ``cpuinfo_min_freq`` and
 ``scaling_cur_freq`` attributes are produced by applying a processor-specific
 multiplier to the internal P-state representation used by ``intel_pstate``.
 Also, the values of the ``scaling_max_freq`` and ``scaling_min_freq``
 attributes are capped by the frequency corresponding to the maximum P-state that
 the driver is allowed to set.
 If the ``no_turbo`` `global attribute <no_turbo_attr_>`_ is set, the driver is
 not allowed to use turbo P-states, so the maximum value of ``scaling_max_freq``
 and ``scaling_min_freq`` is limited to the maximum non-turbo P-state frequency.
 Accordingly, setting ``no_turbo`` causes ``scaling_max_freq`` and
 ``scaling_min_freq`` to go down to that value if they were above it before.
 However, the old values of ``scaling_max_freq`` and ``scaling_min_freq`` will be
 restored after unsetting ``no_turbo``, unless these attributes have been written
 to after ``no_turbo`` was set.
 If ``no_turbo`` is not set, the maximum possible value of ``scaling_max_freq``
 and ``scaling_min_freq`` corresponds to the maximum supported turbo P-state,
 which also is the value of ``cpuinfo_max_freq`` in either case.
 Next, the following policy attributes have special meaning if
 ``intel_pstate`` works in the `active mode <Active Mode_>`_:
 ``scaling_available_governors``
 	List of P-state selection algorithms provided by ``intel_pstate``.
 ``scaling_governor``
 	P-state selection algorithm provided by ``intel_pstate`` currently in
 	use with the given policy.
 ``scaling_cur_freq``
 	Frequency of the average P-state of the CPU represented by the given
 	policy for the time interval between the last two invocations of the
 	driver's utilization update callback by the CPU scheduler for that CPU.
 The meaning of these attributes in the `passive mode <Passive Mode_>`_ is the
 same as for other scaling drivers.
 Additionally, the value of the ``scaling_driver`` attribute for ``intel_pstate``
 depends on the operation mode of the driver.  Namely, it is either
 "intel_pstate" (in the `active mode <Active Mode_>`_) or "intel_cpufreq" (in the
 `passive mode <Passive Mode_>`_).
 Coordination of P-State Limits
 ------------------------------
 ``intel_pstate`` allows P-state limits to be set in two ways: with the help of
 the ``max_perf_pct`` and ``min_perf_pct`` `global attributes
 <Global Attributes_>`_ or via the ``scaling_max_freq`` and ``scaling_min_freq``
 ``CPUFreq`` policy attributes.  The coordination between those limits is based
 on the following rules, regardless of the current operation mode of the driver:
 1. All CPUs are affected by the global limits (that is, none of them can be
    requested to run faster than the global maximum and none of them can be
    requested to run slower than the global minimum).
 2. Each individual CPU is affected by its own per-policy limits (that is, it
    cannot be requested to run faster than its own per-policy maximum and it
    cannot be requested to run slower than its own per-policy minimum).
 3. The global and per-policy limits can be set independently.
 If the `HWP feature is enabled in the processor <Active Mode With HWP_>`_, the
 resulting effective values are written into its registers whenever the limits
 change in order to request its internal P-state selection logic to always set
 P-states within these limits.  Otherwise, the limits are taken into account by
 scaling governors (in the `passive mode <Passive Mode_>`_) and by the driver
 every time before setting a new P-state for a CPU.
 Additionally, if the ``intel_pstate=per_cpu_perf_limits`` command line argument
 is passed to the kernel, ``max_perf_pct`` and ``min_perf_pct`` are not exposed
 at all and the only way to set the limits is by using the policy attributes.
 Energy vs Performance Hints
 ---------------------------
 If ``intel_pstate`` works in the `active mode with the HWP feature enabled
 <Active Mode With HWP_>`_ in the processor, additional attributes are present
 in every ``CPUFreq`` policy directory in ``sysfs``.  They are intended to allow
 user space to help ``intel_pstate`` to adjust the processor's internal P-state
 selection logic by focusing it on performance or on energy-efficiency, or
 somewhere between the two extremes:
 ``energy_performance_preference``
 	Current value of the energy vs performance hint for the given policy
 	(or the CPU represented by it).
 	The hint can be changed by writing to this attribute.
 ``energy_performance_available_preferences``
 	List of strings that can be written to the
 	``energy_performance_preference`` attribute.
 	They represent different energy vs performance hints and should be
 	self-explanatory, except that ``default`` represents whatever hint
 	value was set by the platform firmware.
 Strings written to the ``energy_performance_preference`` attribute are
 internally translated to integer values written to the processor's
 Energy-Performance Preference (EPP) knob (if supported) or its
 Energy-Performance Bias (EPB) knob.
 [Note that tasks may by migrated from one CPU to another by the scheduler's
 load-balancing algorithm and if different energy vs performance hints are
 set for those CPUs, that may lead to undesirable outcomes.  To avoid such
 issues it is better to set the same energy vs performance hint for all CPUs
 or to pin every task potentially sensitive to them to a specific CPU.]
 .. _acpi-cpufreq:
 ``intel_pstate`` vs ``acpi-cpufreq``
 ====================================
 On the majority of systems supported by ``intel_pstate``, the ACPI tables
 provided by the platform firmware contain ``_PSS`` objects returning information
 that can be used for CPU performance scaling (refer to the `ACPI specification`_
 for details on the ``_PSS`` objects and the format of the information returned
 by them).
 The information returned by the ACPI ``_PSS`` objects is used by the
 ``acpi-cpufreq`` scaling driver.  On systems supported by ``intel_pstate``
 the ``acpi-cpufreq`` driver uses the same hardware CPU performance scaling
 interface, but the set of P-states it can use is limited by the ``_PSS``
 output.
 On those systems each ``_PSS`` object returns a list of P-states supported by
 the corresponding CPU which basically is a subset of the P-states range that can
 be used by ``intel_pstate`` on the same system, with one exception: the whole
 `turbo range <turbo_>`_ is represented by one item in it (the topmost one).  By
 convention, the frequency returned by ``_PSS`` for that item is greater by 1 MHz
 than the frequency of the highest non-turbo P-state listed by it, but the
 corresponding P-state representation (following the hardware specification)
 returned for it matches the maximum supported turbo P-state (or is the
 special value 255 meaning essentially "go as high as you can get").
 The list of P-states returned by ``_PSS`` is reflected by the table of
 available frequencies supplied by ``acpi-cpufreq`` to the ``CPUFreq`` core and
 scaling governors and the minimum and maximum supported frequencies reported by
 it come from that list as well.  In particular, given the special representation
 of the turbo range described above, this means that the maximum supported
 frequency reported by ``acpi-cpufreq`` is higher by 1 MHz than the frequency
 of the highest supported non-turbo P-state listed by ``_PSS`` which, of course,
 affects decisions made by the scaling governors, except for ``powersave`` and
 ``performance``.
 For example, if a given governor attempts to select a frequency proportional to
 estimated CPU load and maps the load of 100% to the maximum supported frequency
 (possibly multiplied by a constant), then it will tend to choose P-states below
 the turbo threshold if ``acpi-cpufreq`` is used as the scaling driver, because
 in that case the turbo range corresponds to a small fraction of the frequency
 band it can use (1 MHz vs 1 GHz or more).  In consequence, it will only go to
 the turbo range for the highest loads and the other loads above 50% that might
 benefit from running at turbo frequencies will be given non-turbo P-states
 instead.
 One more issue related to that may appear on systems supporting the
 `Configurable TDP feature <turbo_>`_ allowing the platform firmware to set the
 turbo threshold.  Namely, if that is not coordinated with the lists of P-states
 returned by ``_PSS`` properly, there may be more than one item corresponding to
 a turbo P-state in those lists and there may be a problem with avoiding the
 turbo range (if desirable or necessary).  Usually, to avoid using turbo
 P-states overall, ``acpi-cpufreq`` simply avoids using the topmost state listed
 by ``_PSS``, but that is not sufficient when there are other turbo P-states in
 the list returned by it.
 Apart from the above, ``acpi-cpufreq`` works like ``intel_pstate`` in the
 `passive mode <Passive Mode_>`_, except that the number of P-states it can set
 is limited to the ones listed by the ACPI ``_PSS`` objects.
 Kernel Command Line Options for ``intel_pstate``
 ================================================
 Several kernel command line options can be used to pass early-configuration-time
 parameters to ``intel_pstate`` in order to enforce specific behavior of it.  All
 of them have to be prepended with the ``intel_pstate=`` prefix.
 ``disable``
 	Do not register ``intel_pstate`` as the scaling driver even if the
 	processor is supported by it.
 ``passive``
 	Register ``intel_pstate`` in the `passive mode <Passive Mode_>`_ to
 	start with.
 	This option implies the ``no_hwp`` one described below.
 ``force``
 	Register ``intel_pstate`` as the scaling driver instead of
 	``acpi-cpufreq`` even if the latter is preferred on the given system.
 	This may prevent some platform features (such as thermal controls and
 	power capping) that rely on the availability of ACPI P-states
 	information from functioning as expected, so it should be used with
 	caution.
 	This option does not work with processors that are not supported by
 	``intel_pstate`` and on platforms where the ``pcc-cpufreq`` scaling
 	driver is used instead of ``acpi-cpufreq``.
 ``no_hwp``
 	Do not enable the `hardware-managed P-states (HWP) feature
 	<Active Mode With HWP_>`_ even if it is supported by the processor.
 ``hwp_only``
 	Register ``intel_pstate`` as the scaling driver only if the
 	`hardware-managed P-states (HWP) feature <Active Mode With HWP_>`_ is
 	supported by the processor.
 ``support_acpi_ppc``
 	Take ACPI ``_PPC`` performance limits into account.
 	If the preferred power management profile in the FADT (Fixed ACPI
 	Description Table) is set to "Enterprise Server" or "Performance
 	Server", the ACPI ``_PPC`` limits are taken into account by default
 	and this option has no effect.
 ``per_cpu_perf_limits``
 	Use per-logical-CPU P-State limits (see `Coordination of P-state
 	Limits`_ for details).
 Diagnostics and Tuning
 ======================
 Trace Events
 ------------
 There are two static trace events that can be used for ``intel_pstate``
 diagnostics.  One of them is the ``cpu_frequency`` trace event generally used
 by ``CPUFreq``, and the other one is the ``pstate_sample`` trace event specific
 to ``intel_pstate``.  Both of them are triggered by ``intel_pstate`` only if
 it works in the `active mode <Active Mode_>`_.
 The following sequence of shell commands can be used to enable them and see
 their output (if the kernel is generally configured to support event tracing)::
 # cd /sys/kernel/debug/tracing/
 # echo 1 > events/power/pstate_sample/enable
 # echo 1 > events/power/cpu_frequency/enable
 # cat trace
 gnome-terminal--4510  [001] ..s.  1177.680733: pstate_sample: core_busy=107 scaled=94 from=26 to=26 mperf=1143818 aperf=1230607 tsc=29838618 freq=2474476
 cat-5235  [002] ..s.  1177.681723: cpu_frequency: state=2900000 cpu_id=2
 If ``intel_pstate`` works in the `passive mode <Passive Mode_>`_, the
 ``cpu_frequency`` trace event will be triggered either by the ``schedutil``
 scaling governor (for the policies it is attached to), or by the ``CPUFreq``
 core (for the policies with other scaling governors).
 ``ftrace``
 ----------
 The ``ftrace`` interface can be used for low-level diagnostics of
 ``intel_pstate``.  For example, to check how often the function to set a
 P-state is called, the ``ftrace`` filter can be set to to
 :c:func:`intel_pstate_set_pstate`::
 # cd /sys/kernel/debug/tracing/
 # cat available_filter_functions | grep -i pstate
 intel_pstate_set_pstate
 intel_pstate_cpu_init
 ...
 # echo intel_pstate_set_pstate > set_ftrace_filter
 # echo function > current_tracer
 # cat trace | head -15
 # tracer: function
 #
 # entries-in-buffer/entries-written: 80/80   #P:4
 #
 #                              _-----=> irqs-off
 #                             / _----=> need-resched
 #                            | / _---=> hardirq/softirq
 #                            || / _--=> preempt-depth
 #                            ||| /     delay
 #           TASK-PID   CPU#  ||||    TIMESTAMP  FUNCTION
 #              | |       |   ||||       |         |
             Xorg-3129  [000] ..s.  2537.644844: intel_pstate_set_pstate <-intel_pstate_timer_func
  gnome-terminal--4510  [002] ..s.  2537.649844: intel_pstate_set_pstate <-intel_pstate_timer_func
      gnome-shell-3409  [001] ..s.  2537.650850: intel_pstate_set_pstate <-intel_pstate_timer_func
           <idle>-0     [000] ..s.  2537.654843: intel_pstate_set_pstate <-intel_pstate_timer_func
 Tuning Interface in ``debugfs``
 -------------------------------
 The ``powersave`` algorithm provided by ``intel_pstate`` for `the Core line of
 processors in the active mode <powersave_>`_ is based on a `PID controller`_
 whose parameters were chosen to address a number of different use cases at the
 same time.  However, it still is possible to fine-tune it to a specific workload
 and the ``debugfs`` interface under ``/sys/kernel/debug/pstate_snb/`` is
 provided for this purpose.  [Note that the ``pstate_snb`` directory will be
 present only if the specific P-state selection algorithm matching the interface
 in it actually is in use.]
 The following files present in that directory can be used to modify the PID
 controller parameters at run time:
 | ``deadband``
 | ``d_gain_pct``
 | ``i_gain_pct``
 | ``p_gain_pct``
 | ``sample_rate_ms``
 | ``setpoint``
 Note, however, that achieving desirable results this way generally requires
 expert-level understanding of the power vs performance tradeoff, so extra care
 is recommended when attempting to do that.
 .. _LCEU2015: http://events.linuxfoundation.org/sites/events/files/slides/LinuxConEurope_2015.pdf
 .. _SDM: http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-system-programming-manual-325384.html
 .. _ACPI specification: http://www.uefi.org/sites/default/files/resources/ACPI_6_1.pdf
 .. _PID controller: https://en.wikipedia.org/wiki/PID_controller
--- a/Documentation/cpu-freq/intel-pstate.txt
+++ b/Documentation/cpu-freq/intel-pstate.txt
@ -1,281 +0,0 @@
 Intel P-State driver
 --------------------
 This driver provides an interface to control the P-State selection for the
 SandyBridge+ Intel processors.
 The following document explains P-States:
 http://events.linuxfoundation.org/sites/events/files/slides/LinuxConEurope_2015.pdf
 As stated in the document, P-State doesn’t exactly mean a frequency. However, for
 the sake of the relationship with cpufreq, P-State and frequency are used
 interchangeably.
 Understanding the cpufreq core governors and policies are important before
 discussing more details about the Intel P-State driver. Based on what callbacks
 a cpufreq driver provides to the cpufreq core, it can support two types of
 drivers:
 - with target_index() callback: In this mode, the drivers using cpufreq core
 simply provide the minimum and maximum frequency limits and an additional
 interface target_index() to set the current frequency. The cpufreq subsystem
 has a number of scaling governors ("performance", "powersave", "ondemand",
 etc.). Depending on which governor is in use, cpufreq core will call for
 transitions to a specific frequency using target_index() callback.
 - setpolicy() callback: In this mode, drivers do not provide target_index()
 callback, so cpufreq core can't request a transition to a specific frequency.
 The driver provides minimum and maximum frequency limits and callbacks to set a
 policy. The policy in cpufreq sysfs is referred to as the "scaling governor".
 The cpufreq core can request the driver to operate in any of the two policies:
 "performance" and "powersave". The driver decides which frequency to use based
 on the above policy selection considering minimum and maximum frequency limits.
 The Intel P-State driver falls under the latter category, which implements the
 setpolicy() callback. This driver decides what P-State to use based on the
 requested policy from the cpufreq core. If the processor is capable of
 selecting its next P-State internally, then the driver will offload this
 responsibility to the processor (aka HWP: Hardware P-States). If not, the
 driver implements algorithms to select the next P-State.
 Since these policies are implemented in the driver, they are not same as the
 cpufreq scaling governors implementation, even if they have the same name in
 the cpufreq sysfs (scaling_governors). For example the "performance" policy is
 similar to cpufreq’s "performance" governor, but "powersave" is completely
 different than the cpufreq "powersave" governor. The strategy here is similar
 to cpufreq "ondemand", where the requested P-State is related to the system load.
 Sysfs Interface
 In addition to the frequency-controlling interfaces provided by the cpufreq
 core, the driver provides its own sysfs files to control the P-State selection.
 These files have been added to /sys/devices/system/cpu/intel_pstate/.
 Any changes made to these files are applicable to all CPUs (even in a
 multi-package system, Refer to later section on placing "Per-CPU limits").
      max_perf_pct: Limits the maximum P-State that will be requested by
      the driver. It states it as a percentage of the available performance. The
      available (P-State) performance may be reduced by the no_turbo
      setting described below.
      min_perf_pct: Limits the minimum P-State that will be requested by
      the driver. It states it as a percentage of the max (non-turbo)
      performance level.
      no_turbo: Limits the driver to selecting P-State below the turbo
      frequency range.
      turbo_pct: Displays the percentage of the total performance that
      is supported by hardware that is in the turbo range. This number
      is independent of whether turbo has been disabled or not.
      num_pstates: Displays the number of P-States that are supported
      by hardware. This number is independent of whether turbo has
      been disabled or not.
 For example, if a system has these parameters:
 	Max 1 core turbo ratio: 0x21 (Max 1 core ratio is the maximum P-State)
 	Max non turbo ratio: 0x17
 	Minimum ratio : 0x08 (Here the ratio is called max efficiency ratio)
 Sysfs will show :
 	max_perf_pct:100, which corresponds to 1 core ratio
 	min_perf_pct:24, max_efficiency_ratio / max 1 Core ratio
 	no_turbo:0, turbo is not disabled
 	num_pstates:26 = (max 1 Core ratio - Max Efficiency Ratio + 1)
 	turbo_pct:39 = (max 1 core ratio - max non turbo ratio) / num_pstates
 Refer to "Intel® 64 and IA-32 Architectures Software Developer’s Manual
 Volume 3: System Programming Guide" to understand ratios.
 There is one more sysfs attribute in /sys/devices/system/cpu/intel_pstate/
 that can be used for controlling the operation mode of the driver:
      status: Three settings are possible:
      "off"     - The driver is not in use at this time.
      "active"  - The driver works as a P-state governor (default).
      "passive" - The driver works as a regular cpufreq one and collaborates
                  with the generic cpufreq governors (it sets P-states as
                  requested by those governors).
      The current setting is returned by reads from this attribute.  Writing one
      of the above strings to it changes the operation mode as indicated by that
      string, if possible.  If HW-managed P-states (HWP) are enabled, it is not
      possible to change the driver's operation mode and attempts to write to
      this attribute will fail.
 cpufreq sysfs for Intel P-State
 Since this driver registers with cpufreq, cpufreq sysfs is also presented.
 There are some important differences, which need to be considered.
 scaling_cur_freq: This displays the real frequency which was used during
 the last sample period instead of what is requested. Some other cpufreq driver,
 like acpi-cpufreq, displays what is requested (Some changes are on the
 way to fix this for acpi-cpufreq driver). The same is true for frequencies
 displayed at /proc/cpuinfo.
 scaling_governor: This displays current active policy. Since each CPU has a
 cpufreq sysfs, it is possible to set a scaling governor to each CPU. But this
 is not possible with Intel P-States, as there is one common policy for all
 CPUs. Here, the last requested policy will be applicable to all CPUs. It is
 suggested that one use the cpupower utility to change policy to all CPUs at the
 same time.
 scaling_setspeed: This attribute can never be used with Intel P-State.
 scaling_max_freq/scaling_min_freq: This interface can be used similarly to
 the max_perf_pct/min_perf_pct of Intel P-State sysfs. However since frequencies
 are converted to nearest possible P-State, this is prone to rounding errors.
 This method is not preferred to limit performance.
 affected_cpus: Not used
 related_cpus: Not used
 For contemporary Intel processors, the frequency is controlled by the
 processor itself and the P-State exposed to software is related to
 performance levels.  The idea that frequency can be set to a single
 frequency is fictional for Intel Core processors. Even if the scaling
 driver selects a single P-State, the actual frequency the processor
 will run at is selected by the processor itself.
 Per-CPU limits
 The kernel command line option "intel_pstate=per_cpu_perf_limits" forces
 the intel_pstate driver to use per-CPU performance limits.  When it is set,
 the sysfs control interface described above is subject to limitations.
 - The following controls are not available for both read and write
 	/sys/devices/system/cpu/intel_pstate/max_perf_pct
 	/sys/devices/system/cpu/intel_pstate/min_perf_pct
 - The following controls can be used to set performance limits, as far as the
 architecture of the processor permits:
 	/sys/devices/system/cpu/cpu*/cpufreq/scaling_max_freq
 	/sys/devices/system/cpu/cpu*/cpufreq/scaling_min_freq
 	/sys/devices/system/cpu/cpu*/cpufreq/scaling_governor
 - User can still observe turbo percent and number of P-States from
 	/sys/devices/system/cpu/intel_pstate/turbo_pct
 	/sys/devices/system/cpu/intel_pstate/num_pstates
 - User can read write system wide turbo status
 	/sys/devices/system/cpu/no_turbo
 Support of energy performance hints
 It is possible to provide hints to the HWP algorithms in the processor
 to be more performance centric to more energy centric. When the driver
 is using HWP, two additional cpufreq sysfs attributes are presented for
 each logical CPU.
 These attributes are:
 	- energy_performance_available_preferences
 	- energy_performance_preference
 To get list of supported hints:
 $ cat energy_performance_available_preferences
    default performance balance_performance balance_power power
 The current preference can be read or changed via cpufreq sysfs
 attribute "energy_performance_preference". Reading from this attribute
 will display current effective setting. User can write any of the valid
 preference string to this attribute. User can always restore to power-on
 default by writing "default".
 Since threads can migrate to different CPUs, this is possible that the
 new CPU may have different energy performance preference than the previous
 one. To avoid such issues, either threads can be pinned to specific CPUs
 or set the same energy performance preference value to all CPUs.
 Tuning Intel P-State driver
 When the performance can be tuned using PID (Proportional Integral
 Derivative) controller, debugfs files are provided for adjusting performance.
 They are presented under:
 /sys/kernel/debug/pstate_snb/
 The PID tunable parameters are:
      deadband
      d_gain_pct
      i_gain_pct
      p_gain_pct
      sample_rate_ms
      setpoint
 To adjust these parameters, some understanding of driver implementation is
 necessary. There are some tweeks described here, but be very careful. Adjusting
 them requires expert level understanding of power and performance relationship.
 These limits are only useful when the "powersave" policy is active.
 -To make the system more responsive to load changes, sample_rate_ms can
 be adjusted  (current default is 10ms).
 -To make the system use higher performance, even if the load is lower, setpoint
 can be adjusted to a lower number. This will also lead to faster ramp up time
 to reach the maximum P-State.
 If there are no derivative and integral coefficients, The next P-State will be
 equal to:
 	current P-State - ((setpoint - current cpu load) * p_gain_pct)
 For example, if the current PID parameters are (Which are defaults for the core
 processors like SandyBridge):
      deadband = 0
      d_gain_pct = 0
      i_gain_pct = 0
      p_gain_pct = 20
      sample_rate_ms = 10
      setpoint = 97
 If the current P-State = 0x08 and current load = 100, this will result in the
 next P-State = 0x08 - ((97 - 100) * 0.2) = 8.6 (rounded to 9). Here the P-State
 goes up by only 1. If during next sample interval the current load doesn't
 change and still 100, then P-State goes up by one again. This process will
 continue as long as the load is more than the setpoint until the maximum P-State
 is reached.
 For the same load at setpoint = 60, this will result in the next P-State
 = 0x08 - ((60 - 100) * 0.2) = 16
 So by changing the setpoint from 97 to 60, there is an increase of the
 next P-State from 9 to 16. So this will make processor execute at higher
 P-State for the same CPU load. If the load continues to be more than the
 setpoint during next sample intervals, then P-State will go up again till the
 maximum P-State is reached. But the ramp up time to reach the maximum P-State
 will be much faster when the setpoint is 60 compared to 97.
 Debugging Intel P-State driver
 Event tracing
 To debug P-State transition, the Linux event tracing interface can be used.
 There are two specific events, which can be enabled (Provided the kernel
 configs related to event tracing are enabled).
 # cd /sys/kernel/debug/tracing/
 # echo 1 > events/power/pstate_sample/enable
 # echo 1 > events/power/cpu_frequency/enable
 # cat trace
 gnome-terminal--4510  [001] ..s.  1177.680733: pstate_sample: core_busy=107
 	scaled=94 from=26 to=26 mperf=1143818 aperf=1230607 tsc=29838618
 		freq=2474476
 cat-5235  [002] ..s.  1177.681723: cpu_frequency: state=2900000 cpu_id=2
 Using ftrace
 If function level tracing is required, the Linux ftrace interface can be used.
 For example if we want to check how often a function to set a P-State is
 called, we can set ftrace filter to intel_pstate_set_pstate.
 # cd /sys/kernel/debug/tracing/
 # cat available_filter_functions | grep -i pstate
 intel_pstate_set_pstate
 intel_pstate_cpu_init
 ...
 # echo intel_pstate_set_pstate > set_ftrace_filter
 # echo function > current_tracer
 # cat trace | head -15
 # tracer: function
 #
 # entries-in-buffer/entries-written: 80/80   #P:4
 #
 #                              _-----=> irqs-off
 #                             / _----=> need-resched
 #                            | / _---=> hardirq/softirq
 #                            || / _--=> preempt-depth
 #                            ||| /     delay
 #           TASK-PID   CPU#  ||||    TIMESTAMP  FUNCTION
 #              | |       |   ||||       |         |
            Xorg-3129  [000] ..s.  2537.644844: intel_pstate_set_pstate <-intel_pstate_timer_func
 gnome-terminal--4510  [002] ..s.  2537.649844: intel_pstate_set_pstate <-intel_pstate_timer_func
     gnome-shell-3409  [001] ..s.  2537.650850: intel_pstate_set_pstate <-intel_pstate_timer_func
          <idle>-0     [000] ..s.  2537.654843: intel_pstate_set_pstate <-intel_pstate_timer_func
--- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
@ -36,7 +36,7 @@ Optional properties:
                control gpios
 - threshold:   allows setting the "click"-threshold in the range
-                from 20 to 80.
+                from 0 to 80.
 - gain:        allows setting the sensitivity in the range from 0 to
                31. Note that lower values indicate higher
--- a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
+++ b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt
@ -16,6 +16,11 @@ Required properties:
 - reg:                  Base address of PMIC on Hi6220 SoC.
 - interrupt-controller: Hi655x has internal IRQs (has own IRQ domain).
 - pmic-gpios:           The GPIO used by PMIC IRQ.
 - #clock-cells:		From common clock binding; shall be set to 0
 Optional properties:
 - clock-output-names: From common clock binding to override the
  default output clock name
 Example:
 	pmic: pmic@f8000000 {
@ -24,4 +29,5 @@ Example:
 		interrupt-controller;
 		#interrupt-cells = <2>;
 		pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 		#clock-cells = <0>;
 	}
--- a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt
+++ b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt
@ -18,6 +18,8 @@ Optional properties:
  "ext_clock" (External clock provided to the card).
 - post-power-on-delay-ms : Delay in ms after powering the card and
 	de-asserting the reset-gpios (if any)
 - power-off-delay-us : Delay in us after asserting the reset-gpios (if any)
 	during power off of the card.
 Example:
--- a/Documentation/devicetree/bindings/net/dsa/marvell.txt
+++ b/Documentation/devicetree/bindings/net/dsa/marvell.txt
@ -26,6 +26,10 @@ Optional properties:
 - interrupt-controller	: Indicates the switch is itself an interrupt
 			  controller. This is used for the PHY interrupts.
 #interrupt-cells = <2>	: Controller uses two cells, number and flag
 - eeprom-length		: Set to the length of an EEPROM connected to the
 			  switch. Must be set if the switch can not detect
 			  the presence and/or size of a connected EEPROM,
 			  otherwise optional.
 - mdio			: Container of PHY and devices on the switches MDIO
 			  bus.
 - mdio?		: Container of PHYs and devices on the external MDIO
--- a/Documentation/devicetree/bindings/net/fsl-fec.txt
+++ b/Documentation/devicetree/bindings/net/fsl-fec.txt
@ -15,6 +15,10 @@ Optional properties:
 - phy-reset-active-high : If present then the reset sequence using the GPIO
  specified in the "phy-reset-gpios" property is reversed (H=reset state,
  L=operation state).
 - phy-reset-post-delay : Post reset delay in milliseconds. If present then
  a delay of phy-reset-post-delay milliseconds will be observed after the
  phy-reset-gpios has been toggled. Can be omitted thus no delay is
  observed. Delay is in range of 1ms to 1000ms. Other delays are invalid.
 - phy-supply : regulator that powers the Ethernet PHY.
 - phy-handle : phandle to the PHY device connected to this device.
 - fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
@ -247,7 +247,6 @@ bias-bus-hold		- latch weakly
 bias-pull-up		- pull up the pin
 bias-pull-down		- pull down the pin
 bias-pull-pin-default	- use pin-default pull state
 bi-directional		- pin supports simultaneous input/output operations
 drive-push-pull		- drive actively high and low
 drive-open-drain	- drive with open drain
 drive-open-source	- drive with open source
@ -260,7 +259,6 @@ input-debounce		- debounce mode with debound time X
 power-source		- select between different power supplies
 low-power-enable	- enable low power mode
 low-power-disable	- disable low power mode
 output-enable		- enable output on pin regardless of output value
 output-low		- set the pin to output mode with low level
 output-high		- set the pin to output mode with high level
 slew-rate		- set the slew rate
--- a/Documentation/devicetree/bindings/staging/ion/hi6220-ion.txt
+++ b/Documentation/devicetree/bindings/staging/ion/hi6220-ion.txt
@ -1,31 +0,0 @@
 Hi6220 SoC ION
 ===================================================================
 Required properties:
 - compatible : "hisilicon,hi6220-ion"
 - list of the ION heaps
 	- heap name : maybe heap_sys_user@0
 	- heap id   : id should be unique in the system.
 	- heap base : base ddr address of the heap,0 means that
 	it is dynamic.
 	- heap size : memory size and 0 means it is dynamic.
 	- heap type : the heap type of the heap, please also
 	see the define in ion.h(drivers/staging/android/uapi/ion.h)
 -------------------------------------------------------------------
 Example:
 	hi6220-ion {
 		compatible = "hisilicon,hi6220-ion";
 		heap_sys_user@0 {
 			heap-name = "sys_user";
 			heap-id   = <0x0>;
 			heap-base = <0x0>;
 			heap-size = <0x0>;
 			heap-type = "ion_system";
 		};
 		heap_sys_contig@0 {
 			heap-name = "sys_contig";
 			heap-id   = <0x1>;
 			heap-base = <0x0>;
 			heap-size = <0x0>;
 			heap-type = "ion_system_contig";
 		};
 	};
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@ -10,6 +10,7 @@ Required properties:
  - "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
  - "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
  - "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
  - "amlogic,meson8-usb": The DWC2 USB controller instance in Amlogic Meson8 SoCs;
  - "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs;
  - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
  - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs;
--- a/Documentation/input/devices/edt-ft5x06.rst
+++ b/Documentation/input/devices/edt-ft5x06.rst
@ -15,7 +15,7 @@ It has been tested with the following devices:
 The driver allows configuration of the touch screen via a set of sysfs files:
 /sys/class/input/eventX/device/device/threshold:
-    allows setting the "click"-threshold in the range from 20 to 80.
+    allows setting the "click"-threshold in the range from 0 to 80.
 /sys/class/input/eventX/device/device/gain:
    allows setting the sensitivity in the range from 0 to 31. Note that
--- a/Documentation/networking/dpaa.txt
+++ b/Documentation/networking/dpaa.txt
@ -0,0 +1,194 @@
 The QorIQ DPAA Ethernet Driver
 ==============================
 Authors:
 Madalin Bucur <madalin.bucur@nxp.com>
 Camelia Groza <camelia.groza@nxp.com>
 Contents
 ========
 	- DPAA Ethernet Overview
 	- DPAA Ethernet Supported SoCs
 	- Configuring DPAA Ethernet in your kernel
 	- DPAA Ethernet Frame Processing
 	- DPAA Ethernet Features
 	- Debugging
 DPAA Ethernet Overview
 ======================
 DPAA stands for Data Path Acceleration Architecture and it is a
 set of networking acceleration IPs that are available on several
 generations of SoCs, both on PowerPC and ARM64.
 The Freescale DPAA architecture consists of a series of hardware blocks
 that support Ethernet connectivity. The Ethernet driver depends upon the
 following drivers in the Linux kernel:
 - Peripheral Access Memory Unit (PAMU) (* needed only for PPC platforms)
    drivers/iommu/fsl_*
 - Frame Manager (FMan)
    drivers/net/ethernet/freescale/fman
 - Queue Manager (QMan), Buffer Manager (BMan)
    drivers/soc/fsl/qbman
 A simplified view of the dpaa_eth interfaces mapped to FMan MACs:
  dpaa_eth       /eth0\     ...       /ethN\
  driver        |      |             |      |
  -------------   ----   -----------   ----   -------------
       -Ports  / Tx  Rx \    ...    / Tx  Rx \
  FMan        |          |         |          |
       -MACs  |   MAC0   |         |   MACN   |
             /   dtsec0   \  ...  /   dtsecN   \ (or tgec)
            /              \     /              \(or memac)
  ---------  --------------  ---  --------------  ---------
      FMan, FMan Port, FMan SP, FMan MURAM drivers
  ---------------------------------------------------------
      FMan HW blocks: MURAM, MACs, Ports, SP
  ---------------------------------------------------------
 The dpaa_eth relation to the QMan, BMan and FMan:
              ________________________________
  dpaa_eth   /            eth0                \
  driver    /                                  \
  ---------   -^-   -^-   -^-   ---    ---------
  QMan driver / \   / \   / \  \   /  | BMan    |
             |Rx | |Rx | |Tx | |Tx |  | driver  |
  ---------  |Dfl| |Err| |Cnf| |FQs|  |         |
  QMan HW    |FQ | |FQ | |FQs| |   |  |         |
             /   \ /   \ /   \  \ /   |         |
  ---------   ---   ---   ---   -v-    ---------
            |        FMan QMI         |         |
            | FMan HW       FMan BMI  | BMan HW |
              -----------------------   --------
 where the acronyms used above (and in the code) are:
 DPAA = Data Path Acceleration Architecture
 FMan = DPAA Frame Manager
 QMan = DPAA Queue Manager
 BMan = DPAA Buffers Manager
 QMI = QMan interface in FMan
 BMI = BMan interface in FMan
 FMan SP = FMan Storage Profiles
 MURAM = Multi-user RAM in FMan
 FQ = QMan Frame Queue
 Rx Dfl FQ = default reception FQ
 Rx Err FQ = Rx error frames FQ
 Tx Cnf FQ = Tx confirmation FQs
 Tx FQs = transmission frame queues
 dtsec = datapath three speed Ethernet controller (10/100/1000 Mbps)
 tgec = ten gigabit Ethernet controller (10 Gbps)
 memac = multirate Ethernet MAC (10/100/1000/10000)
 DPAA Ethernet Supported SoCs
 ============================
 The DPAA drivers enable the Ethernet controllers present on the following SoCs:
 # PPC
 P1023
 P2041
 P3041
 P4080
 P5020
 P5040
 T1023
 T1024
 T1040
 T1042
 T2080
 T4240
 B4860
 # ARM
 LS1043A
 LS1046A
 Configuring DPAA Ethernet in your kernel
 ========================================
 To enable the DPAA Ethernet driver, the following Kconfig options are required:
 # common for arch/arm64 and arch/powerpc platforms
 CONFIG_FSL_DPAA=y
 CONFIG_FSL_FMAN=y
 CONFIG_FSL_DPAA_ETH=y
 CONFIG_FSL_XGMAC_MDIO=y
 # for arch/powerpc only
 CONFIG_FSL_PAMU=y
 # common options needed for the PHYs used on the RDBs
 CONFIG_VITESSE_PHY=y
 CONFIG_REALTEK_PHY=y
 CONFIG_AQUANTIA_PHY=y
 DPAA Ethernet Frame Processing
 ==============================
 On Rx, buffers for the incoming frames are retrieved from one of the three
 existing buffers pools. The driver initializes and seeds these, each with
 buffers of different sizes: 1KB, 2KB and 4KB.
 On Tx, all transmitted frames are returned to the driver through Tx
 confirmation frame queues. The driver is then responsible for freeing the
 buffers. In order to do this properly, a backpointer is added to the buffer
 before transmission that points to the skb. When the buffer returns to the
 driver on a confirmation FQ, the skb can be correctly consumed.
 DPAA Ethernet Features
 ======================
 Currently the DPAA Ethernet driver enables the basic features required for
 a Linux Ethernet driver. The support for advanced features will be added
 gradually.
 The driver has Rx and Tx checksum offloading for UDP and TCP. Currently the Rx
 checksum offload feature is enabled by default and cannot be controlled through
 ethtool.
 The driver has support for multiple prioritized Tx traffic classes. Priorities
 range from 0 (lowest) to 3 (highest). These are mapped to HW workqueues with
 strict priority levels. Each traffic class contains NR_CPU TX queues. By
 default, only one traffic class is enabled and the lowest priority Tx queues
 are used. Higher priority traffic classes can be enabled with the mqprio
 qdisc. For example, all four traffic classes are enabled on an interface with
 the following command. Furthermore, skb priority levels are mapped to traffic
 classes as follows:
 	* priorities 0 to 3 - traffic class 0 (low priority)
 	* priorities 4 to 7 - traffic class 1 (medium-low priority)
 	* priorities 8 to 11 - traffic class 2 (medium-high priority)
 	* priorities 12 to 15 - traffic class 3 (high priority)
 tc qdisc add dev <int> root handle 1: \
 	 mqprio num_tc 4 map 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 hw 1
 Debugging
 =========
 The following statistics are exported for each interface through ethtool:
 	- interrupt count per CPU
 	- Rx packets count per CPU
 	- Tx packets count per CPU
 	- Tx confirmed packets count per CPU
 	- Tx S/G frames count per CPU
 	- Tx error count per CPU
 	- Rx error count per CPU
 	- Rx error count per type
 	- congestion related statistics:
 		- congestion status
 		- time spent in congestion
 		- number of time the device entered congestion
 		- dropped packets count per cause
 The driver also exports the following information in sysfs:
 	- the FQ IDs for each FQ type
 	/sys/devices/platform/dpaa-ethernet.0/net/<int>/fqids
 	- the IDs of the buffer pools in use
 	/sys/devices/platform/dpaa-ethernet.0/net/<int>/bpids
--- a/Documentation/networking/tcp.txt
+++ b/Documentation/networking/tcp.txt
@ -1,7 +1,7 @@
 TCP protocol
 ============
-Last updated: 9 February 2008
+Last updated: 3 June 2017
 Contents
 ========
@ -29,18 +29,19 @@ As of 2.6.13, Linux supports pluggable congestion control algorithms.
 A congestion control mechanism can be registered through functions in
 tcp_cong.c. The functions used by the congestion control mechanism are
 registered via passing a tcp_congestion_ops struct to
-tcp_register_congestion_control. As a minimum name, ssthresh,
+tcp_register_congestion_control. As a minimum, the congestion control
-cong_avoid must be valid.
+mechanism must provide a valid name and must implement either ssthresh,
 cong_avoid and undo_cwnd hooks or the "omnipotent" cong_control hook.
 Private data for a congestion control mechanism is stored in tp->ca_priv.
 tcp_ca(tp) returns a pointer to this space.  This is preallocated space - it
 is important to check the size of your private data will fit this space, or
-alternatively space could be allocated elsewhere and a pointer to it could
+alternatively, space could be allocated elsewhere and a pointer to it could
 be stored here.
 There are three kinds of congestion control algorithms currently: The
 simplest ones are derived from TCP reno (highspeed, scalable) and just
-provide an alternative the congestion window calculation. More complex
+provide an alternative congestion window calculation. More complex
 ones like BIC try to look at other events to provide better
 heuristics.  There are also round trip time based algorithms like
 Vegas and Westwood+.
@ -49,21 +50,15 @@ Good TCP congestion control is a complex problem because the algorithm
 needs to maintain fairness and performance. Please review current
 research and RFC's before developing new modules.
-The method that is used to determine which congestion control mechanism is
+The default congestion control mechanism is chosen based on the
-determined by the setting of the sysctl net.ipv4.tcp_congestion_control.
+DEFAULT_TCP_CONG Kconfig parameter. If you really want a particular default
-The default congestion control will be the last one registered (LIFO);
+value then you can set it using sysctl net.ipv4.tcp_congestion_control. The
-so if you built everything as modules, the default will be reno. If you
+module will be autoloaded if needed and you will get the expected protocol. If
-build with the defaults from Kconfig, then CUBIC will be builtin (not a
+you ask for an unknown congestion method, then the sysctl attempt will fail.
 module) and it will end up the default.
-If you really want a particular default value then you will need
+If you remove a TCP congestion control module, then you will get the next
 to set it with the sysctl.  If you use a sysctl, the module will be autoloaded
 if needed and you will get the expected protocol. If you ask for an
 unknown congestion method, then the sysctl attempt will fail.
 If you remove a tcp congestion control module, then you will get the next
 available one. Since reno cannot be built as a module, and cannot be
-deleted, it will always be available.
+removed, it will always be available.
 How the new TCP output machine [nyi] works.
 ===========================================
--- a/Documentation/sound/hd-audio/models.rst
+++ b/Documentation/sound/hd-audio/models.rst
@ -16,6 +16,8 @@ ALC880
    6-jack in back, 2-jack in front
 6stack-digout
    6-jack with a SPDIF out
 6stack-automute
    6-jack with headphone jack detection
 ALC260
 ======
@ -62,6 +64,8 @@ lenovo-dock
    Enables docking station I/O for some Lenovos
 hp-gpio-led
    GPIO LED support on HP laptops
 hp-dock-gpio-mic1-led
    HP dock with mic LED support
 dell-headset-multi
    Headset jack, which can also be used as mic-in
 dell-headset-dock
@ -72,6 +76,12 @@ alc283-sense-combo
    Combo jack sensing on ALC283
 tpt440-dock
    Pin configs for Lenovo Thinkpad Dock support
 tpt440
    Lenovo Thinkpad T440s setup
 tpt460
    Lenovo Thinkpad T460/560 setup
 dual-codecs
    Lenovo laptops with dual codecs
 ALC66x/67x/892
 ==============
@ -97,6 +107,8 @@ inv-dmic
    Inverted internal mic workaround
 dell-headset-multi
    Headset jack, which can also be used as mic-in
 dual-codecs
    Lenovo laptops with dual codecs
 ALC680
 ======
@ -114,6 +126,8 @@ inv-dmic
    Inverted internal mic workaround
 no-primary-hp
    VAIO Z/VGC-LN51JGB workaround (for fixed speaker DAC)
 dual-codecs
    ALC1220 dual codecs for Gaming mobos
 ALC861/660
 ==========
@ -206,65 +220,47 @@ auto
 Conexant 5045
 =============
-laptop-hpsense
+cap-mix-amp
-    Laptop with HP sense (old model laptop)
+    Fix max input level on mixer widget
-laptop-micsense
+toshiba-p105
-    Laptop with Mic sense (old model fujitsu)
+    Toshiba P105 quirk
-laptop-hpmicsense
+hp-530
-    Laptop with HP and Mic senses
+    HP 530 quirk
 benq
    Benq R55E
 laptop-hp530
    HP 530 laptop
 test
    for testing/debugging purpose, almost all controls can be
    adjusted.  Appearing only when compiled with $CONFIG_SND_DEBUG=y
 Conexant 5047
 =============
-laptop
+cap-mix-amp
-    Basic Laptop config 
+    Fix max input level on mixer widget
 laptop-hp
    Laptop config for some HP models (subdevice 30A5)
 laptop-eapd
    Laptop config with EAPD support
 test
    for testing/debugging purpose, almost all controls can be
    adjusted.  Appearing only when compiled with $CONFIG_SND_DEBUG=y
 Conexant 5051
 =============
-laptop
+lenovo-x200
-    Basic Laptop config (default)
+    Lenovo X200 quirk
 hp
    HP Spartan laptop
 hp-dv6736
    HP dv6736
 hp-f700
    HP Compaq Presario F700
 ideapad
    Lenovo IdeaPad laptop
 toshiba
    Toshiba Satellite M300
 Conexant 5066
 =============
-laptop
+stereo-dmic
-    Basic Laptop config (default)
+    Workaround for inverted stereo digital mic
-hp-laptop
+gpio1
-    HP laptops, e g G60
+    Enable GPIO1 pin
-asus
+headphone-mic-pin
-    Asus K52JU, Lenovo G560
+    Enable headphone mic NID 0x18 without detection
-dell-laptop
+tp410
-    Dell laptops
+    Thinkpad T400 & co quirks
 dell-vostro
    Dell Vostro
 olpc-xo-1_5
    OLPC XO 1.5
 ideapad
    Lenovo IdeaPad U150
 thinkpad
-    Lenovo Thinkpad
+    Thinkpad mute/mic LED quirk
 lemote-a1004
    Lemote A1004 quirk
 lemote-a1205
    Lemote A1205 quirk
 olpc-xo
    OLPC XO quirk
 mute-led-eapd
    Mute LED control via EAPD
 hp-dock
    HP dock support
 mute-led-gpio
    Mute LED control via GPIO
 STAC9200
 ========
@ -444,6 +440,8 @@ dell-eq
    Dell desktops/laptops
 alienware
    Alienware M17x
 asus-mobo
    Pin configs for ASUS mobo with 5.1/SPDIF out
 auto
    BIOS setup (default)
@ -477,6 +475,8 @@ hp-envy-ts-bass
    Pin fixup for HP Envy TS bass speaker (NID 0x10)
 hp-bnb13-eq
    Hardware equalizer setup for HP laptops
 hp-envy-ts-bass
    HP Envy TS bass support
 auto
    BIOS setup (default)
@ -496,10 +496,22 @@ auto
 Cirrus Logic CS4206/4207
 ========================
 mbp53
    MacBook Pro 5,3
 mbp55
    MacBook Pro 5,5
 imac27
    IMac 27 Inch
 imac27_122
    iMac 12,2
 apple
    Generic Apple quirk
 mbp101
    MacBookPro 10,1
 mbp81
    MacBookPro 8,1
 mba42
    MacBookAir 4,2
 auto
    BIOS setup (default)
@ -509,6 +521,10 @@ mba6
    MacBook Air 6,1 and 6,2
 gpio0
    Enable GPIO 0 amp
 mbp11
    MacBookPro 11,2
 macmini
    MacMini 7,1
 auto
    BIOS setup (default)
--- a/Documentation/usb/typec.rst
+++ b/Documentation/usb/typec.rst
@ -114,8 +114,7 @@ the details during registration. The class offers the following API for
 registering/unregistering cables and their plugs:
 .. kernel-doc:: drivers/usb/typec/typec.c
-   :functions: typec_register_cable typec_unregister_cable typec_register_plug
+   :functions: typec_register_cable typec_unregister_cable typec_register_plug typec_unregister_plug
   typec_unregister_plug
 The class will provide a handle to struct typec_cable and struct typec_plug if
 the registration is successful, or NULL if it isn't.
@ -137,8 +136,7 @@ during connection of a partner or cable, the port driver must use the following
 APIs to report it to the class:
 .. kernel-doc:: drivers/usb/typec/typec.c
-   :functions: typec_set_data_role typec_set_pwr_role typec_set_vconn_role
+   :functions: typec_set_data_role typec_set_pwr_role typec_set_vconn_role typec_set_pwr_opmode
   typec_set_pwr_opmode
 Alternate Modes
 ~~~~~~~~~~~~~~~
--- a/Documentation/watchdog/watchdog-parameters.txt
+++ b/Documentation/watchdog/watchdog-parameters.txt
@ -117,7 +117,7 @@ nowayout: Watchdog cannot be stopped once started
 -------------------------------------------------
 iTCO_wdt:
 heartbeat: Watchdog heartbeat in seconds.
-	(2<heartbeat<39 (TCO v1) or 613 (TCO v2), default=30)
+	(5<=heartbeat<=74 (TCO v1) or 1226 (TCO v2), default=30)
 nowayout: Watchdog cannot be stopped once started
 	(default=kernel config parameter)
 -------------------------------------------------
--- a/50
+++ b/50
@ -846,7 +846,6 @@ M:	Laura Abbott <labbott@redhat.com>
 M:	Sumit Semwal <sumit.semwal@linaro.org>
 L:	devel@driverdev.osuosl.org
 S:	Supported
 F:	Documentation/devicetree/bindings/staging/ion/
 F:	drivers/staging/android/ion
 F:	drivers/staging/android/uapi/ion.h
 F:	drivers/staging/android/uapi/ion_test.h
@ -1173,7 +1172,7 @@ N:	clps711x
 ARM/CIRRUS LOGIC EP93XX ARM ARCHITECTURE
 M:	Hartley Sweeten <hsweeten@visionengravers.com>
-M:	Ryan Mallon <rmallon@gmail.com>
+M:	Alexander Sverdlin <alexander.sverdlin@gmail.com>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	arch/arm/mach-ep93xx/
@ -1490,13 +1489,15 @@ M:	Gregory Clement <gregory.clement@free-electrons.com>
 M:	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	arch/arm/mach-mvebu/
 F:	drivers/rtc/rtc-armada38x.c
 F:	arch/arm/boot/dts/armada*
 F:	arch/arm/boot/dts/kirkwood*
 F:	arch/arm/configs/mvebu_*_defconfig
 F:	arch/arm/mach-mvebu/
 F:	arch/arm64/boot/dts/marvell/armada*
 F:	drivers/cpufreq/mvebu-cpufreq.c
-F:	arch/arm/configs/mvebu_*_defconfig
+F:	drivers/irqchip/irq-armada-370-xp.c
 F:	drivers/irqchip/irq-mvebu-*
 F:	drivers/rtc/rtc-armada38x.c
 ARM/Marvell Berlin SoC support
 M:	Jisheng Zhang <jszhang@marvell.com>
@ -1722,7 +1723,6 @@ N:	rockchip
 ARM/SAMSUNG EXYNOS ARM ARCHITECTURES
 M:	Kukjin Kim <kgene@kernel.org>
 M:	Krzysztof Kozlowski <krzk@kernel.org>
 R:	Javier Martinez Canillas <javier@osg.samsung.com>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 L:	linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
 Q:	https://patchwork.kernel.org/project/linux-samsung-soc/list/
@ -1830,7 +1830,6 @@ F:	drivers/edac/altera_edac.
 ARM/STI ARCHITECTURE
 M:	Patrice Chotard <patrice.chotard@st.com>
 L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 L:	kernel@stlinux.com
 W:	http://www.stlinux.com
 S:	Maintained
 F:	arch/arm/mach-sti/
@ -3116,6 +3115,14 @@ F:	drivers/net/ieee802154/cc2520.c
 F:	include/linux/spi/cc2520.h
 F:	Documentation/devicetree/bindings/net/ieee802154/cc2520.txt
 CCREE ARM TRUSTZONE CRYPTOCELL 700 REE DRIVER
 M:	Gilad Ben-Yossef <gilad@benyossef.com>
 L:	linux-crypto@vger.kernel.org
 L:	driverdev-devel@linuxdriverproject.org
 S:	Supported
 F:	drivers/staging/ccree/
 W:	https://developer.arm.com/products/system-ip/trustzone-cryptocell/cryptocell-700-family
 CEC FRAMEWORK
 M:	Hans Verkuil <hans.verkuil@cisco.com>
 L:	linux-media@vger.kernel.org
@ -5615,7 +5622,7 @@ F:	scripts/get_maintainer.pl
 GENWQE (IBM Generic Workqueue Card)
 M:	Frank Haverkamp <haver@linux.vnet.ibm.com>
-M:	Gabriel Krisman Bertazi <krisman@linux.vnet.ibm.com>
+M:	Guilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com>
 S:	Supported
 F:	drivers/misc/genwqe/
@ -5660,7 +5667,6 @@ F:	tools/testing/selftests/gpio/
 GPIO SUBSYSTEM
 M:	Linus Walleij <linus.walleij@linaro.org>
 M:	Alexandre Courbot <gnurou@gmail.com>
 L:	linux-gpio@vger.kernel.org
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git
 S:	Maintained
@ -5695,7 +5701,7 @@ M:	Alex Elder <elder@kernel.org>
 M:	Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 S:	Maintained
 F:	drivers/staging/greybus/
-L:	greybus-dev@lists.linaro.org
+L:	greybus-dev@lists.linaro.org (moderated for non-subscribers)
 GREYBUS AUDIO PROTOCOLS DRIVERS
 M:	Vaibhav Agarwal <vaibhav.sr@gmail.com>
@ -7136,7 +7142,7 @@ S:	Maintained
 F:	drivers/media/platform/rcar_jpu.c
 JSM Neo PCI based serial card
-M:	Gabriel Krisman Bertazi <krisman@linux.vnet.ibm.com>
+M:	Guilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com>
 L:	linux-serial@vger.kernel.org
 S:	Maintained
 F:	drivers/tty/serial/jsm/
@ -7700,7 +7706,7 @@ F:	drivers/platform/x86/hp_accel.c
 LIVE PATCHING
 M:	Josh Poimboeuf <jpoimboe@redhat.com>
-M:	Jessica Yu <jeyu@redhat.com>
+M:	Jessica Yu <jeyu@kernel.org>
 M:	Jiri Kosina <jikos@kernel.org>
 M:	Miroslav Benes <mbenes@suse.cz>
 R:	Petr Mladek <pmladek@suse.com>
@ -8501,7 +8507,7 @@ S:	Odd Fixes
 F:	drivers/media/radio/radio-miropcm20*
 MELLANOX MLX4 core VPI driver
-M:	Yishai Hadas <yishaih@mellanox.com>
+M:	Tariq Toukan <tariqt@mellanox.com>
 L:	netdev@vger.kernel.org
 L:	linux-rdma@vger.kernel.org
 W:	http://www.mellanox.com
@ -8509,7 +8515,6 @@ Q:	http://patchwork.ozlabs.org/project/netdev/list/
 S:	Supported
 F:	drivers/net/ethernet/mellanox/mlx4/
 F:	include/linux/mlx4/
 F:	include/uapi/rdma/mlx4-abi.h
 MELLANOX MLX4 IB driver
 M:	Yishai Hadas <yishaih@mellanox.com>
@ -8519,6 +8524,7 @@ Q:	http://patchwork.kernel.org/project/linux-rdma/list/
 S:	Supported
 F:	drivers/infiniband/hw/mlx4/
 F:	include/linux/mlx4/
 F:	include/uapi/rdma/mlx4-abi.h
 MELLANOX MLX5 core VPI driver
 M:	Saeed Mahameed <saeedm@mellanox.com>
@ -8531,7 +8537,6 @@ Q:	http://patchwork.ozlabs.org/project/netdev/list/
 S:	Supported
 F:	drivers/net/ethernet/mellanox/mlx5/core/
 F:	include/linux/mlx5/
 F:	include/uapi/rdma/mlx5-abi.h
 MELLANOX MLX5 IB driver
 M:	Matan Barak <matanb@mellanox.com>
@ -8542,6 +8547,7 @@ Q:	http://patchwork.kernel.org/project/linux-rdma/list/
 S:	Supported
 F:	drivers/infiniband/hw/mlx5/
 F:	include/linux/mlx5/
 F:	include/uapi/rdma/mlx5-abi.h
 MELEXIS MLX90614 DRIVER
 M:	Crt Mori <cmo@melexis.com>
@ -8581,7 +8587,7 @@ S:	Maintained
 F:	drivers/media/dvb-frontends/mn88473*
 MODULE SUPPORT
-M:	Jessica Yu <jeyu@redhat.com>
+M:	Jessica Yu <jeyu@kernel.org>
 M:	Rusty Russell <rusty@rustcorp.com.au>
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/jeyu/linux.git modules-next
 S:	Maintained
@ -9553,10 +9559,6 @@ F:	drivers/net/wireless/intersil/orinoco/
 OSD LIBRARY and FILESYSTEM
 M:	Boaz Harrosh <ooo@electrozaur.com>
 M:	Benny Halevy <bhalevy@primarydata.com>
 L:	osd-dev@open-osd.org
 W:	http://open-osd.org
 T:	git git://git.open-osd.org/open-osd.git
 S:	Maintained
 F:	drivers/scsi/osd/
 F:	include/scsi/osd_*
@ -10447,7 +10449,7 @@ S:	Orphan
 PXA RTC DRIVER
 M:	Robert Jarzmik <robert.jarzmik@free.fr>
-L:	rtc-linux@googlegroups.com
+L:	linux-rtc@vger.kernel.org
 S:	Maintained
 QAT DRIVER
@ -10754,7 +10756,7 @@ X:	kernel/torture.c
 REAL TIME CLOCK (RTC) SUBSYSTEM
 M:	Alessandro Zummo <a.zummo@towertech.it>
 M:	Alexandre Belloni <alexandre.belloni@free-electrons.com>
-L:	rtc-linux@googlegroups.com
+L:	linux-rtc@vger.kernel.org
 Q:	http://patchwork.ozlabs.org/project/rtc-linux/list/
 T:	git git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git
 S:	Maintained
@ -11265,7 +11267,6 @@ F:	drivers/media/rc/serial_ir.c
 STI CEC DRIVER
 M:	Benjamin Gaignard <benjamin.gaignard@linaro.org>
 L:	kernel@stlinux.com
 S:	Maintained
 F:	drivers/staging/media/st-cec/
 F:	Documentation/devicetree/bindings/media/stih-cec.txt
@ -11775,6 +11776,7 @@ T:	git git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci.git
 S:	Supported
 F:	arch/arm/mach-davinci/
 F:	drivers/i2c/busses/i2c-davinci.c
 F:	arch/arm/boot/dts/da850*
 TI DAVINCI SERIES MEDIA DRIVER
 M:	"Lad, Prabhakar" <prabhakar.csengg@gmail.com>
@ -13858,7 +13860,7 @@ S:	Odd fixes
 F:	drivers/net/wireless/wl3501*
 WOLFSON MICROELECTRONICS DRIVERS
-L:	patches@opensource.wolfsonmicro.com
+L:	patches@opensource.cirrus.com
 T:	git https://github.com/CirrusLogic/linux-drivers.git
 W:	https://github.com/CirrusLogic/linux-drivers/wiki
 S:	Supported
--- a/4
+++ b/4
@ -1,7 +1,7 @@
 VERSION = 4
 PATCHLEVEL = 12
 SUBLEVEL = 0
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc5
 NAME = Fearless Coyote
 # *DOCUMENTATION*
@ -1172,7 +1172,7 @@ headers_check_all: headers_install_all
 PHONY += headers_check
 headers_check: headers_install
 	$(Q)$(MAKE) $(hdr-inst)=include/uapi HDRCHECK=1
-	$(Q)$(MAKE) $(hdr-inst)=arch/$(hdr-arch)/include/uapi/ $(hdr-dst) HDRCHECK=1
+	$(Q)$(MAKE) $(hdr-inst)=arch/$(hdr-arch)/include/uapi $(hdr-dst) HDRCHECK=1
 # ---------------------------------------------------------------------------
 # Kernel selftest
--- a/arch/alpha/kernel/osf_sys.c
+++ b/arch/alpha/kernel/osf_sys.c
@ -1201,8 +1201,10 @@ SYSCALL_DEFINE4(osf_wait4, pid_t, pid, int __user *, ustatus, int, options,
 	if (!access_ok(VERIFY_WRITE, ur, sizeof(*ur)))
 		return -EFAULT;
-	err = 0;
+	err = put_user(status, ustatus);
-	err |= put_user(status, ustatus);
+	if (ret < 0)
 		return err ? err : ret;
 	err |= __put_user(r.ru_utime.tv_sec, &ur->ru_utime.tv_sec);
 	err |= __put_user(r.ru_utime.tv_usec, &ur->ru_utime.tv_usec);
 	err |= __put_user(r.ru_stime.tv_sec, &ur->ru_stime.tv_sec);
--- a/arch/arm/boot/compressed/efi-header.S
+++ b/arch/arm/boot/compressed/efi-header.S
@ -17,14 +17,12 @@
 		@ there.
 		.inst	'M' | ('Z' << 8) | (0x1310 << 16)   @ tstne r0, #0x4d000
 #else
-		mov	r0, r0
+		W(mov)	r0, r0
 #endif
 		.endm
 		.macro	__EFI_HEADER
 #ifdef CONFIG_EFI_STUB
 		b	__efi_start
 		.set	start_offset, __efi_start - start
 		.org	start + 0x3c
 		@
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@ -130,19 +130,22 @@ start:
 		.rept	7
 		__nop
 		.endr
-   ARM(		mov	r0, r0		)
+#ifndef CONFIG_THUMB2_KERNEL
-   ARM(		b	1f		)
+		mov	r0, r0
- THUMB(		badr	r12, 1f		)
+#else
- THUMB(		bx	r12		)
+ AR_CLASS(	sub	pc, pc, #3	)	@ A/R: switch to Thumb2 mode
  M_CLASS(	nop.w			)	@ M: already in Thumb2 mode
 		.thumb
 #endif
 		W(b)	1f
 		.word	_magic_sig	@ Magic numbers to help the loader
 		.word	_magic_start	@ absolute load/run zImage address
 		.word	_magic_end	@ zImage end address
 		.word	0x04030201	@ endianness flag
- THUMB(		.thumb			)
+		__EFI_HEADER
-1:		__EFI_HEADER
+1:
 ARM_BE8(	setend	be		)	@ go BE8 if compiled for BE8
 AR_CLASS(	mrs	r9, cpsr	)
 #ifdef CONFIG_ARM_VIRT_EXT
--- a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi
+++ b/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi
@ -1,6 +1,6 @@
 / {
 	aliases {
-		ethernet = &ethernet;
+		ethernet0 = &ethernet;
 	};
 };
--- a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi
+++ b/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi
@ -1,6 +1,6 @@
 / {
 	aliases {
-		ethernet = &ethernet;
+		ethernet0 = &ethernet;
 	};
 };
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@ -3,6 +3,11 @@
 #include <dt-bindings/clock/bcm2835-aux.h>
 #include <dt-bindings/gpio/gpio.h>
 /* firmware-provided startup stubs live here, where the secondary CPUs are
 * spinning.
 */
 /memreserve/ 0x00000000 0x00001000;
 /* This include file covers the common peripherals and configuration between
 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
 * bcm2835.dtsi and bcm2836.dtsi.
@ -198,8 +203,8 @@
 				brcm,pins = <0 1>;
 				brcm,function = <BCM2835_FSEL_ALT0>;
 			};
-			i2c0_gpio32: i2c0_gpio32 {
+			i2c0_gpio28: i2c0_gpio28 {
-				brcm,pins = <32 34>;
+				brcm,pins = <28 29>;
 				brcm,function = <BCM2835_FSEL_ALT0>;
 			};
 			i2c0_gpio44: i2c0_gpio44 {
@ -295,20 +300,28 @@
 			/* Separate from the uart0_gpio14 group
 			 * because it conflicts with spi1_gpio16, and
 			 * people often run uart0 on the two pins
-			 * without flow contrl.
+			 * without flow control.
 			 */
 			uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
 				brcm,pins = <16 17>;
 				brcm,function = <BCM2835_FSEL_ALT3>;
 			};
-			uart0_gpio30: uart0_gpio30 {
+			uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
 				brcm,pins = <30 31>;
 				brcm,function = <BCM2835_FSEL_ALT3>;
 			};
-			uart0_ctsrts_gpio32: uart0_ctsrts_gpio32 {
+			uart0_gpio32: uart0_gpio32 {
 				brcm,pins = <32 33>;
 				brcm,function = <BCM2835_FSEL_ALT3>;
 			};
 			uart0_gpio36: uart0_gpio36 {
 				brcm,pins = <36 37>;
 				brcm,function = <BCM2835_FSEL_ALT2>;
 			};
 			uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
 				brcm,pins = <38 39>;
 				brcm,function = <BCM2835_FSEL_ALT2>;
 			};
 			uart1_gpio14: uart1_gpio14 {
 				brcm,pins = <14 15>;
@ -326,10 +339,6 @@
 				brcm,pins = <30 31>;
 				brcm,function = <BCM2835_FSEL_ALT5>;
 			};
 			uart1_gpio36: uart1_gpio36 {
 				brcm,pins = <36 37 38 39>;
 				brcm,function = <BCM2835_FSEL_ALT2>;
 			};
 			uart1_gpio40: uart1_gpio40 {
 				brcm,pins = <40 41>;
 				brcm,function = <BCM2835_FSEL_ALT5>;
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@ -204,6 +204,8 @@
 	tps659038: tps659038@58 {
 		compatible = "ti,tps659038";
 		reg = <0x58>;
 		ti,palmas-override-powerhold;
 		ti,system-power-controller;
 		tps659038_pmic {
 			compatible = "ti,tps659038-pmic";
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@ -2017,4 +2017,8 @@
 	coefficients = <0 2000>;
 };
 &cpu_crit {
 	temperature = <120000>; /* milli Celsius */
 };
 /include/ "dra7xx-clocks.dtsi"
--- a/arch/arm/boot/dts/imx53-qsrb.dts
+++ b/arch/arm/boot/dts/imx53-qsrb.dts
@ -23,7 +23,7 @@
 	imx53-qsrb {
 		pinctrl_pmic: pmicgrp {
 			fsl,pins = <
-				MX53_PAD_CSI0_DAT5__GPIO5_23	0x1e4 /* IRQ */
+				MX53_PAD_CSI0_DAT5__GPIO5_23	0x1c4 /* IRQ */
 			>;
 		};
 	};
--- a/arch/arm/boot/dts/imx6sx-sdb.dts
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@ -12,23 +12,6 @@
 	model = "Freescale i.MX6 SoloX SDB RevB Board";
 };
 &cpu0 {
 	operating-points = <
 		/* kHz    uV */
 		996000  1250000
 		792000  1175000
 		396000  1175000
 		198000  1175000
 		>;
 	fsl,soc-operating-points = <
 		/* ARM kHz      SOC uV */
 		996000	1250000
 		792000	1175000
 		396000	1175000
 		198000  1175000
 	>;
 };
 &i2c1 {
 	clock-frequency = <100000>;
 	pinctrl-names = "default";
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
@ -120,10 +120,16 @@
 		ethphy0: ethernet-phy@2 {
 			reg = <2>;
 			micrel,led-mode = <1>;
 			clocks = <&clks IMX6UL_CLK_ENET_REF>;
 			clock-names = "rmii-ref";
 		};
 		ethphy1: ethernet-phy@1 {
 			reg = <1>;
 			micrel,led-mode = <1>;
 			clocks = <&clks IMX6UL_CLK_ENET2_REF>;
 			clock-names = "rmii-ref";
 		};
 	};
 };
--- a/arch/arm/boot/dts/include/arm
+++ b/arch/arm/boot/dts/include/arm
@ -1 +0,0 @@
 ..
--- a/arch/arm/boot/dts/include/arm64
+++ b/arch/arm/boot/dts/include/arm64
@ -1 +0,0 @@
 ../../../../arm64/boot/dts
--- a/arch/arm/boot/dts/include/dt-bindings
+++ b/arch/arm/boot/dts/include/dt-bindings
@ -1 +0,0 @@
 ../../../../../include/dt-bindings
--- a/arch/arm/boot/dts/keystone-k2l-netcp.dtsi
+++ b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi
@ -137,8 +137,8 @@ netcp: netcp@26000000 {
 	/* NetCP address range */
 	ranges = <0 0x26000000 0x1000000>;
-	clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>, <&clkosr>;
+	clocks = <&clkpa>, <&clkcpgmac>, <&chipclk12>;
-	clock-names = "pa_clk", "ethss_clk", "cpts", "osr_clk";
+	clock-names = "pa_clk", "ethss_clk", "cpts";
 	dma-coherent;
 	ti,navigator-dmas = <&dma_gbe 0>,
--- a/arch/arm/boot/dts/keystone-k2l.dtsi
+++ b/arch/arm/boot/dts/keystone-k2l.dtsi
@ -232,6 +232,14 @@
 			};
 		};
 		osr: sram@70000000 {
 			compatible = "mmio-sram";
 			reg = <0x70000000 0x10000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			clocks = <&clkosr>;
 		};
 		dspgpio0: keystone_dsp_gpio@02620240 {
 			compatible = "ti,keystone-dsp-gpio";
 			gpio-controller;
--- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
+++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
@ -249,9 +249,9 @@
 			OMAP3_CORE1_IOPAD(0x2110, PIN_INPUT | MUX_MODE0)   /* cam_xclka.cam_xclka */
 			OMAP3_CORE1_IOPAD(0x2112, PIN_INPUT | MUX_MODE0)   /* cam_pclk.cam_pclk */
-			OMAP3_CORE1_IOPAD(0x2114, PIN_INPUT | MUX_MODE0)   /* cam_d0.cam_d0 */
+			OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0)   /* cam_d0.cam_d0 */
-			OMAP3_CORE1_IOPAD(0x2116, PIN_INPUT | MUX_MODE0)   /* cam_d1.cam_d1 */
+			OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0)   /* cam_d1.cam_d1 */
-			OMAP3_CORE1_IOPAD(0x2118, PIN_INPUT | MUX_MODE0)   /* cam_d2.cam_d2 */
+			OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE0)   /* cam_d2.cam_d2 */
 			OMAP3_CORE1_IOPAD(0x211c, PIN_INPUT | MUX_MODE0)   /* cam_d3.cam_d3 */
 			OMAP3_CORE1_IOPAD(0x211e, PIN_INPUT | MUX_MODE0)   /* cam_d4.cam_d4 */
 			OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT | MUX_MODE0)   /* cam_d5.cam_d5 */
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@ -72,6 +72,8 @@
 			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 		clock-frequency = <13000000>;
 		arm,cpu-registers-not-fw-configured;
 	};
 	watchdog: watchdog@10007000 {
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@ -55,7 +55,8 @@
 		simple-audio-card,bitclock-master = <&telephony_link_master>;
 		simple-audio-card,frame-master = <&telephony_link_master>;
 		simple-audio-card,format = "i2s";
-
+		simple-audio-card,bitclock-inversion;
 		simple-audio-card,frame-inversion;
 		simple-audio-card,cpu {
 			sound-dai = <&mcbsp4>;
 		};
--- a/arch/arm/boot/dts/omap4-panda-a4.dts
+++ b/arch/arm/boot/dts/omap4-panda-a4.dts
@ -13,7 +13,7 @@
 /* Pandaboard Rev A4+ have external pullups on SCL & SDA */
 &dss_hdmi_pins {
 	pinctrl-single,pins = <
-		OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+		OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0)		/* hdmi_cec.hdmi_cec */
 		OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0)		/* hdmi_scl.hdmi_scl */
 		OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0)		/* hdmi_sda.hdmi_sda */
 		>;
--- a/arch/arm/boot/dts/omap4-panda-es.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@ -34,7 +34,7 @@
 /* PandaboardES has external pullups on SCL & SDA */
 &dss_hdmi_pins {
 	pinctrl-single,pins = <
-		OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0)	/* hdmi_cec.hdmi_cec */
+		OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0)		/* hdmi_cec.hdmi_cec */
 		OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0)		/* hdmi_scl.hdmi_scl */
 		OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0)		/* hdmi_sda.hdmi_sda */
 		>;
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@ -1,4 +1,4 @@
-#include <versatile-ab.dts>
+#include "versatile-ab.dts"
 / {
 	model = "ARM Versatile PB";
--- a/arch/arm/common/mcpm_entry.c
+++ b/arch/arm/common/mcpm_entry.c
@ -235,7 +235,7 @@ int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster)
 	return ret;
 }
-typedef void (*phys_reset_t)(unsigned long);
+typedef typeof(cpu_reset) phys_reset_t;
 void mcpm_cpu_power_down(void)
 {
@ -300,7 +300,7 @@ void mcpm_cpu_power_down(void)
 	 * on the CPU.
 	 */
 	phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
-	phys_reset(__pa_symbol(mcpm_entry_point));
+	phys_reset(__pa_symbol(mcpm_entry_point), false);
 	/* should never get here */
 	BUG();
@ -389,7 +389,7 @@ static int __init nocache_trampoline(unsigned long _arg)
 	__mcpm_cpu_down(cpu, cluster);
 	phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
-	phys_reset(__pa_symbol(mcpm_entry_point));
+	phys_reset(__pa_symbol(mcpm_entry_point), false);
 	BUG();
 }
--- a/arch/arm/configs/gemini_defconfig
+++ b/arch/arm/configs/gemini_defconfig
@ -0,0 +1,68 @@
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ_IDLE=y
 CONFIG_BSD_PROCESS_ACCT=y
 CONFIG_USER_NS=y
 CONFIG_RELAY=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_MULTI_V4=y
 # CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_GEMINI=y
 CONFIG_PCI=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_CMDLINE="console=ttyS0,115200n8"
 CONFIG_KEXEC=y
 CONFIG_BINFMT_MISC=y
 CONFIG_PM=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_DEVTMPFS=y
 CONFIG_MTD=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
 CONFIG_MTD_CFI_STAA=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_PHYSMAP_OF=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=16384
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_ATA=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=1
 CONFIG_SERIAL_8250_RUNTIME_UARTS=1
 CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_GEMINI_WATCHDOG=y
 CONFIG_USB=y
 CONFIG_USB_MON=y
 CONFIG_USB_FOTG210_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_GEMINI=y
 CONFIG_DMADEVICES=y
 # CONFIG_DNOTIFY is not set
 CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_ROMFS_FS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ISO8859_1=y
 # CONFIG_ENABLE_WARN_DEPRECATED is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_DEBUG_FS=y
--- a/arch/arm/include/asm/device.h
+++ b/arch/arm/include/asm/device.h
@ -19,7 +19,8 @@ struct dev_archdata {
 #ifdef CONFIG_XEN
 	const struct dma_map_ops *dev_dma_ops;
 #endif
-	bool dma_coherent;
+	unsigned int dma_coherent:1;
 	unsigned int dma_ops_setup:1;
 };
 struct omap_device;
--- a/arch/arm/include/asm/kvm_coproc.h
+++ b/arch/arm/include/asm/kvm_coproc.h
@ -31,7 +31,8 @@ void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table);
 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run);
 int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run);
 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run);
-int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run);
+int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run);
 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run);
 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run);
 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run);
--- a/arch/arm/include/asm/pgtable-nommu.h
+++ b/arch/arm/include/asm/pgtable-nommu.h
@ -66,6 +66,7 @@ typedef pte_t *pte_addr_t;
 #define pgprot_noncached(prot)	(prot)
 #define pgprot_writecombine(prot) (prot)
 #define pgprot_dmacoherent(prot) (prot)
 #define pgprot_device(prot)	(prot)
 /*
--- a/arch/arm/kvm/coproc.c
+++ b/arch/arm/kvm/coproc.c
@ -32,6 +32,7 @@
 #include <asm/vfp.h>
 #include "../vfp/vfpinstr.h"
 #define CREATE_TRACE_POINTS
 #include "trace.h"
 #include "coproc.h"
@ -111,12 +112,6 @@ int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
 	return 1;
 }
 int kvm_handle_cp14_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
 	kvm_inject_undefined(vcpu);
 	return 1;
 }
 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
 {
 	/*
@ -284,7 +279,7 @@ static bool access_gic_sre(struct kvm_vcpu *vcpu,
 * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
 * all PM registers, which doesn't crash the guest kernel at least.
 */
-static bool pm_fake(struct kvm_vcpu *vcpu,
+static bool trap_raz_wi(struct kvm_vcpu *vcpu,
 		    const struct coproc_params *p,
 		    const struct coproc_reg *r)
 {
@ -294,19 +289,19 @@ static bool pm_fake(struct kvm_vcpu *vcpu,
 		return read_zero(vcpu, p);
 }
-#define access_pmcr pm_fake
+#define access_pmcr trap_raz_wi
-#define access_pmcntenset pm_fake
+#define access_pmcntenset trap_raz_wi
-#define access_pmcntenclr pm_fake
+#define access_pmcntenclr trap_raz_wi
-#define access_pmovsr pm_fake
+#define access_pmovsr trap_raz_wi
-#define access_pmselr pm_fake
+#define access_pmselr trap_raz_wi
-#define access_pmceid0 pm_fake
+#define access_pmceid0 trap_raz_wi
-#define access_pmceid1 pm_fake
+#define access_pmceid1 trap_raz_wi
-#define access_pmccntr pm_fake
+#define access_pmccntr trap_raz_wi
-#define access_pmxevtyper pm_fake
+#define access_pmxevtyper trap_raz_wi
-#define access_pmxevcntr pm_fake
+#define access_pmxevcntr trap_raz_wi
-#define access_pmuserenr pm_fake
+#define access_pmuserenr trap_raz_wi
-#define access_pmintenset pm_fake
+#define access_pmintenset trap_raz_wi
-#define access_pmintenclr pm_fake
+#define access_pmintenclr trap_raz_wi
 /* Architected CP15 registers.
 * CRn denotes the primary register number, but is copied to the CRm in the
@ -532,12 +527,7 @@ static int emulate_cp15(struct kvm_vcpu *vcpu,
 	return 1;
 }
-/**
+static struct coproc_params decode_64bit_hsr(struct kvm_vcpu *vcpu)
 * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
 * @vcpu: The VCPU pointer
 * @run:  The kvm_run struct
 */
 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
 	struct coproc_params params;
@ -551,9 +541,38 @@ int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
 	params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
 	params.CRm = 0;
 	return params;
 }
 /**
 * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
 * @vcpu: The VCPU pointer
 * @run:  The kvm_run struct
 */
 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
 	struct coproc_params params = decode_64bit_hsr(vcpu);
 	return emulate_cp15(vcpu, &params);
 }
 /**
 * kvm_handle_cp14_64 -- handles a mrrc/mcrr trap on a guest CP14 access
 * @vcpu: The VCPU pointer
 * @run:  The kvm_run struct
 */
 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
 	struct coproc_params params = decode_64bit_hsr(vcpu);
 	/* raz_wi cp14 */
 	trap_raz_wi(vcpu, &params, NULL);
 	/* handled */
 	kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
 	return 1;
 }
 static void reset_coproc_regs(struct kvm_vcpu *vcpu,
 			      const struct coproc_reg *table, size_t num)
 {
@ -564,12 +583,7 @@ static void reset_coproc_regs(struct kvm_vcpu *vcpu,
 			table[i].reset(vcpu, &table[i]);
 }
-/**
+static struct coproc_params decode_32bit_hsr(struct kvm_vcpu *vcpu)
 * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
 * @vcpu: The VCPU pointer
 * @run:  The kvm_run struct
 */
 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
 	struct coproc_params params;
@ -583,9 +597,37 @@ int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
 	params.Op2 = (kvm_vcpu_get_hsr(vcpu) >> 17) & 0x7;
 	params.Rt2 = 0;
 	return params;
 }
 /**
 * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
 * @vcpu: The VCPU pointer
 * @run:  The kvm_run struct
 */
 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
 	struct coproc_params params = decode_32bit_hsr(vcpu);
 	return emulate_cp15(vcpu, &params);
 }
 /**
 * kvm_handle_cp14_32 -- handles a mrc/mcr trap on a guest CP14 access
 * @vcpu: The VCPU pointer
 * @run:  The kvm_run struct
 */
 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
 	struct coproc_params params = decode_32bit_hsr(vcpu);
 	/* raz_wi cp14 */
 	trap_raz_wi(vcpu, &params, NULL);
 	/* handled */
 	kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
 	return 1;
 }
 /******************************************************************************
 * Userspace API
 *****************************************************************************/
--- a/arch/arm/kvm/handle_exit.c
+++ b/arch/arm/kvm/handle_exit.c
@ -95,9 +95,9 @@ static exit_handle_fn arm_exit_handlers[] = {
 	[HSR_EC_WFI]		= kvm_handle_wfx,
 	[HSR_EC_CP15_32]	= kvm_handle_cp15_32,
 	[HSR_EC_CP15_64]	= kvm_handle_cp15_64,
-	[HSR_EC_CP14_MR]	= kvm_handle_cp14_access,
+	[HSR_EC_CP14_MR]	= kvm_handle_cp14_32,
 	[HSR_EC_CP14_LS]	= kvm_handle_cp14_load_store,
-	[HSR_EC_CP14_64]	= kvm_handle_cp14_access,
+	[HSR_EC_CP14_64]	= kvm_handle_cp14_64,
 	[HSR_EC_CP_0_13]	= kvm_handle_cp_0_13_access,
 	[HSR_EC_CP10_ID]	= kvm_handle_cp10_id,
 	[HSR_EC_HVC]		= handle_hvc,
--- a/arch/arm/kvm/hyp/Makefile
+++ b/arch/arm/kvm/hyp/Makefile
@ -2,6 +2,8 @@
 # Makefile for Kernel-based Virtual Machine module, HYP part
 #
 ccflags-y += -fno-stack-protector
 KVM=../../../../virt/kvm
 obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v2-sr.o
--- a/arch/arm/kvm/hyp/switch.c
+++ b/arch/arm/kvm/hyp/switch.c
@ -48,7 +48,9 @@ static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu, u32 *fpexc_host)
 	write_sysreg(HSTR_T(15), HSTR);
 	write_sysreg(HCPTR_TTA | HCPTR_TCP(10) | HCPTR_TCP(11), HCPTR);
 	val = read_sysreg(HDCR);
-	write_sysreg(val | HDCR_TPM | HDCR_TPMCR, HDCR);
+	val |= HDCR_TPM | HDCR_TPMCR; /* trap performance monitors */
 	val |= HDCR_TDRA | HDCR_TDOSA | HDCR_TDA; /* trap debug regs */
 	write_sysreg(val, HDCR);
 }
 static void __hyp_text __deactivate_traps(struct kvm_vcpu *vcpu)
--- a/arch/arm/kvm/init.S
+++ b/arch/arm/kvm/init.S
@ -104,7 +104,6 @@ __do_hyp_init:
 	@  - Write permission implies XN: disabled
 	@  - Instruction cache: enabled
 	@  - Data/Unified cache: enabled
 	@  - Memory alignment checks: enabled
 	@  - MMU: enabled (this code must be run from an identity mapping)
 	mrc	p15, 4, r0, c1, c0, 0	@ HSCR
 	ldr	r2, =HSCTLR_MASK
@ -112,8 +111,8 @@ __do_hyp_init:
 	mrc	p15, 0, r1, c1, c0, 0	@ SCTLR
 	ldr	r2, =(HSCTLR_EE | HSCTLR_FI | HSCTLR_I | HSCTLR_C)
 	and	r1, r1, r2
- ARM(	ldr	r2, =(HSCTLR_M | HSCTLR_A)			)
+ ARM(	ldr	r2, =(HSCTLR_M)					)
- THUMB(	ldr	r2, =(HSCTLR_M | HSCTLR_A | HSCTLR_TE)		)
+ THUMB(	ldr	r2, =(HSCTLR_M | HSCTLR_TE)			)
 	orr	r1, r1, r2
 	orr	r0, r0, r1
 	mcr	p15, 4, r0, c1, c0, 0	@ HSCR
--- a/arch/arm/kvm/trace.h
+++ b/arch/arm/kvm/trace.h
@ -1,5 +1,5 @@
-#if !defined(_TRACE_KVM_H) || defined(TRACE_HEADER_MULTI_READ)
+#if !defined(_TRACE_ARM_KVM_H) || defined(TRACE_HEADER_MULTI_READ)
-#define _TRACE_KVM_H
+#define _TRACE_ARM_KVM_H
 #include <linux/tracepoint.h>
@ -74,10 +74,10 @@ TRACE_EVENT(kvm_hvc,
 		  __entry->vcpu_pc, __entry->r0, __entry->imm)
 );
-#endif /* _TRACE_KVM_H */
+#endif /* _TRACE_ARM_KVM_H */
 #undef TRACE_INCLUDE_PATH
-#define TRACE_INCLUDE_PATH arch/arm/kvm
+#define TRACE_INCLUDE_PATH .
 #undef TRACE_INCLUDE_FILE
 #define TRACE_INCLUDE_FILE trace
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@ -1,6 +1,7 @@
 menuconfig ARCH_AT91
 	bool "Atmel SoCs"
 	depends on ARCH_MULTI_V4T || ARCH_MULTI_V5 || ARCH_MULTI_V7
 	select ARM_CPU_SUSPEND if PM
 	select COMMON_CLK_AT91
 	select GPIOLIB
 	select PINCTRL
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@ -335,7 +335,7 @@ static const struct ramc_info ramc_infos[] __initconst = {
 	{ .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
 };
-static const struct of_device_id const ramc_ids[] __initconst = {
+static const struct of_device_id ramc_ids[] __initconst = {
 	{ .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
 	{ .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
 	{ .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
--- a/arch/arm/mach-bcm/bcm_kona_smc.c
+++ b/arch/arm/mach-bcm/bcm_kona_smc.c
@ -33,7 +33,7 @@ struct bcm_kona_smc_data {
 	unsigned result;
 };
-static const struct of_device_id const bcm_kona_smc_ids[] __initconst = {
+static const struct of_device_id bcm_kona_smc_ids[] __initconst = {
 	{.compatible = "brcm,kona-smc"},
 	{.compatible = "bcm,kona-smc"}, /* deprecated name */
 	{},
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@ -346,7 +346,7 @@ static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = {
 	.power_off	= csn3xxx_usb_power_off,
 };
-static const struct of_dev_auxdata const cns3xxx_auxdata[] __initconst = {
+static const struct of_dev_auxdata cns3xxx_auxdata[] __initconst = {
 	{ "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata },
 	{ "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata },
 	{ "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL },
--- a/arch/arm/mach-davinci/pm.c
+++ b/arch/arm/mach-davinci/pm.c
@ -153,7 +153,8 @@ int __init davinci_pm_init(void)
 	davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
 	if (!davinci_sram_suspend) {
 		pr_err("PM: cannot allocate SRAM memory\n");
-		return -ENOMEM;
+		ret = -ENOMEM;
 		goto no_sram_mem;
 	}
 	davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend,
@ -161,6 +162,10 @@ int __init davinci_pm_init(void)
 	suspend_set_ops(&davinci_pm_ops);
 	return 0;
 no_sram_mem:
 	iounmap(pm_config.ddrpsc_reg_base);
 no_ddrpsc_mem:
 	iounmap(pm_config.ddrpll_reg_base);
 no_ddrpll_mem:
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@ -266,11 +266,12 @@ extern int omap4_cpu_kill(unsigned int cpu);
 extern const struct smp_operations omap4_smp_ops;
 #endif
 extern u32 omap4_get_cpu1_ns_pa_addr(void);
 #if defined(CONFIG_SMP) && defined(CONFIG_PM)
 extern int omap4_mpuss_init(void);
 extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
 extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
 extern u32 omap4_get_cpu1_ns_pa_addr(void);
 #else
 static inline int omap4_enter_lowpower(unsigned int cpu,
 					unsigned int power_state)
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@ -213,11 +213,6 @@ static void __init save_l2x0_context(void)
 {}
 #endif
 u32 omap4_get_cpu1_ns_pa_addr(void)
 {
 	return old_cpu1_ns_pa_addr;
 }
 /**
 * omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
 * The purpose of this function is to manage low power programming
@ -457,6 +452,11 @@ int __init omap4_mpuss_init(void)
 #endif
 u32 omap4_get_cpu1_ns_pa_addr(void)
 {
 	return old_cpu1_ns_pa_addr;
 }
 /*
 * For kexec, we must set CPU1_WAKEUP_NS_PA_ADDR to point to
 * current kernel's secondary_startup() early before
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@ -306,7 +306,6 @@ static void __init omap4_smp_maybe_reset_cpu1(struct omap_smp_config *c)
 	cpu1_startup_pa = readl_relaxed(cfg.wakeupgen_base +
 					OMAP_AUX_CORE_BOOT_1);
 	cpu1_ns_pa_addr = omap4_get_cpu1_ns_pa_addr();
 	/* Did the configured secondary_startup() get overwritten? */
 	if (!omap4_smp_cpu1_startup_valid(cpu1_startup_pa))
@ -316,9 +315,13 @@ static void __init omap4_smp_maybe_reset_cpu1(struct omap_smp_config *c)
 	 * If omap4 or 5 has NS_PA_ADDR configured, CPU1 may be in a
 	 * deeper idle state in WFI and will wake to an invalid address.
 	 */
-	if ((soc_is_omap44xx() || soc_is_omap54xx()) &&
+	if ((soc_is_omap44xx() || soc_is_omap54xx())) {
-	    !omap4_smp_cpu1_startup_valid(cpu1_ns_pa_addr))
+		cpu1_ns_pa_addr = omap4_get_cpu1_ns_pa_addr();
-		needs_reset = true;
+		if (!omap4_smp_cpu1_startup_valid(cpu1_ns_pa_addr))
 			needs_reset = true;
 	} else {
 		cpu1_ns_pa_addr = 0;
 	}
 	if (!needs_reset || !c->cpu1_rstctrl_va)
 		return;
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@ -711,7 +711,7 @@ static struct omap_prcm_init_data scrm_data __initdata = {
 };
 #endif
-static const struct of_device_id const omap_prcm_dt_match_table[] __initconst = {
+static const struct of_device_id omap_prcm_dt_match_table[] __initconst = {
 #ifdef CONFIG_SOC_AM33XX
 	{ .compatible = "ti,am3-prcm", .data = &am3_prm_data },
 #endif
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@ -559,7 +559,7 @@ struct i2c_init_data {
 	u8 hsscll_12;
 };
-static const struct i2c_init_data const omap4_i2c_timing_data[] __initconst = {
+static const struct i2c_init_data omap4_i2c_timing_data[] __initconst = {
 	{
 		.load = 50,
 		.loadbits = 0x3,
--- a/arch/arm/mach-spear/time.c
+++ b/arch/arm/mach-spear/time.c
@ -204,7 +204,7 @@ static void __init spear_clockevent_init(int irq)
 	setup_irq(irq, &spear_timer_irq);
 }
-static const struct of_device_id const timer_of_match[] __initconst = {
+static const struct of_device_id timer_of_match[] __initconst = {
 	{ .compatible = "st,spear-timer", },
 	{ },
 };
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@ -2311,7 +2311,14 @@ int arm_iommu_attach_device(struct device *dev,
 }
 EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
-static void __arm_iommu_detach_device(struct device *dev)
+/**
 * arm_iommu_detach_device
 * @dev: valid struct device pointer
 *
 * Detaches the provided device from a previously attached map.
 * This voids the dma operations (dma_map_ops pointer)
 */
 void arm_iommu_detach_device(struct device *dev)
 {
 	struct dma_iommu_mapping *mapping;
@ -2324,22 +2331,10 @@ static void __arm_iommu_detach_device(struct device *dev)
 	iommu_detach_device(mapping->domain, dev);
 	kref_put(&mapping->kref, release_iommu_mapping);
 	to_dma_iommu_mapping(dev) = NULL;
 	set_dma_ops(dev, NULL);
 	pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
 }
 /**
 * arm_iommu_detach_device
 * @dev: valid struct device pointer
 *
 * Detaches the provided device from a previously attached map.
 * This voids the dma operations (dma_map_ops pointer)
 */
 void arm_iommu_detach_device(struct device *dev)
 {
 	__arm_iommu_detach_device(dev);
 	set_dma_ops(dev, NULL);
 }
 EXPORT_SYMBOL_GPL(arm_iommu_detach_device);
 static const struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent)
@ -2379,7 +2374,7 @@ static void arm_teardown_iommu_dma_ops(struct device *dev)
 	if (!mapping)
 		return;
-	__arm_iommu_detach_device(dev);
+	arm_iommu_detach_device(dev);
 	arm_iommu_release_mapping(mapping);
 }
@ -2430,9 +2425,13 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
 		dev->dma_ops = xen_dma_ops;
 	}
 #endif
 	dev->archdata.dma_ops_setup = true;
 }
 void arch_teardown_dma_ops(struct device *dev)
 {
 	if (!dev->archdata.dma_ops_setup)
 		return;
 	arm_teardown_iommu_dma_ops(dev);
 }
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@ -1084,10 +1084,6 @@ config SYSVIPC_COMPAT
 	def_bool y
 	depends on COMPAT && SYSVIPC
 config KEYS_COMPAT
 	def_bool y
 	depends on COMPAT && KEYS
 endmenu
 menu "Power management options"
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@ -106,8 +106,13 @@ config ARCH_MVEBU
 	select ARMADA_AP806_SYSCON
 	select ARMADA_CP110_SYSCON
 	select ARMADA_37XX_CLK
 	select GPIOLIB
 	select GPIOLIB_IRQCHIP
 	select MVEBU_ODMI
 	select MVEBU_PIC
 	select OF_GPIO
 	select PINCTRL
 	select PINCTRL_ARMADA_37XX
 	help
 	  This enables support for Marvell EBU familly, including:
 	   - Armada 3700 SoC Family
--- a/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
+++ b/arch/arm64/boot/dts/hisilicon/hi6220-hikey.dts
@ -81,6 +81,45 @@
 		};
 	};
 	reg_sys_5v: regulator@0 {
 		compatible = "regulator-fixed";
 		regulator-name = "SYS_5V";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
 		regulator-boot-on;
 		regulator-always-on;
 	};
 	reg_vdd_3v3: regulator@1 {
 		compatible = "regulator-fixed";
 		regulator-name = "VDD_3V3";
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 		regulator-boot-on;
 		regulator-always-on;
 		vin-supply = <&reg_sys_5v>;
 	};
 	reg_5v_hub: regulator@2 {
 		compatible = "regulator-fixed";
 		regulator-name = "5V_HUB";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
 		regulator-boot-on;
 		gpio = <&gpio0 7 0>;
 		regulator-always-on;
 		vin-supply = <&reg_sys_5v>;
 	};
 	wl1835_pwrseq: wl1835-pwrseq {
 		compatible = "mmc-pwrseq-simple";
 		/* WLAN_EN GPIO */
 		reset-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
 		clocks = <&pmic>;
 		clock-names = "ext_clock";
 		power-off-delay-us = <10>;
 	};
 	soc {
 		spi0: spi@f7106000 {
 			status = "ok";
@ -256,11 +295,31 @@
 		/* GPIO blocks 16 thru 19 do not appear to be routed to pins */
-		dwmmc_2: dwmmc2@f723f000 {
+		dwmmc_0: dwmmc0@f723d000 {
-			ti,non-removable;
+			cap-mmc-highspeed;
 			non-removable;
-			/* WL_EN */
+			bus-width = <0x8>;
-			vmmc-supply = <&wlan_en_reg>;
+			vmmc-supply = <&ldo19>;
 		};
 		dwmmc_1: dwmmc1@f723e000 {
 			card-detect-delay = <200>;
 			cap-sd-highspeed;
 			sd-uhs-sdr12;
 			sd-uhs-sdr25;
 			sd-uhs-sdr50;
 			vqmmc-supply = <&ldo7>;
 			vmmc-supply = <&ldo10>;
 			bus-width = <0x4>;
 			disable-wp;
 			cd-gpios = <&gpio1 0 1>;
 		};
 		dwmmc_2: dwmmc2@f723f000 {
 			bus-width = <0x4>;
 			non-removable;
 			vmmc-supply = <&reg_vdd_3v3>;
 			mmc-pwrseq = <&wl1835_pwrseq>;
 			#address-cells = <0x1>;
 			#size-cells = <0x0>;
@ -272,18 +331,6 @@
 				interrupts = <3 IRQ_TYPE_EDGE_RISING>;
 			};
 		};
 		wlan_en_reg: regulator@1 {
 			compatible = "regulator-fixed";
 			regulator-name = "wlan-en-regulator";
 			regulator-min-microvolt = <1800000>;
 			regulator-max-microvolt = <1800000>;
 			/* WLAN_EN GPIO */
 			gpio = <&gpio0 5 0>;
 			/* WLAN card specific delay */
 			startup-delay-us = <70000>;
 			enable-active-high;
 		};
 	};
 	leds {
@ -330,6 +377,7 @@
 	pmic: pmic@f8000000 {
 		compatible = "hisilicon,hi655x-pmic";
 		reg = <0x0 0xf8000000 0x0 0x1000>;
 		#clock-cells = <0>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
 		pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@ -725,20 +725,10 @@
 			status = "disabled";
 		};
 		fixed_5v_hub: regulator@0 {
 			compatible = "regulator-fixed";
 			regulator-name = "fixed_5v_hub";
 			regulator-min-microvolt = <5000000>;
 			regulator-max-microvolt = <5000000>;
 			regulator-boot-on;
 			gpio = <&gpio0 7 0>;
 			regulator-always-on;
 		};
 		usb_phy: usbphy {
 			compatible = "hisilicon,hi6220-usb-phy";
 			#phy-cells = <0>;
-			phy-supply = <&fixed_5v_hub>;
+			phy-supply = <&reg_5v_hub>;
 			hisilicon,peripheral-syscon = <&sys_ctrl>;
 		};
@ -766,17 +756,12 @@
 		dwmmc_0: dwmmc0@f723d000 {
 			compatible = "hisilicon,hi6220-dw-mshc";
 			num-slots = <0x1>;
 			cap-mmc-highspeed;
 			non-removable;
 			reg = <0x0 0xf723d000 0x0 0x1000>;
 			interrupts = <0x0 0x48 0x4>;
 			clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
 			clock-names = "ciu", "biu";
 			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
 			reset-names = "reset";
 			bus-width = <0x8>;
 			vmmc-supply = <&ldo19>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&emmc_pmx_func &emmc_clk_cfg_func
 				     &emmc_cfg_func &emmc_rst_cfg_func>;
@ -784,13 +769,7 @@
 		dwmmc_1: dwmmc1@f723e000 {
 			compatible = "hisilicon,hi6220-dw-mshc";
 			num-slots = <0x1>;
 			card-detect-delay = <200>;
 			hisilicon,peripheral-syscon = <&ao_ctrl>;
 			cap-sd-highspeed;
 			sd-uhs-sdr12;
 			sd-uhs-sdr25;
 			sd-uhs-sdr50;
 			reg = <0x0 0xf723e000 0x0 0x1000>;
 			interrupts = <0x0 0x49 0x4>;
 			#address-cells = <0x1>;
@ -799,11 +778,6 @@
 			clock-names = "ciu", "biu";
 			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
 			reset-names = "reset";
 			vqmmc-supply = <&ldo7>;
 			vmmc-supply = <&ldo10>;
 			bus-width = <0x4>;
 			disable-wp;
 			cd-gpios = <&gpio1 0 1>;
 			pinctrl-names = "default", "idle";
 			pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
 			pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
@ -811,15 +785,12 @@
 		dwmmc_2: dwmmc2@f723f000 {
 			compatible = "hisilicon,hi6220-dw-mshc";
 			num-slots = <0x1>;
 			reg = <0x0 0xf723f000 0x0 0x1000>;
 			interrupts = <0x0 0x4a 0x4>;
 			clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
 			clock-names = "ciu", "biu";
 			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
 			reset-names = "reset";
 			bus-width = <0x4>;
 			broken-cd;
 			pinctrl-names = "default", "idle";
 			pinctrl-0 = <&sdio_pmx_func &sdio_clk_cfg_func &sdio_cfg_func>;
 			pinctrl-1 = <&sdio_pmx_idle &sdio_clk_cfg_idle &sdio_cfg_idle>;
--- a/arch/arm64/boot/dts/include/arm
+++ b/arch/arm64/boot/dts/include/arm
@ -1 +0,0 @@
 ../../../../arm/boot/dts
--- a/arch/arm64/boot/dts/include/arm64
+++ b/arch/arm64/boot/dts/include/arm64
@ -1 +0,0 @@
 ..
--- a/arch/arm64/boot/dts/include/dt-bindings
+++ b/arch/arm64/boot/dts/include/dt-bindings
@ -1 +0,0 @@
 ../../../../../include/dt-bindings
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@ -79,6 +79,8 @@
 };
 &i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c1_pins>;
 	status = "okay";
 	gpio_exp: pca9555@22 {
@ -113,6 +115,8 @@
 &spi0 {
 	status = "okay";
 	pinctrl-names = "default";
 	pinctrl-0 = <&spi_quad_pins>;
 	m25p80@0 {
 		compatible = "jedec,spi-nor";
@ -143,6 +147,8 @@
 /* Exported on the micro USB connector CON32 through an FTDI */
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart1_pins>;
 	status = "okay";
 };
@ -184,6 +190,8 @@
 };
 &eth0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&rgmii_pins>;
 	phy-mode = "rgmii-id";
 	phy = <&phy0>;
 	status = "okay";
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@ -161,16 +161,83 @@
 				#clock-cells = <1>;
 			};
-			gpio1: gpio@13800 {
+			pinctrl_nb: pinctrl@13800 {
-				compatible = "marvell,mvebu-gpio-3700",
+				compatible = "marvell,armada3710-nb-pinctrl",
 				"syscon", "simple-mfd";
-				reg = <0x13800 0x500>;
+				reg = <0x13800 0x100>, <0x13C00 0x20>;
 				gpionb: gpio {
 					#gpio-cells = <2>;
 					gpio-ranges = <&pinctrl_nb 0 0 36>;
 					gpio-controller;
 					interrupts =
 					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 				};
 				xtalclk: xtal-clk {
 					compatible = "marvell,armada-3700-xtal-clock";
 					clock-output-names = "xtal";
 					#clock-cells = <0>;
 				};
 				spi_quad_pins: spi-quad-pins {
 					groups = "spi_quad";
 					function = "spi";
 				};
 				i2c1_pins: i2c1-pins {
 					groups = "i2c1";
 					function = "i2c";
 				};
 				i2c2_pins: i2c2-pins {
 					groups = "i2c2";
 					function = "i2c";
 				};
 				uart1_pins: uart1-pins {
 					groups = "uart1";
 					function = "uart";
 				};
 				uart2_pins: uart2-pins {
 					groups = "uart2";
 					function = "uart";
 				};
 			};
 			pinctrl_sb: pinctrl@18800 {
 				compatible = "marvell,armada3710-sb-pinctrl",
 				"syscon", "simple-mfd";
 				reg = <0x18800 0x100>, <0x18C00 0x20>;
 				gpiosb: gpio {
 					#gpio-cells = <2>;
 					gpio-ranges = <&pinctrl_sb 0 0 29>;
 					gpio-controller;
 					interrupts =
 					<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
 					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 				};
 				rgmii_pins: mii-pins {
 					groups = "rgmii";
 					function = "mii";
 				};
 			};
 			eth0: ethernet@30000 {
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@ -231,8 +231,7 @@
 			cpm_crypto: crypto@800000 {
 				compatible = "inside-secure,safexcel-eip197";
 				reg = <0x800000 0x200000>;
-				interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
+				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 				| IRQ_TYPE_LEVEL_HIGH)>,
 					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@ -221,8 +221,7 @@
 			cps_crypto: crypto@800000 {
 				compatible = "inside-secure,safexcel-eip197";
 				reg = <0x800000 0x200000>;
-				interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
+				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
 				| IRQ_TYPE_LEVEL_HIGH)>,
 					     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 					     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
--- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts
@ -134,6 +134,9 @@
 	bus-width = <8>;
 	max-frequency = <50000000>;
 	cap-mmc-highspeed;
 	mediatek,hs200-cmd-int-delay=<26>;
 	mediatek,hs400-cmd-int-delay=<14>;
 	mediatek,hs400-cmd-resp-sel-rising;
 	vmmc-supply = <&mt6397_vemc_3v3_reg>;
 	vqmmc-supply = <&mt6397_vio18_reg>;
 	non-removable;
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dts
@ -44,7 +44,7 @@
 /dts-v1/;
 #include "rk3399-gru.dtsi"
-#include <include/dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/input/linux-event-codes.h>
 /*
 * Kevin-specific things
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@ -30,7 +30,6 @@ CONFIG_PROFILING=y
 CONFIG_JUMP_LABEL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_ALPINE=y
@ -62,16 +61,16 @@ CONFIG_ARCH_XGENE=y
 CONFIG_ARCH_ZX=y
 CONFIG_ARCH_ZYNQMP=y
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y
 CONFIG_PCI_IOV=y
 CONFIG_PCI_AARDVARK=y
 CONFIG_PCIE_RCAR=y
 CONFIG_PCI_HOST_GENERIC=y
 CONFIG_PCI_XGENE=y
 CONFIG_PCI_LAYERSCAPE=y
 CONFIG_PCI_HISI=y
 CONFIG_PCIE_QCOM=y
 CONFIG_PCIE_ARMADA_8K=y
 CONFIG_PCI_AARDVARK=y
 CONFIG_PCIE_RCAR=y
 CONFIG_PCIE_ROCKCHIP=m
 CONFIG_PCI_HOST_GENERIC=y
 CONFIG_PCI_XGENE=y
 CONFIG_ARM64_VA_BITS_48=y
 CONFIG_SCHED_MC=y
 CONFIG_NUMA=y
@ -80,12 +79,11 @@ CONFIG_KSM=y
 CONFIG_TRANSPARENT_HUGEPAGE=y
 CONFIG_CMA=y
 CONFIG_SECCOMP=y
 CONFIG_XEN=y
 CONFIG_KEXEC=y
 CONFIG_CRASH_DUMP=y
 CONFIG_XEN=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_COMPAT=y
 CONFIG_CPU_IDLE=y
 CONFIG_HIBERNATION=y
 CONFIG_ARM_CPUIDLE=y
 CONFIG_CPU_FREQ=y
@ -155,8 +153,8 @@ CONFIG_MTD_SPI_NOR=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_NBD=m
 CONFIG_VIRTIO_BLK=y
 CONFIG_EEPROM_AT25=m
 CONFIG_SRAM=y
 CONFIG_EEPROM_AT25=m
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 CONFIG_SCSI_SAS_ATA=y
@ -168,8 +166,8 @@ CONFIG_AHCI_CEVA=y
 CONFIG_AHCI_MVEBU=y
 CONFIG_AHCI_XGENE=y
 CONFIG_AHCI_QORIQ=y
 CONFIG_SATA_RCAR=y
 CONFIG_SATA_SIL24=y
 CONFIG_SATA_RCAR=y
 CONFIG_PATA_PLATFORM=y
 CONFIG_PATA_OF_PLATFORM=y
 CONFIG_NETDEVICES=y
@ -186,18 +184,17 @@ CONFIG_HNS_ENET=y
 CONFIG_E1000E=y
 CONFIG_IGB=y
 CONFIG_IGBVF=y
 CONFIG_MVPP2=y
 CONFIG_MVNETA=y
 CONFIG_MVPP2=y
 CONFIG_SKY2=y
 CONFIG_RAVB=y
 CONFIG_SMC91X=y
 CONFIG_SMSC911X=y
 CONFIG_STMMAC_ETH=m
-CONFIG_REALTEK_PHY=m
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
 CONFIG_MESON_GXL_PHY=m
 CONFIG_MICREL_PHY=y
-CONFIG_MDIO_BUS_MUX=y
+CONFIG_REALTEK_PHY=m
 CONFIG_MDIO_BUS_MUX_MMIOREG=y
 CONFIG_USB_PEGASUS=m
 CONFIG_USB_RTL8150=m
 CONFIG_USB_RTL8152=m
@ -212,6 +209,8 @@ CONFIG_BRCMFMAC=m
 CONFIG_WL18XX=m
 CONFIG_WLCORE_SDIO=m
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_ADC=m
 CONFIG_KEYBOARD_CROS_EC=y
 CONFIG_KEYBOARD_GPIO=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_PM8941_PWRKEY=y
@ -230,14 +229,14 @@ CONFIG_SERIAL_8250_UNIPHIER=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_SERIAL_MESON=y
 CONFIG_SERIAL_MESON_CONSOLE=y
 CONFIG_SERIAL_SAMSUNG=y
 CONFIG_SERIAL_SAMSUNG_CONSOLE=y
 CONFIG_SERIAL_TEGRA=y
 CONFIG_SERIAL_SH_SCI=y
 CONFIG_SERIAL_SH_SCI_NR_UARTS=11
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 CONFIG_SERIAL_MESON=y
 CONFIG_SERIAL_MESON_CONSOLE=y
 CONFIG_SERIAL_MSM=y
 CONFIG_SERIAL_MSM_CONSOLE=y
 CONFIG_SERIAL_XILINX_PS_UART=y
@ -261,14 +260,15 @@ CONFIG_I2C_UNIPHIER_F=y
 CONFIG_I2C_RCAR=y
 CONFIG_I2C_CROS_EC_TUNNEL=y
 CONFIG_SPI=y
 CONFIG_SPI_MESON_SPIFC=m
 CONFIG_SPI_BCM2835=m
 CONFIG_SPI_BCM2835AUX=m
 CONFIG_SPI_MESON_SPIFC=m
 CONFIG_SPI_ORION=y
 CONFIG_SPI_PL022=y
 CONFIG_SPI_QUP=y
-CONFIG_SPI_SPIDEV=m
+CONFIG_SPI_ROCKCHIP=y
 CONFIG_SPI_S3C64XX=y
 CONFIG_SPI_SPIDEV=m
 CONFIG_SPMI=y
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_PINCTRL_MAX77620=y
@ -286,33 +286,33 @@ CONFIG_GPIO_PCA953X=y
 CONFIG_GPIO_PCA953X_IRQ=y
 CONFIG_GPIO_MAX77620=y
 CONFIG_POWER_RESET_MSM=y
 CONFIG_BATTERY_BQ27XXX=y
 CONFIG_POWER_RESET_XGENE=y
 CONFIG_POWER_RESET_SYSCON=y
 CONFIG_BATTERY_BQ27XXX=y
 CONFIG_SENSORS_ARM_SCPI=y
 CONFIG_SENSORS_LM90=m
 CONFIG_SENSORS_INA2XX=m
 CONFIG_SENSORS_ARM_SCPI=y
 CONFIG_THERMAL=y
 CONFIG_THERMAL_EMULATION=y
 CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
 CONFIG_CPU_THERMAL=y
-CONFIG_BCM2835_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
 CONFIG_EXYNOS_THERMAL=y
 CONFIG_ROCKCHIP_THERMAL=m
 CONFIG_WATCHDOG=y
 CONFIG_BCM2835_WDT=y
 CONFIG_RENESAS_WDT=y
 CONFIG_S3C2410_WATCHDOG=y
 CONFIG_MESON_GXBB_WATCHDOG=m
 CONFIG_MESON_WATCHDOG=m
-CONFIG_MFD_EXYNOS_LPASS=m
+CONFIG_RENESAS_WDT=y
-CONFIG_MFD_MAX77620=y
+CONFIG_BCM2835_WDT=y
 CONFIG_MFD_RK808=y
 CONFIG_MFD_SPMI_PMIC=y
 CONFIG_MFD_SEC_CORE=y
 CONFIG_MFD_HI655X_PMIC=y
 CONFIG_REGULATOR=y
 CONFIG_MFD_CROS_EC=y
 CONFIG_MFD_CROS_EC_I2C=y
 CONFIG_MFD_CROS_EC_SPI=y
 CONFIG_MFD_EXYNOS_LPASS=m
 CONFIG_MFD_HI655X_PMIC=y
 CONFIG_MFD_MAX77620=y
 CONFIG_MFD_SPMI_PMIC=y
 CONFIG_MFD_RK808=y
 CONFIG_MFD_SEC_CORE=y
 CONFIG_REGULATOR_FAN53555=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_HI655X=y
@ -345,13 +345,12 @@ CONFIG_DRM_EXYNOS_DSI=y
 CONFIG_DRM_EXYNOS_HDMI=y
 CONFIG_DRM_EXYNOS_MIC=y
 CONFIG_DRM_RCAR_DU=m
 CONFIG_DRM_RCAR_HDMI=y
 CONFIG_DRM_RCAR_LVDS=y
 CONFIG_DRM_RCAR_VSP=y
 CONFIG_DRM_TEGRA=m
 CONFIG_DRM_VC4=m
 CONFIG_DRM_PANEL_SIMPLE=m
 CONFIG_DRM_I2C_ADV7511=m
 CONFIG_DRM_VC4=m
 CONFIG_DRM_HISI_KIRIN=m
 CONFIG_DRM_MESON=m
 CONFIG_FB=y
@ -366,39 +365,37 @@ CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_SOC=y
 CONFIG_SND_BCM2835_SOC_I2S=m
 CONFIG_SND_SOC_RCAR=y
 CONFIG_SND_SOC_SAMSUNG=y
 CONFIG_SND_SOC_RCAR=y
 CONFIG_SND_SOC_AK4613=y
 CONFIG_USB=y
 CONFIG_USB_OTG=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_PLATFORM=y
 CONFIG_USB_XHCI_RCAR=y
 CONFIG_USB_EHCI_EXYNOS=y
 CONFIG_USB_XHCI_TEGRA=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MSM=y
 CONFIG_USB_EHCI_EXYNOS=y
 CONFIG_USB_EHCI_HCD_PLATFORM=y
 CONFIG_USB_OHCI_EXYNOS=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_EXYNOS=y
 CONFIG_USB_OHCI_HCD_PLATFORM=y
 CONFIG_USB_RENESAS_USBHS=m
 CONFIG_USB_STORAGE=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_DWC3=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_CHIPIDEA=y
 CONFIG_USB_CHIPIDEA_UDC=y
 CONFIG_USB_CHIPIDEA_HOST=y
 CONFIG_USB_ISP1760=y
 CONFIG_USB_HSIC_USB3503=y
 CONFIG_USB_MSM_OTG=y
 CONFIG_USB_QCOM_8X16_PHY=y
 CONFIG_USB_ULPI=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_RENESAS_USBHS_UDC=m
 CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=32
 CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_MESON_GX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ACPI=y
 CONFIG_MMC_SDHCI_PLTFM=y
@ -406,6 +403,7 @@ CONFIG_MMC_SDHCI_OF_ARASAN=y
 CONFIG_MMC_SDHCI_OF_ESDHC=y
 CONFIG_MMC_SDHCI_CADENCE=y
 CONFIG_MMC_SDHCI_TEGRA=y
 CONFIG_MMC_MESON_GX=y
 CONFIG_MMC_SDHCI_MSM=y
 CONFIG_MMC_SPI=y
 CONFIG_MMC_SDHI=y
@ -414,32 +412,31 @@ CONFIG_MMC_DW_EXYNOS=y
 CONFIG_MMC_DW_K3=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SUNXI=y
 CONFIG_MMC_SDHCI_XENON=y
 CONFIG_MMC_BCM2835=y
 CONFIG_MMC_SDHCI_XENON=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_PWM=y
 CONFIG_LEDS_SYSCON=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_CPU=y
 CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_MAX77686=y
 CONFIG_RTC_DRV_RK808=m
 CONFIG_RTC_DRV_S5M=y
 CONFIG_RTC_DRV_DS3232=y
 CONFIG_RTC_DRV_EFI=y
 CONFIG_RTC_DRV_S3C=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_RTC_DRV_SUN6I=y
 CONFIG_RTC_DRV_RK808=m
 CONFIG_RTC_DRV_TEGRA=y
 CONFIG_RTC_DRV_XGENE=y
 CONFIG_RTC_DRV_S3C=y
 CONFIG_DMADEVICES=y
 CONFIG_DMA_BCM2835=m
 CONFIG_MV_XOR_V2=y
 CONFIG_PL330_DMA=y
 CONFIG_DMA_BCM2835=m
 CONFIG_TEGRA20_APB_DMA=y
 CONFIG_QCOM_BAM_DMA=y
 CONFIG_QCOM_HIDMA_MGMT=y
@ -452,52 +449,56 @@ CONFIG_VIRTIO_BALLOON=y
 CONFIG_VIRTIO_MMIO=y
 CONFIG_XEN_GNTDEV=y
 CONFIG_XEN_GRANT_DEV_ALLOC=y
 CONFIG_COMMON_CLK_RK808=y
 CONFIG_COMMON_CLK_SCPI=y
 CONFIG_COMMON_CLK_CS2000_CP=y
 CONFIG_COMMON_CLK_S2MPS11=y
 CONFIG_COMMON_CLK_PWM=y
 CONFIG_COMMON_CLK_RK808=y
 CONFIG_CLK_QORIQ=y
 CONFIG_COMMON_CLK_PWM=y
 CONFIG_COMMON_CLK_QCOM=y
 CONFIG_QCOM_CLK_SMD_RPM=y
 CONFIG_MSM_GCC_8916=y
 CONFIG_MSM_GCC_8994=y
 CONFIG_MSM_MMCC_8996=y
 CONFIG_HWSPINLOCK_QCOM=y
 CONFIG_MAILBOX=y
 CONFIG_ARM_MHU=y
 CONFIG_PLATFORM_MHU=y
 CONFIG_BCM2835_MBOX=y
 CONFIG_HI6220_MBOX=y
 CONFIG_ARM_SMMU=y
 CONFIG_ARM_SMMU_V3=y
 CONFIG_RPMSG_QCOM_SMD=y
 CONFIG_RASPBERRYPI_POWER=y
 CONFIG_QCOM_SMEM=y
 CONFIG_QCOM_SMD=y
 CONFIG_QCOM_SMD_RPM=y
 CONFIG_QCOM_SMP2P=y
 CONFIG_QCOM_SMSM=y
 CONFIG_ROCKCHIP_PM_DOMAINS=y
 CONFIG_ARCH_TEGRA_132_SOC=y
 CONFIG_ARCH_TEGRA_210_SOC=y
 CONFIG_ARCH_TEGRA_186_SOC=y
 CONFIG_EXTCON_USB_GPIO=y
 CONFIG_IIO=y
 CONFIG_EXYNOS_ADC=y
 CONFIG_ROCKCHIP_SARADC=m
 CONFIG_PWM=y
 CONFIG_PWM_BCM2835=m
-CONFIG_PWM_ROCKCHIP=y
+CONFIG_PWM_CROS_EC=m
 CONFIG_PWM_TEGRA=m
 CONFIG_PWM_MESON=m
-CONFIG_COMMON_RESET_HI6220=y
+CONFIG_PWM_ROCKCHIP=y
 CONFIG_PWM_SAMSUNG=y
 CONFIG_PWM_TEGRA=m
 CONFIG_PHY_RCAR_GEN3_USB2=y
 CONFIG_PHY_HI6220_USB=y
 CONFIG_PHY_SUN4I_USB=y
 CONFIG_PHY_ROCKCHIP_INNO_USB2=y
 CONFIG_PHY_ROCKCHIP_EMMC=y
-CONFIG_PHY_SUN4I_USB=y
+CONFIG_PHY_ROCKCHIP_PCIE=m
 CONFIG_PHY_XGENE=y
 CONFIG_PHY_TEGRA_XUSB=y
 CONFIG_ARM_SCPI_PROTOCOL=y
 CONFIG_ACPI=y
 CONFIG_IIO=y
 CONFIG_EXYNOS_ADC=y
 CONFIG_PWM_SAMSUNG=y
 CONFIG_RASPBERRYPI_FIRMWARE=y
 CONFIG_ACPI=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
@ -511,7 +512,6 @@ CONFIG_FUSE_FS=m
 CONFIG_CUSE=m
 CONFIG_OVERLAY_FS=m
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_HUGETLBFS=y
 CONFIG_CONFIGFS_FS=y
 CONFIG_EFIVAR_FS=y
@ -539,11 +539,9 @@ CONFIG_MEMTEST=y
 CONFIG_SECURITY=y
 CONFIG_CRYPTO_ECHAINIV=y
 CONFIG_CRYPTO_ANSI_CPRNG=y
 CONFIG_CRYPTO_DEV_SAFEXCEL=m
 CONFIG_ARM64_CRYPTO=y
 CONFIG_CRYPTO_SHA1_ARM64_CE=y
 CONFIG_CRYPTO_SHA2_ARM64_CE=y
 CONFIG_CRYPTO_GHASH_ARM64_CE=y
 CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
 CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
 # CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set
--- a/arch/arm64/include/asm/acpi.h
+++ b/arch/arm64/include/asm/acpi.h
@ -23,9 +23,9 @@
 #define ACPI_MADT_GICC_LENGTH	\
 	(acpi_gbl_FADT.header.revision < 6 ? 76 : 80)
-#define BAD_MADT_GICC_ENTRY(entry, end)						\
+#define BAD_MADT_GICC_ENTRY(entry, end)					\
-	(!(entry) || (unsigned long)(entry) + sizeof(*(entry)) > (end) ||	\
+	(!(entry) || (entry)->header.length != ACPI_MADT_GICC_LENGTH ||	\
-	 (entry)->header.length != ACPI_MADT_GICC_LENGTH)
+	(unsigned long)(entry) + ACPI_MADT_GICC_LENGTH > (end))
 /* Basic configuration for ACPI */
 #ifdef	CONFIG_ACPI
--- a/arch/arm64/include/asm/atomic_ll_sc.h
+++ b/arch/arm64/include/asm/atomic_ll_sc.h
@ -264,7 +264,6 @@ __LL_SC_PREFIX(__cmpxchg_case_##name(volatile void *ptr,		\
 	"	st" #rel "xr" #sz "\t%w[tmp], %" #w "[new], %[v]\n"	\
 	"	cbnz	%w[tmp], 1b\n"					\
 	"	" #mb "\n"						\
 	"	mov	%" #w "[oldval], %" #w "[old]\n"		\
 	"2:"								\
 	: [tmp] "=&r" (tmp), [oldval] "=&r" (oldval),			\
 	  [v] "+Q" (*(unsigned long *)ptr)				\
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@ -115,6 +115,7 @@ struct arm64_cpu_capabilities {
 extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
 extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];
 extern struct static_key_false arm64_const_caps_ready;
 bool this_cpu_has_cap(unsigned int cap);
@ -124,7 +125,7 @@ static inline bool cpu_have_feature(unsigned int num)
 }
 /* System capability check for constant caps */
-static inline bool cpus_have_const_cap(int num)
+static inline bool __cpus_have_const_cap(int num)
 {
 	if (num >= ARM64_NCAPS)
 		return false;
@ -138,6 +139,14 @@ static inline bool cpus_have_cap(unsigned int num)
 	return test_bit(num, cpu_hwcaps);
 }
 static inline bool cpus_have_const_cap(int num)
 {
 	if (static_branch_likely(&arm64_const_caps_ready))
 		return __cpus_have_const_cap(num);
 	else
 		return cpus_have_cap(num);
 }
 static inline void cpus_set_cap(unsigned int num)
 {
 	if (num >= ARM64_NCAPS) {
@ -145,7 +154,6 @@ static inline void cpus_set_cap(unsigned int num)
 			num, ARM64_NCAPS);
 	} else {
 		__set_bit(num, cpu_hwcaps);
 		static_branch_enable(&cpu_hwcap_keys[num]);
 	}
 }
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@ -24,6 +24,7 @@
 #include <linux/types.h>
 #include <linux/kvm_types.h>
 #include <asm/cpufeature.h>
 #include <asm/kvm.h>
 #include <asm/kvm_asm.h>
 #include <asm/kvm_mmio.h>
@ -355,9 +356,12 @@ static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
 				       unsigned long vector_ptr)
 {
 	/*
-	 * Call initialization code, and switch to the full blown
+	 * Call initialization code, and switch to the full blown HYP code.
-	 * HYP code.
+	 * If the cpucaps haven't been finalized yet, something has gone very
 	 * wrong, and hyp will crash and burn when it uses any
 	 * cpus_have_const_cap() wrapper.
 	 */
 	BUG_ON(!static_branch_likely(&arm64_const_caps_ready));
 	__kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr);
 }
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@ -286,6 +286,10 @@
 #define SCTLR_ELx_A	(1 << 1)
 #define SCTLR_ELx_M	1
 #define SCTLR_EL2_RES1	((1 << 4)  | (1 << 5)  | (1 << 11) | (1 << 16) | \
 			 (1 << 16) | (1 << 18) | (1 << 22) | (1 << 23) | \
 			 (1 << 28) | (1 << 29))
 #define SCTLR_ELx_FLAGS	(SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
 			 SCTLR_ELx_SA | SCTLR_ELx_I)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@ -985,8 +985,16 @@ void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
 */
 void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
 {
-	for (; caps->matches; caps++)
+	for (; caps->matches; caps++) {
-		if (caps->enable && cpus_have_cap(caps->capability))
+		unsigned int num = caps->capability;
 		if (!cpus_have_cap(num))
 			continue;
 		/* Ensure cpus_have_const_cap(num) works */
 		static_branch_enable(&cpu_hwcap_keys[num]);
 		if (caps->enable) {
 			/*
 			 * Use stop_machine() as it schedules the work allowing
 			 * us to modify PSTATE, instead of on_each_cpu() which
@ -994,6 +1002,8 @@ void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
 			 * we return.
 			 */
 			stop_machine(caps->enable, NULL, cpu_online_mask);
 		}
 	}
 }
 /*
@ -1096,6 +1106,14 @@ static void __init setup_feature_capabilities(void)
 	enable_cpu_capabilities(arm64_features);
 }
 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
 EXPORT_SYMBOL(arm64_const_caps_ready);
 static void __init mark_const_caps_ready(void)
 {
 	static_branch_enable(&arm64_const_caps_ready);
 }
 /*
 * Check if the current CPU has a given feature capability.
 * Should be called from non-preemptible context.
@ -1131,6 +1149,7 @@ void __init setup_cpu_features(void)
 	/* Set the CPU feature capabilies */
 	setup_feature_capabilities();
 	enable_errata_workarounds();
 	mark_const_caps_ready();
 	setup_elf_hwcaps(arm64_elf_hwcaps);
 	if (system_supports_32bit_el0())
--- a/arch/arm64/kernel/pci.c
+++ b/arch/arm64/kernel/pci.c
@ -191,8 +191,10 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
 		return NULL;
 	root_ops = kzalloc_node(sizeof(*root_ops), GFP_KERNEL, node);
-	if (!root_ops)
+	if (!root_ops) {
 		kfree(ri);
 		return NULL;
 	}
 	ri->cfg = pci_acpi_setup_ecam_mapping(root);
 	if (!ri->cfg) {
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@ -877,15 +877,24 @@ static int armv8pmu_set_event_filter(struct hw_perf_event *event,
 	if (attr->exclude_idle)
 		return -EPERM;
-	if (is_kernel_in_hyp_mode() &&
+
-	    attr->exclude_kernel != attr->exclude_hv)
+	/*
-		return -EINVAL;
+	 * If we're running in hyp mode, then we *are* the hypervisor.
 	 * Therefore we ignore exclude_hv in this configuration, since
 	 * there's no hypervisor to sample anyway. This is consistent
 	 * with other architectures (x86 and Power).
 	 */
 	if (is_kernel_in_hyp_mode()) {
 		if (!attr->exclude_kernel)
 			config_base |= ARMV8_PMU_INCLUDE_EL2;
 	} else {
 		if (attr->exclude_kernel)
 			config_base |= ARMV8_PMU_EXCLUDE_EL1;
 		if (!attr->exclude_hv)
 			config_base |= ARMV8_PMU_INCLUDE_EL2;
 	}
 	if (attr->exclude_user)
 		config_base |= ARMV8_PMU_EXCLUDE_EL0;
 	if (!is_kernel_in_hyp_mode() && attr->exclude_kernel)
 		config_base |= ARMV8_PMU_EXCLUDE_EL1;
 	if (!attr->exclude_hv)
 		config_base |= ARMV8_PMU_INCLUDE_EL2;
 	/*
 	 * Install the filter into config_base as this is used to
--- a/arch/arm64/kvm/hyp-init.S
+++ b/arch/arm64/kvm/hyp-init.S
@ -106,10 +106,13 @@ __do_hyp_init:
 	tlbi	alle2
 	dsb	sy
-	mrs	x4, sctlr_el2
+	/*
-	and	x4, x4, #SCTLR_ELx_EE	// preserve endianness of EL2
+	 * Preserve all the RES1 bits while setting the default flags,
-	ldr	x5, =SCTLR_ELx_FLAGS
+	 * as well as the EE bit on BE. Drop the A flag since the compiler
-	orr	x4, x4, x5
+	 * is allowed to generate unaligned accesses.
 	 */
 	ldr	x4, =(SCTLR_EL2_RES1 | (SCTLR_ELx_FLAGS & ~SCTLR_ELx_A))
 CPU_BE(	orr	x4, x4, #SCTLR_ELx_EE)
 	msr	sctlr_el2, x4
 	isb
--- a/arch/arm64/kvm/hyp/Makefile
+++ b/arch/arm64/kvm/hyp/Makefile
@ -2,6 +2,8 @@
 # Makefile for Kernel-based Virtual Machine module, HYP part
 #
 ccflags-y += -fno-stack-protector
 KVM=../../../../virt/kvm
 obj-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/hyp/vgic-v2-sr.o
--- a/arch/arm64/kvm/vgic-sys-reg-v3.c
+++ b/arch/arm64/kvm/vgic-sys-reg-v3.c
@ -65,8 +65,8 @@ static bool access_gic_ctlr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 		 * Here set VMCR.CTLR in ICC_CTLR_EL1 layout.
 		 * The vgic_set_vmcr() will convert to ICH_VMCR layout.
 		 */
-		vmcr.ctlr = val & ICC_CTLR_EL1_CBPR_MASK;
+		vmcr.cbpr = (val & ICC_CTLR_EL1_CBPR_MASK) >> ICC_CTLR_EL1_CBPR_SHIFT;
-		vmcr.ctlr |= val & ICC_CTLR_EL1_EOImode_MASK;
+		vmcr.eoim = (val & ICC_CTLR_EL1_EOImode_MASK) >> ICC_CTLR_EL1_EOImode_SHIFT;
 		vgic_set_vmcr(vcpu, &vmcr);
 	} else {
 		val = 0;
@ -83,8 +83,8 @@ static bool access_gic_ctlr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 		 * The VMCR.CTLR value is in ICC_CTLR_EL1 layout.
 		 * Extract it directly using ICC_CTLR_EL1 reg definitions.
 		 */
-		val |= vmcr.ctlr & ICC_CTLR_EL1_CBPR_MASK;
+		val |= (vmcr.cbpr << ICC_CTLR_EL1_CBPR_SHIFT) & ICC_CTLR_EL1_CBPR_MASK;
-		val |= vmcr.ctlr & ICC_CTLR_EL1_EOImode_MASK;
+		val |= (vmcr.eoim << ICC_CTLR_EL1_EOImode_SHIFT) & ICC_CTLR_EL1_EOImode_MASK;
 		p->regval = val;
 	}
@ -135,7 +135,7 @@ static bool access_gic_bpr1(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
 		p->regval = 0;
 	vgic_get_vmcr(vcpu, &vmcr);
-	if (!((vmcr.ctlr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT)) {
+	if (!vmcr.cbpr) {
 		if (p->is_write) {
 			vmcr.abpr = (p->regval & ICC_BPR1_EL1_MASK) >>
 				     ICC_BPR1_EL1_SHIFT;
--- a/arch/arm64/net/bpf_jit_comp.c
+++ b/arch/arm64/net/bpf_jit_comp.c
@ -253,8 +253,9 @@ static int emit_bpf_tail_call(struct jit_ctx *ctx)
 	 */
 	off = offsetof(struct bpf_array, ptrs);
 	emit_a64_mov_i64(tmp, off, ctx);
-	emit(A64_LDR64(tmp, r2, tmp), ctx);
+	emit(A64_ADD(1, tmp, r2, tmp), ctx);
-	emit(A64_LDR64(prg, tmp, r3), ctx);
+	emit(A64_LSL(1, prg, r3, 3), ctx);
 	emit(A64_LDR64(prg, tmp, prg), ctx);
 	emit(A64_CBZ(1, prg, jmp_offset), ctx);
 	/* goto *(prog->bpf_func + prologue_size); */
--- a/arch/cris/boot/dts/include/dt-bindings
+++ b/arch/cris/boot/dts/include/dt-bindings
@ -1 +0,0 @@
 ../../../../../include/dt-bindings
--- a/arch/frv/include/asm/timex.h
+++ b/arch/frv/include/asm/timex.h
@ -16,5 +16,11 @@ static inline cycles_t get_cycles(void)
 #define vxtime_lock()		do {} while (0)
 #define vxtime_unlock()		do {} while (0)
 /* This attribute is used in include/linux/jiffies.h alongside with
 * __cacheline_aligned_in_smp. It is assumed that __cacheline_aligned_in_smp
 * for frv does not contain another section specification.
 */
 #define __jiffy_arch_data	__attribute__((__section__(".data")))
 #endif
--- a/arch/hexagon/mm/uaccess.c
+++ b/arch/hexagon/mm/uaccess.c
@ -37,15 +37,14 @@ __kernel_size_t __clear_user_hexagon(void __user *dest, unsigned long count)
 	long uncleared;
 	while (count > PAGE_SIZE) {
-		uncleared = __copy_to_user_hexagon(dest, &empty_zero_page,
+		uncleared = raw_copy_to_user(dest, &empty_zero_page, PAGE_SIZE);
 						PAGE_SIZE);
 		if (uncleared)
 			return count - (PAGE_SIZE - uncleared);
 		count -= PAGE_SIZE;
 		dest += PAGE_SIZE;
 	}
 	if (count)
-		count = __copy_to_user_hexagon(dest, &empty_zero_page, count);
+		count = raw_copy_to_user(dest, &empty_zero_page, count);
 	return count;
 }
--- a/arch/metag/boot/dts/include/dt-bindings
+++ b/arch/metag/boot/dts/include/dt-bindings
@ -1 +0,0 @@
 ../../../../../include/dt-bindings
--- a/arch/mips/boot/dts/include/dt-bindings
+++ b/arch/mips/boot/dts/include/dt-bindings
@ -1 +0,0 @@
 ../../../../../include/dt-bindings
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@ -120,7 +120,6 @@ int copy_thread_tls(unsigned long clone_flags, unsigned long usp,
 	struct thread_info *ti = task_thread_info(p);
 	struct pt_regs *childregs, *regs = current_pt_regs();
 	unsigned long childksp;
 	p->set_child_tid = p->clear_child_tid = NULL;
 	childksp = (unsigned long)task_stack_page(p) + THREAD_SIZE - 32;
--- a/arch/openrisc/kernel/process.c
+++ b/arch/openrisc/kernel/process.c
@ -167,8 +167,6 @@ copy_thread(unsigned long clone_flags, unsigned long usp,
 	top_of_kernel_stack = sp;
 	p->set_child_tid = p->clear_child_tid = NULL;
 	/* Locate userspace context on stack... */
 	sp -= STACK_FRAME_OVERHEAD;	/* redzone */
 	sp -= sizeof(struct pt_regs);
--- a/Show more
+++ b/Show more