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LoongArch: Derive timer max_delta from PRCFG1's timer_bits
As per arch spec, maximum timer bits is configurable and should not be hardcoded in any way. Probe timer bits from PRCFG1 and use that to determine the clockevent's max_delta to be conformance. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
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341cf992d3
commit
98e720f77d
4 changed files with 3 additions and 2 deletions
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@ -57,6 +57,7 @@ struct cpuinfo_loongarch {
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int global_id; /* physical global thread number */
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int vabits; /* Virtual Address size in bits */
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int pabits; /* Physical Address size in bits */
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int timerbits; /* Width of arch timer in bits */
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unsigned int ksave_mask; /* Usable KSave mask. */
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unsigned int watch_dreg_count; /* Number data breakpoints */
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unsigned int watch_ireg_count; /* Number instruction breakpoints */
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@ -466,7 +466,6 @@
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#define LOONGARCH_CSR_TCFG 0x41 /* Timer config */
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#define CSR_TCFG_VAL_SHIFT 2
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#define CSR_TCFG_VAL_WIDTH 48
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#define CSR_TCFG_VAL (_ULCAST_(0x3fffffffffff) << CSR_TCFG_VAL_SHIFT)
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#define CSR_TCFG_PERIOD_SHIFT 1
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#define CSR_TCFG_PERIOD (_ULCAST_(0x1) << CSR_TCFG_PERIOD_SHIFT)
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@ -190,6 +190,7 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
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set_cpu_asid_mask(c, asid_mask);
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config = read_csr_prcfg1();
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c->timerbits = (config & CSR_CONF1_TMRBITS) >> CSR_CONF1_TMRBITS_SHIFT;
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c->ksave_mask = GENMASK((config & CSR_CONF1_KSNUM) - 1, 0);
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c->ksave_mask &= ~(EXC_KSAVE_MASK | PERCPU_KSAVE_MASK | KVM_KSAVE_MASK);
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@ -132,7 +132,7 @@ int constant_clockevent_init(void)
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#else
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unsigned long min_delta = 1000;
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#endif
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unsigned long max_delta = (1UL << 48) - 1;
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unsigned long max_delta = GENMASK_ULL(boot_cpu_data.timerbits, 0);
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struct clock_event_device *cd;
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static int irq = 0, timer_irq_installed = 0;
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