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Memory controller drivers for v6.17

Browse source 
1. Several cleanups: Use dev_fwnode() in OMAP GPMX, convert
    arm,pl172.txt DT bindings to DT schema, use
    syscon_regmap_lookup_by_phandle_args() wrapper, correct kerneldoc.
 
 2. Mediatek MT8186 SMI: Extend hardware bandwidth limits to fix VENC
    hardware during stress testing.
 
 3. Broadcom brcmstb_memc: Add additional fallback compatible and
    simplify device driver matching.  The change comes from Broadcom
    SoC maintainer (Florian Fainelli), thus its ABI impact is
    acknowledged.
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Merge tag 'memory-controller-drv-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers

Memory controller drivers for v6.17

1. Several cleanups: Use dev_fwnode() in OMAP GPMX, convert
   arm,pl172.txt DT bindings to DT schema, use
   syscon_regmap_lookup_by_phandle_args() wrapper, correct kerneldoc.

2. Mediatek MT8186 SMI: Extend hardware bandwidth limits to fix VENC
   hardware during stress testing.

3. Broadcom brcmstb_memc: Add additional fallback compatible and
   simplify device driver matching.  The change comes from Broadcom
   SoC maintainer (Florian Fainelli), thus its ABI impact is
   acknowledged.

* tag 'memory-controller-drv-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  dt-bindings: memory: renesas,rzg3e-xspi: Document RZ/V2H(P) and RZ/V2N support
  memory: brcmstb_memc: Simplify compatible matching
  dt-bindings: memory-controller: Define fallback compatible
  memory: omap-gpmx: Use dev_fwnode()
  memory: mtk-smi: Add ostd setting for mt8186
  dt-bindings: memory-controllers: convert arm,pl172.txt to yaml format
  memory: stm32_omm: Use syscon_regmap_lookup_by_phandle_args
  memory: emif: Add missing kerneldoc for lpmode

Link: https://lore.kernel.org/r/20250715095315.59299-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2025-07-22 22:46:59 +02:00
commit 9841d92754
9 changed files with 308 additions and 219 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

127
Documentation/devicetree/bindings/memory-controllers/arm,pl172.txt
View file

@ -1,127 +0,0 @@
* Device tree bindings for ARM PL172/PL175/PL176 MultiPort Memory Controller
Required properties:
- compatible: Must be "arm,primecell" and exactly one from
"arm,pl172", "arm,pl175" or "arm,pl176".
- reg: Must contains offset/length value for controller.
- #address-cells: Must be 2. The partition number has to be encoded in the
first address cell and it may accept values 0..N-1
(N - total number of partitions). The second cell is the
offset into the partition.
- #size-cells: Must be set to 1.
- ranges: Must contain one or more chip select memory regions.
- clocks: Must contain references to controller clocks.
- clock-names: Must contain "mpmcclk" and "apb_pclk".
- clock-ranges: Empty property indicating that child nodes can inherit
named clocks. Required only if clock tree data present
in device tree.
See clock-bindings.txt
Child chip-select (cs) nodes contain the memory devices nodes connected to
such as NOR (e.g. cfi-flash) and NAND.
Required child cs node properties:
- #address-cells: Must be 2.
- #size-cells: Must be 1.
- ranges: Empty property indicating that child nodes can inherit
memory layout.
- clock-ranges: Empty property indicating that child nodes can inherit
named clocks. Required only if clock tree data present
in device tree.
- mpmc,cs: Chip select number. Indicates to the pl0172 driver
which chipselect is used for accessing the memory.
- mpmc,memory-width: Width of the chip select memory. Must be equal to
either 8, 16 or 32.
Optional child cs node config properties:
- mpmc,async-page-mode: Enable asynchronous page mode.
- mpmc,cs-active-high: Set chip select polarity to active high.
- mpmc,byte-lane-low: Set byte lane state to low.
- mpmc,extended-wait: Enable extended wait.
- mpmc,buffer-enable: Enable write buffer, option is not supported by
PL175 and PL176 controllers.
- mpmc,write-protect: Enable write protect.
Optional child cs node timing properties:
- mpmc,write-enable-delay: Delay from chip select assertion to write
enable (WE signal) in nano seconds.
- mpmc,output-enable-delay: Delay from chip select assertion to output
enable (OE signal) in nano seconds.
- mpmc,write-access-delay: Delay from chip select assertion to write
access in nano seconds.
- mpmc,read-access-delay: Delay from chip select assertion to read
access in nano seconds.
- mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential
accesses in nano seconds.
- mpmc,turn-round-delay: Delay between access to memory banks in nano
seconds.
If any of the above timing parameters are absent, current parameter value will
be taken from the corresponding HW reg.
Example for pl172 with nor flash on chip select 0 shown below.
emc: memory-controller@40005000 {
compatible = "arm,pl172", "arm,primecell";
reg = <0x40005000 0x1000>;
clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
clock-names = "mpmcclk", "apb_pclk";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x1c000000 0x1000000
1 0 0x1d000000 0x1000000
2 0 0x1e000000 0x1000000
3 0 0x1f000000 0x1000000>;
cs0 {
#address-cells = <2>;
#size-cells = <1>;
ranges;
mpmc,cs = <0>;
mpmc,memory-width = <16>;
mpmc,byte-lane-low;
mpmc,write-enable-delay = <0>;
mpmc,output-enable-delay = <0>;
mpmc,read-enable-delay = <70>;
mpmc,page-mode-read-delay = <70>;
flash@0,0 {
compatible = "sst,sst39vf320", "cfi-flash";
reg = <0 0 0x400000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "data";
reg = <0 0x400000>;
};
};
};
};

222
Documentation/devicetree/bindings/memory-controllers/arm,pl172.yaml Normal file
View file

@ -0,0 +1,222 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/arm,pl172.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM PL172/PL175/PL176 MultiPort Memory Controller
maintainers:
- Frank Li <Frank.Li@nxp.com>
# We need a select here so we don't match all nodes with 'arm,primecell'
select:
properties:
compatible:
contains:
enum:
- arm,pl172
- arm,pl175
- arm,pl176
required:
- compatible
properties:
compatible:
items:
- enum:
- arm,pl172
- arm,pl175
- arm,pl176
- const: arm,primecell
reg:
maxItems: 1
'#address-cells':
const: 2
'#size-cells':
const: 1
ranges: true
clocks:
maxItems: 2
clock-names:
items:
- const: mpmcclk
- const: apb_pclk
clock-ranges: true
resets:
maxItems: 1
patternProperties:
"^cs[0-9]$":
type: object
additionalProperties: false
patternProperties:
"^flash@[0-9],[0-9a-f]+$":
type: object
$ref: /schemas/mtd/mtd-physmap.yaml#
unevaluatedProperties: false
"^(gpio|sram)@[0-9],[0-9a-f]+$":
type: object
additionalProperties: true
properties:
'#address-cells':
const: 2
'#size-cells':
const: 1
ranges: true
clocks:
maxItems: 2
clock-ranges: true
mpmc,cs:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Chip select number. Indicates to the pl0172 driver
which chipselect is used for accessing the memory.
mpmc,memory-width:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8, 16, 32]
description:
Width of the chip select memory. Must be equal to either 8, 16 or 32.
mpmc,async-page-mode:
$ref: /schemas/types.yaml#/definitions/flag
description:
Enable asynchronous page mode.
mpmc,cs-active-high:
$ref: /schemas/types.yaml#/definitions/flag
description:
Set chip select polarity to active high.
mpmc,byte-lane-low:
$ref: /schemas/types.yaml#/definitions/flag
description:
Set byte lane state to low.
mpmc,extended-wait:
$ref: /schemas/types.yaml#/definitions/flag
description:
Enable extended wait.
mpmc,buffer-enable:
$ref: /schemas/types.yaml#/definitions/flag
description:
Enable write buffer, option is not supported by
PL175 and PL176 controllers.
mpmc,write-protect:
$ref: /schemas/types.yaml#/definitions/flag
description:
Enable write protect.
mpmc,read-enable-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Delay from chip select assertion to read
enable (RE signal) in nano seconds.
mpmc,write-enable-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Delay from chip select assertion to write
enable (WE signal) in nano seconds.
mpmc,output-enable-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Delay from chip select assertion to output
enable (OE signal) in nano seconds.
mpmc,write-access-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Delay from chip select assertion to write
access in nano seconds.
mpmc,read-access-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Delay from chip select assertion to read
access in nano seconds.
mpmc,page-mode-read-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Delay for asynchronous page mode sequential
accesses in nano seconds.
mpmc,turn-round-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Delay between access to memory banks in nano
seconds.
required:
- compatible
- reg
- '#address-cells'
- '#size-cells'
- ranges
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/lpc18xx-ccu.h>
memory-controller@40005000 {
compatible = "arm,pl172", "arm,primecell";
reg = <0x40005000 0x1000>;
clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
clock-names = "mpmcclk", "apb_pclk";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x1c000000 0x1000000
1 0 0x1d000000 0x1000000
2 0 0x1e000000 0x1000000
3 0 0x1f000000 0x1000000>;
cs0 {
#address-cells = <2>;
#size-cells = <1>;
ranges;
mpmc,cs = <0>;
mpmc,memory-width = <16>;
mpmc,byte-lane-low;
mpmc,write-enable-delay = <0>;
mpmc,output-enable-delay = <0>;
mpmc,read-enable-delay = <70>;
mpmc,page-mode-read-delay = <70>;
flash@0,0 {
compatible = "sst,sst39vf320", "cfi-flash";
reg = <0 0 0x400000>;
bank-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "data";
reg = <0 0x400000>;
};
};
};
};

54
Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml
View file

@ -11,25 +11,37 @@ maintainers:
properties:
compatible:
items:
- enum:
- brcm,brcmstb-memc-ddr-rev-b.1.x
- brcm,brcmstb-memc-ddr-rev-b.2.0
- brcm,brcmstb-memc-ddr-rev-b.2.1
- brcm,brcmstb-memc-ddr-rev-b.2.2
- brcm,brcmstb-memc-ddr-rev-b.2.3
- brcm,brcmstb-memc-ddr-rev-b.2.5
- brcm,brcmstb-memc-ddr-rev-b.2.6
- brcm,brcmstb-memc-ddr-rev-b.2.7
- brcm,brcmstb-memc-ddr-rev-b.2.8
- brcm,brcmstb-memc-ddr-rev-b.3.0
- brcm,brcmstb-memc-ddr-rev-b.3.1
- brcm,brcmstb-memc-ddr-rev-c.1.0
- brcm,brcmstb-memc-ddr-rev-c.1.1
- brcm,brcmstb-memc-ddr-rev-c.1.2
- brcm,brcmstb-memc-ddr-rev-c.1.3
- brcm,brcmstb-memc-ddr-rev-c.1.4
- const: brcm,brcmstb-memc-ddr
oneOf:
- description: Revision > 2.1 controllers
items:
- enum:
- brcm,brcmstb-memc-ddr-rev-b.2.2
- brcm,brcmstb-memc-ddr-rev-b.2.3
- brcm,brcmstb-memc-ddr-rev-b.2.5
- brcm,brcmstb-memc-ddr-rev-b.2.6
- brcm,brcmstb-memc-ddr-rev-b.2.7
- brcm,brcmstb-memc-ddr-rev-b.2.8
- brcm,brcmstb-memc-ddr-rev-b.3.0
- brcm,brcmstb-memc-ddr-rev-b.3.1
- brcm,brcmstb-memc-ddr-rev-c.1.0
- brcm,brcmstb-memc-ddr-rev-c.1.1
- brcm,brcmstb-memc-ddr-rev-c.1.2
- brcm,brcmstb-memc-ddr-rev-c.1.3
- brcm,brcmstb-memc-ddr-rev-c.1.4
- const: brcm,brcmstb-memc-ddr-rev-b.2.1
- const: brcm,brcmstb-memc-ddr
- description: Revision 2.1 controllers
items:
- const: brcm,brcmstb-memc-ddr-rev-b.2.1
- const: brcm,brcmstb-memc-ddr
- description: Revision 2.0 controllers
items:
- const: brcm,brcmstb-memc-ddr-rev-b.2.0
- const: brcm,brcmstb-memc-ddr
- description: Revision 1.x controllers
items:
- const: brcm,brcmstb-memc-ddr-rev-b.1.x
- const: brcm,brcmstb-memc-ddr
reg:
maxItems: 1
@ -46,7 +58,9 @@ additionalProperties: false
examples:
- |
memory-controller@9902000 {
compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1", "brcm,brcmstb-memc-ddr";
compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1",
"brcm,brcmstb-memc-ddr-rev-b.2.1",
"brcm,brcmstb-memc-ddr";
reg = <0x9902000 0x600>;
clock-frequency = <2133000000>;
};

9
Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml
View file

@ -23,7 +23,14 @@ allOf:
properties:
compatible:
const: renesas,r9a09g047-xspi # RZ/G3E
oneOf:
- const: renesas,r9a09g047-xspi # RZ/G3E
- items:
- enum:
- renesas,r9a09g056-xspi # RZ/V2N
- renesas,r9a09g057-xspi # RZ/V2H(P)
- const: renesas,r9a09g047-xspi
reg:
items:

56
drivers/memory/brcmstb_memc.c
View file

@ -184,62 +184,10 @@ static const struct of_device_id brcmstb_memc_of_match[] = {
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.5",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.6",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.7",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.2.8",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-b.3.1",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.0",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.1",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.2",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.3",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{
.compatible = "brcm,brcmstb-memc-ddr-rev-c.1.4",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
/* default to the original offset */
/* default to the V21 offset */
{
.compatible = "brcm,brcmstb-memc-ddr",
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V1X]
.data = &brcmstb_memc_versions[BRCMSTB_MEMC_V21]
},
{}
};

1
drivers/memory/emif.c
View file

@ -39,6 +39,7 @@
* are two devices attached to this EMIF, this
* value is the maximum of the two temperature
* levels.
* @lpmode: Chosen low power mode
* @node: node in the device list
* @base: base address of memory-mapped IO registers.
* @dev: device pointer.

33
drivers/memory/mtk-smi.c
View file

@ -320,6 +320,38 @@ static const u8 mtk_smi_larb_mt6893_ostd[][SMI_LARB_PORT_NR_MAX] = {
[20] = {0x9, 0x9, 0x5, 0x5, 0x1, 0x1},
};
static const u8 mtk_smi_larb_mt8186_ostd[][SMI_LARB_PORT_NR_MAX] = {
[0] = {0x2, 0x1, 0x8, 0x1,},
[1] = {0x1, 0x3, 0x1, 0x1,},
[2] = {0x6, 0x1, 0x4, 0x1,},
[3] = {},
[4] = {0xf, 0x1, 0x5, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
0x1, 0x1, 0x1,},
[5] = {},
[6] = {},
[7] = {0x1, 0x3, 0x1, 0x1, 0x1, 0x3, 0x2, 0xd, 0x7, 0x5, 0x3,
0x1, 0x5,},
[8] = {0x1, 0x2, 0x2,},
[9] = {0x9, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0xb, 0x7, 0x4,
0x9, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
0x1, 0x1, 0x1, 0x1, 0x1,},
[10] = {},
[11] = {0x9, 0x7, 0xf, 0x8, 0x1, 0x8, 0x9, 0x3, 0x3, 0xb, 0x7, 0x4,
0x9, 0x1, 0x1, 0x1, 0x1, 0x1, 0x8, 0x7, 0x7, 0x1, 0x6, 0x2,
0xf, 0x8, 0x1, 0x1, 0x1,},
[12] = {},
[13] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x6, 0x6, 0x6, 0x1, 0x1, 0x1,},
[14] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1,},
[15] = {},
[16] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x1, 0x14, 0x1, 0x4, 0x4, 0x4,
0x2, 0x4, 0x2, 0x8, 0x4, 0x4,},
[17] = {0x28, 0x14, 0x2, 0xc, 0x18, 0x1, 0x14, 0x1, 0x4, 0x4, 0x4,
0x2, 0x4, 0x2, 0x8, 0x4, 0x4,},
[18] = {},
[19] = {0x1, 0x1, 0x1, 0x1,},
[20] = {0x2, 0x2, 0x2, 0x2, 0x1, 0x1,},
};
static const u8 mtk_smi_larb_mt8188_ostd[][SMI_LARB_PORT_NR_MAX] = {
[0] = {0x02, 0x18, 0x22, 0x22, 0x01, 0x02, 0x0a,},
[1] = {0x12, 0x02, 0x14, 0x14, 0x01, 0x18, 0x0a,},
@ -491,6 +523,7 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = {
.config_port = mtk_smi_larb_config_port_gen2_general,
.flags_general = MTK_SMI_FLAG_SLEEP_CTL,
.ostd = mtk_smi_larb_mt8186_ostd,
};
static const struct mtk_smi_larb_gen mtk_smi_larb_mt8188 = {

4
drivers/memory/omap-gpmc.c
View file

@ -1455,8 +1455,8 @@ static int gpmc_setup_irq(struct gpmc_device *gpmc)
gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
gpmc_irq_domain = irq_domain_create_linear(of_fwnode_handle(gpmc->dev->of_node),
gpmc->nirqs, &gpmc_irq_domain_ops, gpmc);
gpmc_irq_domain = irq_domain_create_linear(dev_fwnode(gpmc->dev), gpmc->nirqs,
&gpmc_irq_domain_ops, gpmc);
if (!gpmc_irq_domain) {
dev_err(gpmc->dev, "IRQ domain add failed\n");
return -ENODEV;

21
drivers/memory/stm32_omm.c
View file

@ -46,7 +46,7 @@ static int stm32_omm_set_amcr(struct device *dev, bool set)
struct regmap *syscfg_regmap;
struct device_node *node;
struct resource res, res1;
u32 amcr_base, amcr_mask;
unsigned int syscon_args[2];
int ret, idx;
unsigned int i, amcr, read_amcr;
@ -98,29 +98,20 @@ static int stm32_omm_set_amcr(struct device *dev, bool set)
of_node_put(node);
}
syscfg_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "st,syscfg-amcr");
syscfg_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, "st,syscfg-amcr",
2, syscon_args);
if (IS_ERR(syscfg_regmap))
return dev_err_probe(dev, PTR_ERR(syscfg_regmap),
"Failed to get st,syscfg-amcr property\n");
ret = of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 1,
&amcr_base);
if (ret)
return ret;
ret = of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 2,
&amcr_mask);
if (ret)
return ret;
amcr = mm_ospi2_size / SZ_64M;
if (set)
regmap_update_bits(syscfg_regmap, amcr_base, amcr_mask, amcr);
regmap_update_bits(syscfg_regmap, syscon_args[0], syscon_args[1], amcr);
/* read AMCR and check coherency with memory-map areas defined in DT */
regmap_read(syscfg_regmap, amcr_base, &read_amcr);
read_amcr = read_amcr >> (ffs(amcr_mask) - 1);
regmap_read(syscfg_regmap, syscon_args[0], &read_amcr);
read_amcr = read_amcr >> (ffs(syscon_args[1]) - 1);
if (amcr != read_amcr) {
dev_err(dev, "AMCR value not coherent with DT memory-map areas\n");