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ASoC: SOF: amd: add interrupt handling for SoundWire manager devices
Add support for interrupt handling for soundwire manager platform devices. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com> Link: https://msgid.link/r/20240129055147.1493853-9-Vijendar.Mukunda@amd.com Signed-off-by: Mark Brown <broonie@kernel.org>
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d948218424
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3 changed files with 46 additions and 1 deletions
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@ -78,6 +78,10 @@
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#define ACP5X_AXI2DAGB_SEM_0 0x1884
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#define ACP5X_AXI2DAGB_SEM_0 0x1884
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#define ACP6X_AXI2DAGB_SEM_0 0x1874
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#define ACP6X_AXI2DAGB_SEM_0 0x1874
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/* ACP common registers to report errors related to I2S & SoundWire interfaces */
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#define ACP_SW0_I2S_ERROR_REASON 0x18B4
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#define ACP_SW1_I2S_ERROR_REASON 0x1A50
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/* Registers from ACP_SHA block */
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/* Registers from ACP_SHA block */
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#define ACP_SHA_DSP_FW_QUALIFIER 0x1C70
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#define ACP_SHA_DSP_FW_QUALIFIER 0x1C70
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#define ACP_SHA_DMA_CMD 0x1CB0
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#define ACP_SHA_DMA_CMD 0x1CB0
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@ -375,10 +375,13 @@ static irqreturn_t acp_irq_thread(int irq, void *context)
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static irqreturn_t acp_irq_handler(int irq, void *dev_id)
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static irqreturn_t acp_irq_handler(int irq, void *dev_id)
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{
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{
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struct amd_sdw_manager *amd_manager;
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struct snd_sof_dev *sdev = dev_id;
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struct snd_sof_dev *sdev = dev_id;
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const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
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const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
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struct acp_dev_data *adata = sdev->pdata->hw_pdata;
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unsigned int base = desc->dsp_intr_base;
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unsigned int base = desc->dsp_intr_base;
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unsigned int val;
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unsigned int val;
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int irq_flag = 0;
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val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET);
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val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET);
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if (val & ACP_DSP_TO_HOST_IRQ) {
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if (val & ACP_DSP_TO_HOST_IRQ) {
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@ -387,6 +390,37 @@ static irqreturn_t acp_irq_handler(int irq, void *dev_id)
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return IRQ_WAKE_THREAD;
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return IRQ_WAKE_THREAD;
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}
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}
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val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat);
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if (val & ACP_SDW0_IRQ_MASK) {
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amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_SDW0_IRQ_MASK);
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if (amd_manager)
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schedule_work(&amd_manager->amd_sdw_irq_thread);
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irq_flag = 1;
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}
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if (val & ACP_ERROR_IRQ_MASK) {
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW0_I2S_ERROR_REASON, 0);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_SW1_I2S_ERROR_REASON, 0);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + ACP_ERROR_STATUS, 0);
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irq_flag = 1;
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}
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if (desc->ext_intr_stat1) {
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val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1);
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if (val & ACP_SDW1_IRQ_MASK) {
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amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1,
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ACP_SDW1_IRQ_MASK);
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if (amd_manager)
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schedule_work(&amd_manager->amd_sdw_irq_thread);
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irq_flag = 1;
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}
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}
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if (irq_flag)
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return IRQ_HANDLED;
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else
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return IRQ_NONE;
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return IRQ_NONE;
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}
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}
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@ -443,6 +477,8 @@ static int acp_reset(struct snd_sof_dev *sdev)
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if (desc->ext_intr_enb)
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if (desc->ext_intr_enb)
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01);
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01);
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if (desc->ext_intr_cntl)
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snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK);
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return ret;
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return ret;
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}
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}
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@ -93,6 +93,9 @@
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#define PROBE_STATUS_BIT BIT(31)
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#define PROBE_STATUS_BIT BIT(31)
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#define ACP_FIRMWARE_SIGNATURE 0x100
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#define ACP_FIRMWARE_SIGNATURE 0x100
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#define ACP_ERROR_IRQ_MASK BIT(29)
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#define ACP_SDW0_IRQ_MASK BIT(21)
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#define ACP_SDW1_IRQ_MASK BIT(2)
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#define ACP_DEFAULT_SRAM_LENGTH 0x00080000
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#define ACP_DEFAULT_SRAM_LENGTH 0x00080000
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#define ACP_SRAM_PAGE_COUNT 128
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#define ACP_SRAM_PAGE_COUNT 128
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@ -184,7 +187,9 @@ struct sof_amd_acp_desc {
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unsigned int host_bridge_id;
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unsigned int host_bridge_id;
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u32 pgfsm_base;
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u32 pgfsm_base;
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u32 ext_intr_enb;
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u32 ext_intr_enb;
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u32 ext_intr_cntl;
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u32 ext_intr_stat;
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u32 ext_intr_stat;
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u32 ext_intr_stat1;
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u32 dsp_intr_base;
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u32 dsp_intr_base;
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u32 sram_pte_offset;
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u32 sram_pte_offset;
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u32 hw_semaphore_offset;
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u32 hw_semaphore_offset;
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