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dt-bindings: msm/mdp4: convert to yaml format

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Convert mdp4 binding into yaml format.

Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220109171814.16103-1-david@ixit.cz
This commit is contained in:
David Heidelberg 2022-01-09 18:18:13 +01:00 • committed by Rob Herring
parent 066aef6907
commit 92649241a2
2 changed files with 124 additions and 114 deletions
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114
Documentation/devicetree/bindings/display/msm/mdp4.txt
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Qualcomm adreno/snapdragon MDP4 display controller
Description:
This is the bindings documentation for the MDP4 display controller found in
SoCs like MSM8960, APQ8064 and MSM8660.
Required properties:
- compatible:
* "qcom,mdp4" - mdp4
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt signal from the display controller.
- clocks: device clocks
See ../clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required.
* "core_clk"
* "iface_clk"
* "bus_clk"
* "lut_clk"
* "hdmi_clk"
* "tv_clk"
- ports: contains the list of output ports from MDP. These connect to interfaces
that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
special case since it is a part of the MDP block itself).
Each output port contains an endpoint that describes how it is connected to an
external interface. These are described by the standard properties documented
here:
Documentation/devicetree/bindings/graph.txt
Documentation/devicetree/bindings/media/video-interfaces.txt
The output port mappings are:
Port 0 -> LCDC/LVDS
Port 1 -> DSI1 Cmd/Video
Port 2 -> DSI2 Cmd/Video
Port 3 -> DTV
Optional properties:
- clock-names: the following clocks are optional:
* "lut_clk"
- qcom,lcdc-align-lsb: Boolean value indicating that LSB alignment should be
used for LCDC. This is only valid for 18bpp panels.
Example:
/ {
...
hdmi: hdmi@4a00000 {
...
ports {
...
port@0 {
reg = <0>;
hdmi_in: endpoint {
remote-endpoint = <&mdp_dtv_out>;
};
};
...
};
...
};
...
mdp: mdp@5100000 {
compatible = "qcom,mdp4";
reg = <0x05100000 0xf0000>;
interrupts = <GIC_SPI 75 0>;
clock-names =
"core_clk",
"iface_clk",
"lut_clk",
"hdmi_clk",
"tv_clk";
clocks =
<&mmcc MDP_CLK>,
<&mmcc MDP_AHB_CLK>,
<&mmcc MDP_AXI_CLK>,
<&mmcc MDP_LUT_CLK>,
<&mmcc HDMI_TV_CLK>,
<&mmcc MDP_TV_CLK>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdp_lvds_out: endpoint {
};
};
port@1 {
reg = <1>;
mdp_dsi1_out: endpoint {
};
};
port@2 {
reg = <2>;
mdp_dsi2_out: endpoint {
};
};
port@3 {
reg = <3>;
mdp_dtv_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
};
};

124
Documentation/devicetree/bindings/display/msm/mdp4.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/msm/mdp4.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Adreno/Snapdragon MDP4 display controller
description: >
MDP4 display controller found in SoCs like MSM8960, APQ8064 and MSM8660.
maintainers:
- Rob Clark <robdclark@gmail.com>
properties:
compatible:
const: qcom,mdp4
clocks:
minItems: 6
maxItems: 6
clock-names:
items:
- const: core_clk
- const: iface_clk
- const: bus_clk
- const: lut_clk
- const: hdmi_clk
- const: tv_clk
reg:
maxItems: 1
interrupts:
maxItems: 1
iommus:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: LCDC/LVDS
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: DSI1 Cmd / Video
port@2:
$ref: /schemas/graph.yaml#/properties/port
description: DSI2 Cmd / Video
port@3:
$ref: /schemas/graph.yaml#/properties/port
description: Digital TV
qcom,lcdc-align-lsb:
type: boolean
description: >
Indication that LSB alignment should be used for LCDC.
This is only valid for 18bpp panels.
required:
- compatible
- reg
- clocks
- ports
additionalProperties: false
examples:
- |
mdp: mdp@5100000 {
compatible = "qcom,mdp4";
reg = <0x05100000 0xf0000>;
interrupts = <0 75 0>;
clock-names =
"core_clk",
"iface_clk",
"bus_clk",
"lut_clk",
"hdmi_clk",
"tv_clk";
clocks =
<&mmcc 77>,
<&mmcc 86>,
<&mmcc 102>,
<&mmcc 75>,
<&mmcc 97>,
<&mmcc 12>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdp_lvds_out: endpoint {
};
};
port@1 {
reg = <1>;
mdp_dsi1_out: endpoint {
};
};
port@2 {
reg = <2>;
mdp_dsi2_out: endpoint {
};
};
port@3 {
reg = <3>;
mdp_dtv_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
};