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media: ipu6: fix the wrong type casting and 64-bit division

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This patch fixes the build errors with `i386-allmodconfig`, the
errors are caused by wrong type casting and 64-bit division.

Signed-off-by: Bingbu Cao <bingbu.cao@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
Bingbu Cao 2024-10-09 13:20:30 +08:00 • committed by Mauro Carvalho Chehab
parent afdb1f1fef
commit 92271cec68
7 changed files with 18 additions and 17 deletions
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6
drivers/media/pci/intel/ipu6/ipu6-cpd.c
View file

@ -43,9 +43,9 @@
* 63:56 55 54:48 47:32 31:24 23:0
* Rsvd Rsvd Type Version Rsvd Size
*/
#define PKG_DIR_SIZE_MASK GENMASK(23, 0)
#define PKG_DIR_VERSION_MASK GENMASK(47, 32)
#define PKG_DIR_TYPE_MASK GENMASK(54, 48)
#define PKG_DIR_SIZE_MASK GENMASK_ULL(23, 0)
#define PKG_DIR_VERSION_MASK GENMASK_ULL(47, 32)
#define PKG_DIR_TYPE_MASK GENMASK_ULL(54, 48)
static inline const struct ipu6_cpd_ent *ipu6_cpd_get_entry(const void *cpd,
u8 idx)

8
drivers/media/pci/intel/ipu6/ipu6-fw-com.c
View file

@ -242,7 +242,7 @@ void *ipu6_fw_com_prepare(struct ipu6_fw_com_cfg *cfg,
/* initialize input queues */
offset += specific_size;
res.reg = SYSCOM_QPR_BASE_REG;
res.host_address = (u64)(ctx->dma_buffer + offset);
res.host_address = (uintptr_t)(ctx->dma_buffer + offset);
res.vied_address = ctx->dma_addr + offset;
for (i = 0; i < cfg->num_input_queues; i++)
ipu6_sys_queue_init(ctx->input_queue + i,
@ -251,7 +251,7 @@ void *ipu6_fw_com_prepare(struct ipu6_fw_com_cfg *cfg,
/* initialize output queues */
offset += sizeinput;
res.host_address = (u64)(ctx->dma_buffer + offset);
res.host_address = (uintptr_t)(ctx->dma_buffer + offset);
res.vied_address = ctx->dma_addr + offset;
for (i = 0; i < cfg->num_output_queues; i++) {
ipu6_sys_queue_init(ctx->output_queue + i,
@ -358,7 +358,7 @@ void *ipu6_send_get_token(struct ipu6_fw_com_context *ctx, int q_nbr)
index = readl(q_dmem + FW_COM_WR_REG);
return (void *)(q->host_address + index * q->token_size);
return (void *)((uintptr_t)q->host_address + index * q->token_size);
}
EXPORT_SYMBOL_NS_GPL(ipu6_send_get_token, INTEL_IPU6);
@ -395,7 +395,7 @@ void *ipu6_recv_get_token(struct ipu6_fw_com_context *ctx, int q_nbr)
if (!packets)
return NULL;
return (void *)(q->host_address + rd * q->token_size);
return (void *)((uintptr_t)q->host_address + rd * q->token_size);
}
EXPORT_SYMBOL_NS_GPL(ipu6_recv_get_token, INTEL_IPU6);

4
drivers/media/pci/intel/ipu6/ipu6-isys-dwc-phy.c
View file

@ -67,7 +67,7 @@ static void dwc_dphy_write(struct ipu6_isys *isys, u32 phy_id, u32 addr,
void __iomem *isys_base = isys->pdata->base;
void __iomem *base = isys_base + IPU6_DWC_DPHY_BASE(phy_id);
dev_dbg(dev, "write: reg 0x%lx = data 0x%x", base + addr - isys_base,
dev_dbg(dev, "write: reg 0x%zx = data 0x%x", base + addr - isys_base,
data);
writel(data, base + addr);
}
@ -80,7 +80,7 @@ static u32 dwc_dphy_read(struct ipu6_isys *isys, u32 phy_id, u32 addr)
u32 data;
data = readl(base + addr);
dev_dbg(dev, "read: reg 0x%lx = data 0x%x", base + addr - isys_base,
dev_dbg(dev, "read: reg 0x%zx = data 0x%x", base + addr - isys_base,
data);
return data;

6
drivers/media/pci/intel/ipu6/ipu6-isys-video.c
View file

@ -543,7 +543,7 @@ static int start_stream_firmware(struct ipu6_isys_video *av,
ret = ipu6_isys_fw_pin_cfg(__av, stream_cfg);
if (ret < 0) {
ipu6_put_fw_msg_buf(av->isys, (u64)stream_cfg);
ipu6_put_fw_msg_buf(av->isys, (uintptr_t)stream_cfg);
return ret;
}
}
@ -560,7 +560,7 @@ static int start_stream_firmware(struct ipu6_isys_video *av,
IPU6_FW_ISYS_SEND_TYPE_STREAM_OPEN);
if (ret < 0) {
dev_err(dev, "can't open stream (%d)\n", ret);
ipu6_put_fw_msg_buf(av->isys, (u64)stream_cfg);
ipu6_put_fw_msg_buf(av->isys, (uintptr_t)stream_cfg);
return ret;
}
@ -569,7 +569,7 @@ static int start_stream_firmware(struct ipu6_isys_video *av,
tout = wait_for_completion_timeout(&stream->stream_open_completion,
IPU6_FW_CALL_TIMEOUT_JIFFIES);
ipu6_put_fw_msg_buf(av->isys, (u64)stream_cfg);
ipu6_put_fw_msg_buf(av->isys, (uintptr_t)stream_cfg);
if (!tout) {
dev_err(dev, "stream open time out\n");

6
drivers/media/pci/intel/ipu6/ipu6-isys.c
View file

@ -576,7 +576,7 @@ void update_watermark_setting(struct ipu6_isys *isys)
}
enable_iwake(isys, true);
calc_fill_time_us = max_sram_size / isys_pb_datarate_mbs;
calc_fill_time_us = div64_u64(max_sram_size, isys_pb_datarate_mbs);
if (isys->pdata->ipdata->enhanced_iwake) {
ltr = isys->pdata->ipdata->ltr;
@ -1026,11 +1026,11 @@ void ipu6_cleanup_fw_msg_bufs(struct ipu6_isys *isys)
spin_unlock_irqrestore(&isys->listlock, flags);
}
void ipu6_put_fw_msg_buf(struct ipu6_isys *isys, u64 data)
void ipu6_put_fw_msg_buf(struct ipu6_isys *isys, uintptr_t data)
{
struct isys_fw_msgs *msg;
unsigned long flags;
u64 *ptr = (u64 *)data;
void *ptr = (void *)data;
if (!ptr)
return;

2
drivers/media/pci/intel/ipu6/ipu6-isys.h
View file

@ -180,7 +180,7 @@ struct isys_fw_msgs {
};
struct isys_fw_msgs *ipu6_get_fw_msg_buf(struct ipu6_isys_stream *stream);
void ipu6_put_fw_msg_buf(struct ipu6_isys *isys, u64 data);
void ipu6_put_fw_msg_buf(struct ipu6_isys *isys, uintptr_t data);
void ipu6_cleanup_fw_msg_bufs(struct ipu6_isys *isys);
extern const struct v4l2_ioctl_ops ipu6_isys_ioctl_ops;

3
drivers/media/pci/intel/ipu6/ipu6.c
View file

@ -247,7 +247,8 @@ ipu6_pkg_dir_configure_spc(struct ipu6_device *isp,
dma_addr = sg_dma_address(isp->psys->fw_sgt.sgl);
pg_offset = server_fw_addr - dma_addr;
prog = (struct ipu6_cell_program *)((u64)isp->cpd_fw->data + pg_offset);
prog = (struct ipu6_cell_program *)((uintptr_t)isp->cpd_fw->data +
pg_offset);
spc_base = base + prog->regs_addr;
if (spc_base != (base + hw_variant->spc_offset))
dev_warn(&isp->pdev->dev,