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drm/amd/display: read invalid ddc pin status cause engine busy
[Why] There is no DDC_6 pin on new asic cause the mapping table is incorrect. When app try to access DDC_VGA port, driver read an invalid ddc pin status and report engine busy. [How] Add dummy DDC_6 pin to align gpio structure. Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Paul Hsieh <Paul.Hsieh@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 2 additions and 2 deletions
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@ -256,8 +256,8 @@ static const struct hw_factory_funcs funcs = {
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*/
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void dal_hw_factory_dcn32_init(struct hw_factory *factory)
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{
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factory->number_of_pins[GPIO_ID_DDC_DATA] = 6;
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factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 6;
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factory->number_of_pins[GPIO_ID_DDC_DATA] = 8;
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factory->number_of_pins[GPIO_ID_DDC_CLOCK] = 8;
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factory->number_of_pins[GPIO_ID_GENERIC] = 4;
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factory->number_of_pins[GPIO_ID_HPD] = 5;
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factory->number_of_pins[GPIO_ID_GPIO_PAD] = 28;
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