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memory: Add STM32 Octo Memory Manager driver
Octo Memory Manager driver (OMM) manages:
- the muxing between 2 OSPI busses and 2 output ports.
There are 4 possible muxing configurations:
- direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2
output is on port 2
- OSPI1 and OSPI2 are multiplexed over the same output port 1
- swapped mode (no multiplexing), OSPI1 output is on port 2,
OSPI2 output is on port 1
- OSPI1 and OSPI2 are multiplexed over the same output port 2
- the split of the memory area shared between the 2 OSPI instances.
- chip select selection override.
- the time between 2 transactions in multiplexed mode.
- check firewall access.
Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20250428-upstream_ospi_v6-v11-2-1548736fd9d2@foss.st.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Patrice Chotard
Krzysztof Kozlowski
parent
4a98ec836a
commit
8181d061dc
3 changed files with 494 additions and 0 deletions
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@ -225,6 +225,23 @@ config STM32_FMC2_EBI
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devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
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devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
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SOCs containing the FMC2 External Bus Interface.
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SOCs containing the FMC2 External Bus Interface.
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config STM32_OMM
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tristate "STM32 Octo Memory Manager"
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depends on SPI_STM32_OSPI || COMPILE_TEST
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help
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This driver manages the muxing between the 2 OSPI busses and
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the 2 output ports. There are 4 possible muxing configurations:
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- direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2
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output is on port 2
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- OSPI1 and OSPI2 are multiplexed over the same output port 1
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- swapped mode (no multiplexing), OSPI1 output is on port 2,
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OSPI2 output is on port 1
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- OSPI1 and OSPI2 are multiplexed over the same output port 2
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It also manages :
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- the split of the memory area shared between the 2 OSPI instances.
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- chip select selection override.
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- the time between 2 transactions in multiplexed mode.
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source "drivers/memory/samsung/Kconfig"
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source "drivers/memory/samsung/Kconfig"
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source "drivers/memory/tegra/Kconfig"
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source "drivers/memory/tegra/Kconfig"
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@ -24,6 +24,7 @@ obj-$(CONFIG_DA8XX_DDRCTL) += da8xx-ddrctl.o
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obj-$(CONFIG_PL353_SMC) += pl353-smc.o
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obj-$(CONFIG_PL353_SMC) += pl353-smc.o
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obj-$(CONFIG_RENESAS_RPCIF) += renesas-rpc-if.o
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obj-$(CONFIG_RENESAS_RPCIF) += renesas-rpc-if.o
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obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o
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obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o
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obj-$(CONFIG_STM32_OMM) += stm32_omm.o
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obj-$(CONFIG_SAMSUNG_MC) += samsung/
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obj-$(CONFIG_SAMSUNG_MC) += samsung/
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obj-$(CONFIG_TEGRA_MC) += tegra/
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obj-$(CONFIG_TEGRA_MC) += tegra/
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476
drivers/memory/stm32_omm.c
Normal file
476
drivers/memory/stm32_omm.c
Normal file
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@ -0,0 +1,476 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
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* Author(s): Patrice Chotard <patrice.chotard@foss.st.com> for STMicroelectronics.
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*/
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#include <linux/bitfield.h>
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#include <linux/bus/stm32_firewall_device.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#define OMM_CR 0
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#define CR_MUXEN BIT(0)
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#define CR_MUXENMODE_MASK GENMASK(1, 0)
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#define CR_CSSEL_OVR_EN BIT(4)
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#define CR_CSSEL_OVR_MASK GENMASK(6, 5)
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#define CR_REQ2ACK_MASK GENMASK(23, 16)
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#define OMM_CHILD_NB 2
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#define OMM_CLK_NB 3
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struct stm32_omm {
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struct resource *mm_res;
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struct clk_bulk_data clk_bulk[OMM_CLK_NB];
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struct reset_control *child_reset[OMM_CHILD_NB];
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void __iomem *io_base;
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u32 cr;
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u8 nb_child;
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bool restore_omm;
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};
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static int stm32_omm_set_amcr(struct device *dev, bool set)
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{
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struct stm32_omm *omm = dev_get_drvdata(dev);
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resource_size_t mm_ospi2_size = 0;
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static const char * const mm_name[] = { "ospi1", "ospi2" };
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struct regmap *syscfg_regmap;
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struct device_node *node;
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struct resource res, res1;
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u32 amcr_base, amcr_mask;
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int ret, idx;
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unsigned int i, amcr, read_amcr;
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for (i = 0; i < omm->nb_child; i++) {
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idx = of_property_match_string(dev->of_node,
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"memory-region-names",
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mm_name[i]);
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if (idx < 0)
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continue;
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/* res1 only used on second loop iteration */
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res1.start = res.start;
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res1.end = res.end;
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node = of_parse_phandle(dev->of_node, "memory-region", idx);
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if (!node)
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continue;
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ret = of_address_to_resource(node, 0, &res);
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if (ret) {
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of_node_put(node);
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dev_err(dev, "unable to resolve memory region\n");
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return ret;
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}
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/* check that memory region fits inside OMM memory map area */
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if (!resource_contains(omm->mm_res, &res)) {
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dev_err(dev, "%s doesn't fit inside OMM memory map area\n",
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mm_name[i]);
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dev_err(dev, "%pR doesn't fit inside %pR\n", &res, omm->mm_res);
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of_node_put(node);
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return -EFAULT;
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}
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if (i == 1) {
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mm_ospi2_size = resource_size(&res);
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/* check that OMM memory region 1 doesn't overlap memory region 2 */
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if (resource_overlaps(&res, &res1)) {
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dev_err(dev, "OMM memory-region %s overlaps memory region %s\n",
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mm_name[0], mm_name[1]);
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dev_err(dev, "%pR overlaps %pR\n", &res1, &res);
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of_node_put(node);
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return -EFAULT;
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}
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}
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of_node_put(node);
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}
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syscfg_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "st,syscfg-amcr");
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if (IS_ERR(syscfg_regmap))
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return dev_err_probe(dev, PTR_ERR(syscfg_regmap),
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"Failed to get st,syscfg-amcr property\n");
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ret = of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 1,
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&amcr_base);
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if (ret)
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return ret;
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ret = of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 2,
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&amcr_mask);
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if (ret)
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return ret;
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amcr = mm_ospi2_size / SZ_64M;
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if (set)
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regmap_update_bits(syscfg_regmap, amcr_base, amcr_mask, amcr);
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/* read AMCR and check coherency with memory-map areas defined in DT */
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regmap_read(syscfg_regmap, amcr_base, &read_amcr);
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read_amcr = read_amcr >> (ffs(amcr_mask) - 1);
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if (amcr != read_amcr) {
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dev_err(dev, "AMCR value not coherent with DT memory-map areas\n");
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ret = -EINVAL;
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}
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return ret;
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}
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static int stm32_omm_toggle_child_clock(struct device *dev, bool enable)
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{
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struct stm32_omm *omm = dev_get_drvdata(dev);
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int i, ret;
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for (i = 0; i < omm->nb_child; i++) {
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if (enable) {
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ret = clk_prepare_enable(omm->clk_bulk[i + 1].clk);
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if (ret) {
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dev_err(dev, "Can not enable clock\n");
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goto clk_error;
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}
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} else {
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clk_disable_unprepare(omm->clk_bulk[i + 1].clk);
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}
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}
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return 0;
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clk_error:
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while (i--)
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clk_disable_unprepare(omm->clk_bulk[i + 1].clk);
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return ret;
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}
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static int stm32_omm_disable_child(struct device *dev)
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{
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struct stm32_omm *omm = dev_get_drvdata(dev);
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struct reset_control *reset;
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int ret;
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u8 i;
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ret = stm32_omm_toggle_child_clock(dev, true);
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if (!ret)
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return ret;
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for (i = 0; i < omm->nb_child; i++) {
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/* reset OSPI to ensure CR_EN bit is set to 0 */
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reset = omm->child_reset[i];
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ret = reset_control_acquire(reset);
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if (ret) {
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stm32_omm_toggle_child_clock(dev, false);
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dev_err(dev, "Can not acquire resset %d\n", ret);
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return ret;
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}
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reset_control_assert(reset);
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udelay(2);
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reset_control_deassert(reset);
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reset_control_release(reset);
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}
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return stm32_omm_toggle_child_clock(dev, false);
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}
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static int stm32_omm_configure(struct device *dev)
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{
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static const char * const clocks_name[] = {"omm", "ospi1", "ospi2"};
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struct stm32_omm *omm = dev_get_drvdata(dev);
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unsigned long clk_rate_max = 0;
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u32 mux = 0;
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u32 cssel_ovr = 0;
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u32 req2ack = 0;
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struct reset_control *rstc;
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unsigned long clk_rate;
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int ret;
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u8 i;
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for (i = 0; i < OMM_CLK_NB; i++)
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omm->clk_bulk[i].id = clocks_name[i];
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/* retrieve OMM, OSPI1 and OSPI2 clocks */
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ret = devm_clk_bulk_get(dev, OMM_CLK_NB, omm->clk_bulk);
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if (ret)
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return dev_err_probe(dev, ret, "Failed to get OMM/OSPI's clocks\n");
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/* Ensure both OSPI instance are disabled before configuring OMM */
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ret = stm32_omm_disable_child(dev);
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if (ret)
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return ret;
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ret = pm_runtime_resume_and_get(dev);
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if (ret < 0)
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return ret;
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/* parse children's clock */
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for (i = 1; i <= omm->nb_child; i++) {
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clk_rate = clk_get_rate(omm->clk_bulk[i].clk);
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if (!clk_rate) {
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dev_err(dev, "Invalid clock rate\n");
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goto error;
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}
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if (clk_rate > clk_rate_max)
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clk_rate_max = clk_rate;
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}
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rstc = devm_reset_control_get_exclusive(dev, "omm");
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if (IS_ERR(rstc))
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return dev_err_probe(dev, PTR_ERR(rstc), "reset get failed\n");
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reset_control_assert(rstc);
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udelay(2);
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reset_control_deassert(rstc);
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omm->cr = readl_relaxed(omm->io_base + OMM_CR);
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/* optional */
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ret = of_property_read_u32(dev->of_node, "st,omm-mux", &mux);
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if (!ret) {
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if (mux & CR_MUXEN) {
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ret = of_property_read_u32(dev->of_node, "st,omm-req2ack-ns",
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&req2ack);
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if (!ret && !req2ack) {
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req2ack = DIV_ROUND_UP(req2ack, NSEC_PER_SEC / clk_rate_max) - 1;
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if (req2ack > 256)
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req2ack = 256;
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}
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req2ack = FIELD_PREP(CR_REQ2ACK_MASK, req2ack);
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omm->cr &= ~CR_REQ2ACK_MASK;
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omm->cr |= FIELD_PREP(CR_REQ2ACK_MASK, req2ack);
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/*
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* If the mux is enabled, the 2 OSPI clocks have to be
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* always enabled
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*/
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ret = stm32_omm_toggle_child_clock(dev, true);
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if (ret)
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goto error;
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}
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omm->cr &= ~CR_MUXENMODE_MASK;
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omm->cr |= FIELD_PREP(CR_MUXENMODE_MASK, mux);
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}
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/* optional */
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ret = of_property_read_u32(dev->of_node, "st,omm-cssel-ovr", &cssel_ovr);
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if (!ret) {
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omm->cr &= ~CR_CSSEL_OVR_MASK;
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omm->cr |= FIELD_PREP(CR_CSSEL_OVR_MASK, cssel_ovr);
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omm->cr |= CR_CSSEL_OVR_EN;
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}
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omm->restore_omm = true;
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writel_relaxed(omm->cr, omm->io_base + OMM_CR);
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ret = stm32_omm_set_amcr(dev, true);
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error:
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pm_runtime_put_sync_suspend(dev);
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return ret;
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}
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static int stm32_omm_check_access(struct device_node *np)
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{
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struct stm32_firewall firewall;
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int ret;
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ret = stm32_firewall_get_firewall(np, &firewall, 1);
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if (ret)
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return ret;
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return stm32_firewall_grant_access(&firewall);
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}
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static int stm32_omm_probe(struct platform_device *pdev)
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{
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static const char * const resets_name[] = {"ospi1", "ospi2"};
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struct device *dev = &pdev->dev;
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u8 child_access_granted = 0;
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struct stm32_omm *omm;
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||||||
|
int i, ret;
|
||||||
|
|
||||||
|
omm = devm_kzalloc(dev, sizeof(*omm), GFP_KERNEL);
|
||||||
|
if (!omm)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
omm->io_base = devm_platform_ioremap_resource_byname(pdev, "regs");
|
||||||
|
if (IS_ERR(omm->io_base))
|
||||||
|
return PTR_ERR(omm->io_base);
|
||||||
|
|
||||||
|
omm->mm_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory_map");
|
||||||
|
if (IS_ERR(omm->mm_res))
|
||||||
|
return PTR_ERR(omm->mm_res);
|
||||||
|
|
||||||
|
/* check child's access */
|
||||||
|
for_each_child_of_node_scoped(dev->of_node, child) {
|
||||||
|
if (omm->nb_child >= OMM_CHILD_NB) {
|
||||||
|
dev_err(dev, "Bad DT, found too much children\n");
|
||||||
|
return -E2BIG;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = stm32_omm_check_access(child);
|
||||||
|
if (ret < 0 && ret != -EACCES)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
if (!ret)
|
||||||
|
child_access_granted++;
|
||||||
|
|
||||||
|
omm->nb_child++;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (omm->nb_child != OMM_CHILD_NB)
|
||||||
|
return -EINVAL;
|
||||||
|
|
||||||
|
platform_set_drvdata(pdev, omm);
|
||||||
|
|
||||||
|
devm_pm_runtime_enable(dev);
|
||||||
|
|
||||||
|
/* check if OMM's resource access is granted */
|
||||||
|
ret = stm32_omm_check_access(dev->of_node);
|
||||||
|
if (ret < 0 && ret != -EACCES)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
for (i = 0; i < omm->nb_child; i++) {
|
||||||
|
omm->child_reset[i] = devm_reset_control_get_exclusive_released(dev,
|
||||||
|
resets_name[i]);
|
||||||
|
|
||||||
|
if (IS_ERR(omm->child_reset[i]))
|
||||||
|
return dev_err_probe(dev, PTR_ERR(omm->child_reset[i]),
|
||||||
|
"Can't get %s reset\n", resets_name[i]);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!ret && child_access_granted == OMM_CHILD_NB) {
|
||||||
|
ret = stm32_omm_configure(dev);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
} else {
|
||||||
|
dev_dbg(dev, "Octo Memory Manager resource's access not granted\n");
|
||||||
|
/*
|
||||||
|
* AMCR can't be set, so check if current value is coherent
|
||||||
|
* with memory-map areas defined in DT
|
||||||
|
*/
|
||||||
|
ret = stm32_omm_set_amcr(dev, false);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
ret = devm_of_platform_populate(dev);
|
||||||
|
if (ret) {
|
||||||
|
if (omm->cr & CR_MUXEN)
|
||||||
|
stm32_omm_toggle_child_clock(&pdev->dev, false);
|
||||||
|
|
||||||
|
return dev_err_probe(dev, ret, "Failed to create Octo Memory Manager child\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void stm32_omm_remove(struct platform_device *pdev)
|
||||||
|
{
|
||||||
|
struct stm32_omm *omm = platform_get_drvdata(pdev);
|
||||||
|
|
||||||
|
if (omm->cr & CR_MUXEN)
|
||||||
|
stm32_omm_toggle_child_clock(&pdev->dev, false);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct of_device_id stm32_omm_of_match[] = {
|
||||||
|
{ .compatible = "st,stm32mp25-omm", },
|
||||||
|
{}
|
||||||
|
};
|
||||||
|
MODULE_DEVICE_TABLE(of, stm32_omm_of_match);
|
||||||
|
|
||||||
|
static int __maybe_unused stm32_omm_runtime_suspend(struct device *dev)
|
||||||
|
{
|
||||||
|
struct stm32_omm *omm = dev_get_drvdata(dev);
|
||||||
|
|
||||||
|
clk_disable_unprepare(omm->clk_bulk[0].clk);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int __maybe_unused stm32_omm_runtime_resume(struct device *dev)
|
||||||
|
{
|
||||||
|
struct stm32_omm *omm = dev_get_drvdata(dev);
|
||||||
|
|
||||||
|
return clk_prepare_enable(omm->clk_bulk[0].clk);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int __maybe_unused stm32_omm_suspend(struct device *dev)
|
||||||
|
{
|
||||||
|
struct stm32_omm *omm = dev_get_drvdata(dev);
|
||||||
|
|
||||||
|
if (omm->restore_omm && omm->cr & CR_MUXEN)
|
||||||
|
stm32_omm_toggle_child_clock(dev, false);
|
||||||
|
|
||||||
|
return pinctrl_pm_select_sleep_state(dev);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int __maybe_unused stm32_omm_resume(struct device *dev)
|
||||||
|
{
|
||||||
|
struct stm32_omm *omm = dev_get_drvdata(dev);
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
pinctrl_pm_select_default_state(dev);
|
||||||
|
|
||||||
|
if (!omm->restore_omm)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
/* Ensure both OSPI instance are disabled before configuring OMM */
|
||||||
|
ret = stm32_omm_disable_child(dev);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
ret = pm_runtime_resume_and_get(dev);
|
||||||
|
if (ret < 0)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
writel_relaxed(omm->cr, omm->io_base + OMM_CR);
|
||||||
|
ret = stm32_omm_set_amcr(dev, true);
|
||||||
|
pm_runtime_put_sync_suspend(dev);
|
||||||
|
if (ret)
|
||||||
|
return ret;
|
||||||
|
|
||||||
|
if (omm->cr & CR_MUXEN)
|
||||||
|
ret = stm32_omm_toggle_child_clock(dev, true);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct dev_pm_ops stm32_omm_pm_ops = {
|
||||||
|
SET_RUNTIME_PM_OPS(stm32_omm_runtime_suspend,
|
||||||
|
stm32_omm_runtime_resume, NULL)
|
||||||
|
SET_SYSTEM_SLEEP_PM_OPS(stm32_omm_suspend, stm32_omm_resume)
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct platform_driver stm32_omm_driver = {
|
||||||
|
.probe = stm32_omm_probe,
|
||||||
|
.remove = stm32_omm_remove,
|
||||||
|
.driver = {
|
||||||
|
.name = "stm32-omm",
|
||||||
|
.of_match_table = stm32_omm_of_match,
|
||||||
|
.pm = &stm32_omm_pm_ops,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
module_platform_driver(stm32_omm_driver);
|
||||||
|
|
||||||
|
MODULE_DESCRIPTION("STMicroelectronics Octo Memory Manager driver");
|
||||||
|
MODULE_LICENSE("GPL");
|
||||||
Loading…
Add table
Reference in a new issue