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riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC

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Add known reset configuration for existed device.

Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250617070144.1149926-5-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
This commit is contained in:
Inochi Amaoto 2025-06-17 15:01:42 +08:00
parent f5742f67a4
commit 817c89a6b5
1 changed files with 18 additions and 0 deletions
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18
arch/riscv/boot/dts/sophgo/cv180x.dtsi
View file

@ -36,6 +36,7 @@
reg = <0x3020000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&rst RST_GPIO0>;
porta: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@ -54,6 +55,7 @@
reg = <0x3021000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&rst RST_GPIO1>;
portb: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@ -72,6 +74,7 @@
reg = <0x3022000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&rst RST_GPIO2>;
portc: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@ -90,6 +93,7 @@
reg = <0x3023000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&rst RST_GPIO3>;
portd: gpio-controller@0 {
compatible = "snps,dw-apb-gpio-port";
@ -133,6 +137,7 @@
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_I2C0>;
status = "disabled";
};
@ -144,6 +149,7 @@
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_I2C1>;
status = "disabled";
};
@ -155,6 +161,7 @@
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_I2C2>;
status = "disabled";
};
@ -166,6 +173,7 @@
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_I2C3>;
status = "disabled";
};
@ -177,6 +185,7 @@
clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
clock-names = "ref", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_I2C4>;
status = "disabled";
};
@ -188,6 +197,7 @@
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART0>;
status = "disabled";
};
@ -199,6 +209,7 @@
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART1>;
status = "disabled";
};
@ -210,6 +221,7 @@
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART2>;
status = "disabled";
};
@ -221,6 +233,7 @@
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART3>;
status = "disabled";
};
@ -232,6 +245,7 @@
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_SPI0>;
status = "disabled";
};
@ -243,6 +257,7 @@
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_SPI1>;
status = "disabled";
};
@ -254,6 +269,7 @@
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_SPI2>;
status = "disabled";
};
@ -265,6 +281,7 @@
clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
clock-names = "ssi_clk", "pclk";
interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>;
resets = <&rst RST_SPI3>;
status = "disabled";
};
@ -276,6 +293,7 @@
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
resets = <&rst RST_UART4>;
status = "disabled";
};