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ASoC: rt722-sdca: Add RT722 SDCA driver

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This is the initial codec driver for rt722-sdca.

Signed-off-by: Jack Yu <jack.yu@realtek.com
Link: https://lore.kernel.org/r/20230421030116.26245-1-jack.yu@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org
This commit is contained in:
Jack Yu 2023-04-21 11:01:16 +08:00 • committed by Mark Brown
parent 5782f01994
commit 7f5d6036ca
No known key found for this signature in database
GPG key ID: 24D68B725D5487D0
6 changed files with 2436 additions and 0 deletions
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7
sound/soc/codecs/Kconfig
View file

@ -207,6 +207,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_RT712_SDCA_DMIC_SDW
imply SND_SOC_RT715_SDW
imply SND_SOC_RT715_SDCA_SDW
imply SND_SOC_RT722_SDCA_SDW
imply SND_SOC_RT1308_SDW
imply SND_SOC_RT1316_SDW
imply SND_SOC_RT1318_SDW
@ -1539,6 +1540,12 @@ config SND_SOC_RT712_SDCA_DMIC_SDW
select REGMAP_SOUNDWIRE
select REGMAP_SOUNDWIRE_MBQ
config SND_SOC_RT722_SDCA_SDW
tristate "Realtek RT722 SDCA Codec - SDW"
depends on SOUNDWIRE
select REGMAP_SOUNDWIRE
select REGMAP_SOUNDWIRE_MBQ
config SND_SOC_RT715
tristate

2
sound/soc/codecs/Makefile
View file

@ -237,6 +237,7 @@ snd-soc-rt712-sdca-objs := rt712-sdca.o rt712-sdca-sdw.o
snd-soc-rt712-sdca-dmic-objs := rt712-sdca-dmic.o
snd-soc-rt715-objs := rt715.o rt715-sdw.o
snd-soc-rt715-sdca-objs := rt715-sdca.o rt715-sdca-sdw.o
snd-soc-rt722-sdca-objs := rt722-sdca.o rt722-sdca-sdw.o
snd-soc-rt9120-objs := rt9120.o
snd-soc-sdw-mockup-objs := sdw-mockup.o
snd-soc-sgtl5000-objs := sgtl5000.o
@ -607,6 +608,7 @@ obj-$(CONFIG_SND_SOC_RT712_SDCA_SDW) += snd-soc-rt712-sdca.o
obj-$(CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW) += snd-soc-rt712-sdca-dmic.o
obj-$(CONFIG_SND_SOC_RT715) += snd-soc-rt715.o
obj-$(CONFIG_SND_SOC_RT715_SDCA_SDW) += snd-soc-rt715-sdca.o
obj-$(CONFIG_SND_SOC_RT722_SDCA_SDW) += snd-soc-rt722-sdca.o
obj-$(CONFIG_SND_SOC_RT9120) += snd-soc-rt9120.o
obj-$(CONFIG_SND_SOC_SDW_MOCKUP) += snd-soc-sdw-mockup.o
obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o

510
sound/soc/codecs/rt722-sdca-sdw.c Normal file
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@ -0,0 +1,510 @@
// SPDX-License-Identifier: GPL-2.0-only
//
// rt722-sdca-sdw.c -- rt722 SDCA ALSA SoC audio driver
//
// Copyright(c) 2023 Realtek Semiconductor Corp.
//
//
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/pm_runtime.h>
#include <linux/soundwire/sdw_registers.h>
#include "rt722-sdca.h"
#include "rt722-sdca-sdw.h"
static bool rt722_sdca_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2f01 ... 0x2f0a:
case 0x2f35 ... 0x2f36:
case 0x2f50:
case 0x2f54:
case 0x2f58 ... 0x2f5d:
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_SELECTED_MODE,
0):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_DETECTED_MODE,
0):
case SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, RT722_SDCA_CTL_HIDTX_CURRENT_OWNER,
0) ... SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
RT722_SDCA_CTL_HIDTX_MESSAGE_LENGTH, 0):
case RT722_BUF_ADDR_HID1 ... RT722_BUF_ADDR_HID2:
return true;
default:
return false;
}
}
static bool rt722_sdca_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2f01:
case 0x2f54:
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_GE49, RT722_SDCA_CTL_DETECTED_MODE,
0):
case SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01, RT722_SDCA_CTL_HIDTX_CURRENT_OWNER,
0) ... SDW_SDCA_CTL(FUNC_NUM_HID, RT722_SDCA_ENT_HID01,
RT722_SDCA_CTL_HIDTX_MESSAGE_LENGTH, 0):
case RT722_BUF_ADDR_HID1 ... RT722_BUF_ADDR_HID2:
return true;
default:
return false;
}
}
static bool rt722_sdca_mbq_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2000000 ... 0x2000024:
case 0x2000029 ... 0x200004a:
case 0x2000051 ... 0x2000052:
case 0x200005a ... 0x200005b:
case 0x2000061 ... 0x2000069:
case 0x200006b:
case 0x2000070:
case 0x200007f:
case 0x2000082 ... 0x200008e:
case 0x2000090 ... 0x2000094:
case 0x5300000 ... 0x5300002:
case 0x5400002:
case 0x5600000 ... 0x5600007:
case 0x5700000 ... 0x5700004:
case 0x5800000 ... 0x5800004:
case 0x5b00003:
case 0x5c00011:
case 0x5d00006:
case 0x5f00000 ... 0x5f0000d:
case 0x5f00030:
case 0x6100000 ... 0x6100051:
case 0x6100055 ... 0x6100057:
case 0x6100062:
case 0x6100064 ... 0x6100065:
case 0x6100067:
case 0x6100070 ... 0x610007c:
case 0x6100080:
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
CH_01):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
CH_02):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
CH_03):
case SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
CH_04):
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_L):
case SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_R):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME,
CH_L):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME,
CH_R):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME,
CH_L):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME,
CH_R):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
RT722_SDCA_CTL_FU_CH_GAIN, CH_L):
case SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44,
RT722_SDCA_CTL_FU_CH_GAIN, CH_R):
return true;
default:
return false;
}
}
static bool rt722_sdca_mbq_volatile_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case 0x2000000:
case 0x200000d:
case 0x2000019:
case 0x2000020:
case 0x2000030:
case 0x2000046:
case 0x2000067:
case 0x2000084:
case 0x2000086:
return true;
default:
return false;
}
}
static const struct regmap_config rt722_sdca_regmap = {
.reg_bits = 32,
.val_bits = 8,
.readable_reg = rt722_sdca_readable_register,
.volatile_reg = rt722_sdca_volatile_register,
.max_register = 0x44ffffff,
.reg_defaults = rt722_sdca_reg_defaults,
.num_reg_defaults = ARRAY_SIZE(rt722_sdca_reg_defaults),
.cache_type = REGCACHE_RBTREE,
.use_single_read = true,
.use_single_write = true,
};
static const struct regmap_config rt722_sdca_mbq_regmap = {
.name = "sdw-mbq",
.reg_bits = 32,
.val_bits = 16,
.readable_reg = rt722_sdca_mbq_readable_register,
.volatile_reg = rt722_sdca_mbq_volatile_register,
.max_register = 0x41000312,
.reg_defaults = rt722_sdca_mbq_defaults,
.num_reg_defaults = ARRAY_SIZE(rt722_sdca_mbq_defaults),
.cache_type = REGCACHE_RBTREE,
.use_single_read = true,
.use_single_write = true,
};
static int rt722_sdca_update_status(struct sdw_slave *slave,
enum sdw_slave_status status)
{
struct rt722_sdca_priv *rt722 = dev_get_drvdata(&slave->dev);
/* Update the status */
rt722->status = status;
if (status == SDW_SLAVE_UNATTACHED)
rt722->hw_init = false;
if (status == SDW_SLAVE_ATTACHED) {
if (rt722->hs_jack) {
/*
* Due to the SCP_SDCA_INTMASK will be cleared by any reset, and then
* if the device attached again, we will need to set the setting back.
* It could avoid losing the jack detection interrupt.
* This also could sync with the cache value as the rt722_sdca_jack_init set.
*/
sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK1,
SDW_SCP_SDCA_INTMASK_SDCA_0 | SDW_SCP_SDCA_INTMASK_SDCA_6);
sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INTMASK2,
SDW_SCP_SDCA_INTMASK_SDCA_8);
}
}
/*
* Perform initialization only if slave status is present and
* hw_init flag is false
*/
if (rt722->hw_init || rt722->status != SDW_SLAVE_ATTACHED)
return 0;
/* perform I/O transfers required for Slave initialization */
return rt722_sdca_io_init(&slave->dev, slave);
}
static int rt722_sdca_read_prop(struct sdw_slave *slave)
{
struct sdw_slave_prop *prop = &slave->prop;
int nval;
int i, j;
u32 bit;
unsigned long addr;
struct sdw_dpn_prop *dpn;
prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY;
prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
prop->paging_support = true;
/*
* port = 1 for headphone playback
* port = 2 for headset-mic capture
* port = 3 for speaker playback
* port = 6 for digital-mic capture
*/
prop->source_ports = BIT(6) | BIT(2); /* BITMAP: 01000100 */
prop->sink_ports = BIT(3) | BIT(1); /* BITMAP: 00001010 */
nval = hweight32(prop->source_ports);
prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->src_dpn_prop), GFP_KERNEL);
if (!prop->src_dpn_prop)
return -ENOMEM;
i = 0;
dpn = prop->src_dpn_prop;
addr = prop->source_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[i].num = bit;
dpn[i].type = SDW_DPN_FULL;
dpn[i].simple_ch_prep_sm = true;
dpn[i].ch_prep_timeout = 10;
i++;
}
/* do this again for sink now */
nval = hweight32(prop->sink_ports);
prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
sizeof(*prop->sink_dpn_prop), GFP_KERNEL);
if (!prop->sink_dpn_prop)
return -ENOMEM;
j = 0;
dpn = prop->sink_dpn_prop;
addr = prop->sink_ports;
for_each_set_bit(bit, &addr, 32) {
dpn[j].num = bit;
dpn[j].type = SDW_DPN_FULL;
dpn[j].simple_ch_prep_sm = true;
dpn[j].ch_prep_timeout = 10;
j++;
}
/* set the timeout values */
prop->clk_stop_timeout = 200;
/* wake-up event */
prop->wake_capable = 1;
return 0;
}
static int rt722_sdca_interrupt_callback(struct sdw_slave *slave,
struct sdw_slave_intr_status *status)
{
struct rt722_sdca_priv *rt722 = dev_get_drvdata(&slave->dev);
int ret, stat;
int count = 0, retry = 3;
unsigned int sdca_cascade, scp_sdca_stat1, scp_sdca_stat2 = 0;
if (cancel_delayed_work_sync(&rt722->jack_detect_work)) {
dev_warn(&slave->dev, "%s the pending delayed_work was cancelled", __func__);
/* avoid the HID owner doesn't change to device */
if (rt722->scp_sdca_stat2)
scp_sdca_stat2 = rt722->scp_sdca_stat2;
}
/*
* The critical section below intentionally protects a rather large piece of code.
* We don't want to allow the system suspend to disable an interrupt while we are
* processing it, which could be problematic given the quirky SoundWire interrupt
* scheme. We do want however to prevent new workqueues from being scheduled if
* the disable_irq flag was set during system suspend.
*/
mutex_lock(&rt722->disable_irq_lock);
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT1);
if (ret < 0)
goto io_error;
rt722->scp_sdca_stat1 = ret;
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT2);
if (ret < 0)
goto io_error;
rt722->scp_sdca_stat2 = ret;
if (scp_sdca_stat2)
rt722->scp_sdca_stat2 |= scp_sdca_stat2;
do {
/* clear flag */
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT1);
if (ret < 0)
goto io_error;
if (ret & SDW_SCP_SDCA_INTMASK_SDCA_0) {
ret = sdw_update_no_pm(rt722->slave, SDW_SCP_SDCA_INT1,
SDW_SCP_SDCA_INT_SDCA_0, SDW_SCP_SDCA_INT_SDCA_0);
if (ret < 0)
goto io_error;
} else if (ret & SDW_SCP_SDCA_INTMASK_SDCA_6) {
ret = sdw_update_no_pm(rt722->slave, SDW_SCP_SDCA_INT1,
SDW_SCP_SDCA_INT_SDCA_6, SDW_SCP_SDCA_INT_SDCA_6);
if (ret < 0)
goto io_error;
}
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT2);
if (ret < 0)
goto io_error;
if (ret & SDW_SCP_SDCA_INTMASK_SDCA_8) {
ret = sdw_write_no_pm(rt722->slave, SDW_SCP_SDCA_INT2,
SDW_SCP_SDCA_INTMASK_SDCA_8);
if (ret < 0)
goto io_error;
}
/* check if flag clear or not */
ret = sdw_read_no_pm(rt722->slave, SDW_DP0_INT);
if (ret < 0)
goto io_error;
sdca_cascade = ret & SDW_DP0_SDCA_CASCADE;
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT1);
if (ret < 0)
goto io_error;
scp_sdca_stat1 = ret & SDW_SCP_SDCA_INTMASK_SDCA_0;
ret = sdw_read_no_pm(rt722->slave, SDW_SCP_SDCA_INT2);
if (ret < 0)
goto io_error;
scp_sdca_stat2 = ret & SDW_SCP_SDCA_INTMASK_SDCA_8;
stat = scp_sdca_stat1 || scp_sdca_stat2 || sdca_cascade;
count++;
} while (stat != 0 && count < retry);
if (stat)
dev_warn(&slave->dev,
"%s scp_sdca_stat1=0x%x, scp_sdca_stat2=0x%x\n", __func__,
rt722->scp_sdca_stat1, rt722->scp_sdca_stat2);
if (status->sdca_cascade && !rt722->disable_irq)
mod_delayed_work(system_power_efficient_wq,
&rt722->jack_detect_work, msecs_to_jiffies(30));
mutex_unlock(&rt722->disable_irq_lock);
return 0;
io_error:
mutex_unlock(&rt722->disable_irq_lock);
pr_err_ratelimited("IO error in %s, ret %d\n", __func__, ret);
return ret;
}
static struct sdw_slave_ops rt722_sdca_slave_ops = {
.read_prop = rt722_sdca_read_prop,
.interrupt_callback = rt722_sdca_interrupt_callback,
.update_status = rt722_sdca_update_status,
};
static int rt722_sdca_sdw_probe(struct sdw_slave *slave,
const struct sdw_device_id *id)
{
struct regmap *regmap, *mbq_regmap;
/* Regmap Initialization */
mbq_regmap = devm_regmap_init_sdw_mbq(slave, &rt722_sdca_mbq_regmap);
if (IS_ERR(mbq_regmap))
return PTR_ERR(mbq_regmap);
regmap = devm_regmap_init_sdw(slave, &rt722_sdca_regmap);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
return rt722_sdca_init(&slave->dev, regmap, mbq_regmap, slave);
}
static int rt722_sdca_sdw_remove(struct sdw_slave *slave)
{
struct rt722_sdca_priv *rt722 = dev_get_drvdata(&slave->dev);
if (rt722->hw_init) {
cancel_delayed_work_sync(&rt722->jack_detect_work);
cancel_delayed_work_sync(&rt722->jack_btn_check_work);
}
if (rt722->first_hw_init)
pm_runtime_disable(&slave->dev);
mutex_destroy(&rt722->calibrate_mutex);
mutex_destroy(&rt722->disable_irq_lock);
return 0;
}
static const struct sdw_device_id rt722_sdca_id[] = {
SDW_SLAVE_ENTRY_EXT(0x025d, 0x722, 0x3, 0x1, 0),
{},
};
MODULE_DEVICE_TABLE(sdw, rt722_sdca_id);
static int __maybe_unused rt722_sdca_dev_suspend(struct device *dev)
{
struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev);
if (!rt722->hw_init)
return 0;
cancel_delayed_work_sync(&rt722->jack_detect_work);
cancel_delayed_work_sync(&rt722->jack_btn_check_work);
regcache_cache_only(rt722->regmap, true);
regcache_cache_only(rt722->mbq_regmap, true);
return 0;
}
static int __maybe_unused rt722_sdca_dev_system_suspend(struct device *dev)
{
struct rt722_sdca_priv *rt722_sdca = dev_get_drvdata(dev);
struct sdw_slave *slave = dev_to_sdw_dev(dev);
int ret1, ret2;
if (!rt722_sdca->hw_init)
return 0;
/*
* prevent new interrupts from being handled after the
* deferred work completes and before the parent disables
* interrupts on the link
*/
mutex_lock(&rt722_sdca->disable_irq_lock);
rt722_sdca->disable_irq = true;
ret1 = sdw_update_no_pm(slave, SDW_SCP_SDCA_INTMASK1,
SDW_SCP_SDCA_INTMASK_SDCA_0 | SDW_SCP_SDCA_INTMASK_SDCA_6, 0);
ret2 = sdw_update_no_pm(slave, SDW_SCP_SDCA_INTMASK2,
SDW_SCP_SDCA_INTMASK_SDCA_8, 0);
mutex_unlock(&rt722_sdca->disable_irq_lock);
if (ret1 < 0 || ret2 < 0) {
/* log but don't prevent suspend from happening */
dev_dbg(&slave->dev, "%s: could not disable SDCA interrupts\n:", __func__);
}
return rt722_sdca_dev_suspend(dev);
}
#define RT722_PROBE_TIMEOUT 5000
static int __maybe_unused rt722_sdca_dev_resume(struct device *dev)
{
struct sdw_slave *slave = dev_to_sdw_dev(dev);
struct rt722_sdca_priv *rt722 = dev_get_drvdata(dev);
unsigned long time;
if (!rt722->first_hw_init)
return 0;
if (!slave->unattach_request)
goto regmap_sync;
time = wait_for_completion_timeout(&slave->initialization_complete,
msecs_to_jiffies(RT722_PROBE_TIMEOUT));
if (!time) {
dev_err(&slave->dev, "Initialization not complete, timed out\n");
sdw_show_ping_status(slave->bus, true);
return -ETIMEDOUT;
}
regmap_sync:
slave->unattach_request = 0;
regcache_cache_only(rt722->regmap, false);
regcache_sync(rt722->regmap);
regcache_cache_only(rt722->mbq_regmap, false);
regcache_sync(rt722->mbq_regmap);
return 0;
}
static const struct dev_pm_ops rt722_sdca_pm = {
SET_SYSTEM_SLEEP_PM_OPS(rt722_sdca_dev_system_suspend, rt722_sdca_dev_resume)
SET_RUNTIME_PM_OPS(rt722_sdca_dev_suspend, rt722_sdca_dev_resume, NULL)
};
static struct sdw_driver rt722_sdca_sdw_driver = {
.driver = {
.name = "rt722-sdca",
.owner = THIS_MODULE,
.pm = &rt722_sdca_pm,
},
.probe = rt722_sdca_sdw_probe,
.remove = rt722_sdca_sdw_remove,
.ops = &rt722_sdca_slave_ops,
.id_table = rt722_sdca_id,
};
module_sdw_driver(rt722_sdca_sdw_driver);
MODULE_DESCRIPTION("ASoC RT722 SDCA SDW driver");
MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
MODULE_LICENSE("GPL");

124
sound/soc/codecs/rt722-sdca-sdw.h Normal file
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@ -0,0 +1,124 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* rt722-sdca-sdw.h -- RT722 SDCA ALSA SoC audio driver header
*
* Copyright(c) 2023 Realtek Semiconductor Corp.
*/
#ifndef __RT722_SDW_H__
#define __RT722_SDW_H__
#include <linux/regmap.h>
#include <linux/soundwire/sdw_registers.h>
static const struct reg_default rt722_sdca_reg_defaults[] = {
{ 0x202d, 0x00 },
{ 0x2f01, 0x00 },
{ 0x2f02, 0x09 },
{ 0x2f03, 0x00 },
{ 0x2f04, 0x00 },
{ 0x2f05, 0x0b },
{ 0x2f06, 0x01 },
{ 0x2f08, 0x00 },
{ 0x2f09, 0x00 },
{ 0x2f0a, 0x00 },
{ 0x2f35, 0x00 },
{ 0x2f36, 0x00 },
{ 0x2f50, 0xf0 },
{ 0x2f58, 0x07 },
{ 0x2f59, 0x07 },
{ 0x2f5a, 0x07 },
{ 0x2f5b, 0x07 },
{ 0x2f5c, 0x27 },
{ 0x2f5d, 0x07 },
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS01, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX,
0), 0x09 },
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_CS11, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX,
0), 0x09 },
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE12, RT722_SDCA_CTL_REQ_POWER_STATE,
0), 0x03 },
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PDE40, RT722_SDCA_CTL_REQ_POWER_STATE,
0), 0x03 },
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_MUTE, CH_L),
0x01 },
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_MUTE, CH_R),
0x01 },
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_MUTE, CH_L),
0x01 },
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_MUTE, CH_R),
0x01 },
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_CS1F, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX,
0), 0x09 },
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_01),
0x01 },
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_02),
0x01 },
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_03),
0x01 },
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_MUTE, CH_04),
0x01 },
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_PDE2A, RT722_SDCA_CTL_REQ_POWER_STATE, 0),
0x03 },
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_IT26, RT722_SDCA_CTL_VENDOR_DEF, 0),
0x00 },
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_CS31, RT722_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
0x09 },
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_MUTE, CH_L),
0x01 },
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_MUTE, CH_R),
0x01 },
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_PDE23, RT722_SDCA_CTL_REQ_POWER_STATE, 0),
0x03 },
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_OT23, RT722_SDCA_CTL_VENDOR_DEF, 0), 0x00 },
};
static const struct reg_default rt722_sdca_mbq_defaults[] = {
{ 0x200003c, 0xc214 },
{ 0x2000046, 0x8004 },
{ 0x6100006, 0x0005 },
{ 0x6100010, 0x2630 },
{ 0x6100011, 0x152f },
{ 0x6100013, 0x0102 },
{ 0x6100015, 0x2200 },
{ 0x6100017, 0x0102 },
{ 0x6100025, 0x2a29 },
{ 0x6100026, 0x2a00 },
{ 0x6100028, 0x2a2a },
{ 0x6100029, 0x4141 },
{ 0x6100055, 0x0000 },
{ 0x5810000, 0x702d },
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME,
CH_L), 0x0000 },
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU05, RT722_SDCA_CTL_FU_VOLUME,
CH_R), 0x0000 },
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME,
CH_L), 0x0000 },
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_USER_FU0F, RT722_SDCA_CTL_FU_VOLUME,
CH_R), 0x0000 },
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, RT722_SDCA_CTL_FU_CH_GAIN,
CH_L), 0x0000 },
{ SDW_SDCA_CTL(FUNC_NUM_JACK_CODEC, RT722_SDCA_ENT_PLATFORM_FU44, RT722_SDCA_CTL_FU_CH_GAIN,
CH_R), 0x0000 },
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
CH_01), 0x0000 },
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
CH_02), 0x0000 },
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
CH_03), 0x0000 },
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_USER_FU1E, RT722_SDCA_CTL_FU_VOLUME,
CH_04), 0x0000 },
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_01),
0x0000 },
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_02),
0x0000 },
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_03),
0x0000 },
{ SDW_SDCA_CTL(FUNC_NUM_MIC_ARRAY, RT722_SDCA_ENT_FU15, RT722_SDCA_CTL_FU_CH_GAIN, CH_04),
0x0000 },
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_L),
0x0000 },
{ SDW_SDCA_CTL(FUNC_NUM_AMP, RT722_SDCA_ENT_USER_FU06, RT722_SDCA_CTL_FU_VOLUME, CH_R),
0x0000 },
};
#endif /* __RT722_SDW_H__ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* rt722-sdca.h -- RT722 SDCA ALSA SoC audio driver header
*
* Copyright(c) 2023 Realtek Semiconductor Corp.
*/
#ifndef __RT722_H__
#define __RT722_H__
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>
#include <sound/soc.h>
#include <linux/workqueue.h>
struct rt722_sdca_priv {
struct regmap *regmap;
struct regmap *mbq_regmap;
struct snd_soc_component *component;
struct sdw_slave *slave;
enum sdw_slave_status status;
struct sdw_bus_params params;
bool hw_init;
bool first_hw_init;
struct mutex calibrate_mutex;
struct mutex disable_irq_lock;
bool disable_irq;
/* For Headset jack & Headphone */
unsigned int scp_sdca_stat1;
unsigned int scp_sdca_stat2;
struct snd_soc_jack *hs_jack;
struct delayed_work jack_detect_work;
struct delayed_work jack_btn_check_work;
int jack_type;
int jd_src;
bool fu0f_dapm_mute;
bool fu0f_mixer_l_mute;
bool fu0f_mixer_r_mute;
/* For DMIC */
bool fu1e_dapm_mute;
bool fu1e_mixer_mute[4];
};
struct rt722_sdca_dmic_kctrl_priv {
unsigned int reg_base;
unsigned int count;
unsigned int max;
unsigned int invert;
};
/* NID */
#define RT722_VENDOR_REG 0x20
#define RT722_VENDOR_CALI 0x58
#define RT722_VENDOR_SPK_EFUSE 0x5c
#define RT722_VENDOR_IMS_DRE 0x5b
#define RT722_VENDOR_ANALOG_CTL 0x5f
#define RT722_VENDOR_HDA_CTL 0x61
/* Index (NID:20h) */
#define RT722_JD_PRODUCT_NUM 0x00
#define RT722_ANALOG_BIAS_CTL3 0x04
#define RT722_JD_CTRL1 0x09
#define RT722_LDO2_3_CTL1 0x0e
#define RT722_LDO1_CTL 0x1a
#define RT722_HP_JD_CTRL 0x24
#define RT722_CLSD_CTRL6 0x3c
#define RT722_COMBO_JACK_AUTO_CTL1 0x45
#define RT722_COMBO_JACK_AUTO_CTL2 0x46
#define RT722_COMBO_JACK_AUTO_CTL3 0x47
#define RT722_DIGITAL_MISC_CTRL4 0x4a
#define RT722_FSM_CTL 0x67
#define RT722_SDCA_INTR_REC 0x82
#define RT722_SW_CONFIG1 0x8a
#define RT722_SW_CONFIG2 0x8b
/* Index (NID:58h) */
#define RT722_DAC_DC_CALI_CTL0 0x00
#define RT722_DAC_DC_CALI_CTL1 0x01
#define RT722_DAC_DC_CALI_CTL2 0x02
#define RT722_DAC_DC_CALI_CTL3 0x03
/* Index (NID:59h) */
#define RT722_ULTRA_SOUND_DETECTOR6 0x1e
/* Index (NID:5bh) */
#define RT722_IMS_DIGITAL_CTL1 0x00
#define RT722_IMS_DIGITAL_CTL5 0x05
#define RT722_HP_DETECT_RLDET_CTL1 0x29
#define RT722_HP_DETECT_RLDET_CTL2 0x2a
/* Index (NID:5fh) */
#define RT722_MISC_POWER_CTL0 0x00
#define RT722_MISC_POWER_CTL7 0x08
/* Index (NID:61h) */
#define RT722_HDA_LEGACY_MUX_CTL0 0x00
#define RT722_HDA_LEGACY_UNSOL_CTL 0x03
#define RT722_HDA_LEGACY_CONFIG_CTL0 0x06
#define RT722_HDA_LEGACY_RESET_CTL 0x08
#define RT722_HDA_LEGACY_GPIO_WAKE_EN_CTL 0x0e
#define RT722_DMIC_ENT_FLOAT_CTL 0x10
#define RT722_DMIC_GAIN_ENT_FLOAT_CTL0 0x11
#define RT722_DMIC_GAIN_ENT_FLOAT_CTL2 0x13
#define RT722_ADC_ENT_FLOAT_CTL 0x15
#define RT722_ADC_VOL_CH_FLOAT_CTL 0x17
#define RT722_ADC_SAMPLE_RATE_FLOAT 0x18
#define RT722_DAC03_HP_PDE_FLOAT_CTL 0x22
#define RT722_MIC2_LINE2_PDE_FLOAT_CTL 0x23
#define RT722_ET41_LINE2_PDE_FLOAT_CTL 0x24
#define RT722_ADC0A_08_PDE_FLOAT_CTL 0x25
#define RT722_ADC10_PDE_FLOAT_CTL 0x26
#define RT722_DMIC1_2_PDE_FLOAT_CTL 0x28
#define RT722_AMP_PDE_FLOAT_CTL 0x29
#define RT722_I2S_IN_OUT_PDE_FLOAT_CTL 0x2f
#define RT722_GE_RELATED_CTL1 0x45
#define RT722_GE_RELATED_CTL2 0x46
#define RT722_MIXER_CTL0 0x52
#define RT722_MIXER_CTL1 0x53
#define RT722_EAPD_CTL 0x55
#define RT722_UMP_HID_CTL0 0x60
#define RT722_UMP_HID_CTL1 0x61
#define RT722_UMP_HID_CTL2 0x62
#define RT722_UMP_HID_CTL3 0x63
#define RT722_UMP_HID_CTL4 0x64
#define RT722_UMP_HID_CTL5 0x65
#define RT722_UMP_HID_CTL6 0x66
#define RT722_UMP_HID_CTL7 0x67
#define RT722_UMP_HID_CTL8 0x68
/* Parameter & Verb control 01 (0x1a)(NID:20h) */
#define RT722_HIDDEN_REG_SW_RESET (0x1 << 14)
/* combo jack auto switch control 2 (0x46)(NID:20h) */
#define RT722_COMBOJACK_AUTO_DET_STATUS (0x1 << 11)
#define RT722_COMBOJACK_AUTO_DET_TRS (0x1 << 10)
#define RT722_COMBOJACK_AUTO_DET_CTIA (0x1 << 9)
#define RT722_COMBOJACK_AUTO_DET_OMTP (0x1 << 8)
/* DAC calibration control (0x00)(NID:58h) */
#define RT722_DC_CALIB_CTRL (0x1 << 16)
/* DAC DC offset calibration control-1 (0x01)(NID:58h) */
#define RT722_PDM_DC_CALIB_STATUS (0x1 << 15)
#define RT722_EAPD_HIGH 0x2
#define RT722_EAPD_LOW 0x0
/* Buffer address for HID */
#define RT722_BUF_ADDR_HID1 0x44030000
#define RT722_BUF_ADDR_HID2 0x44030020
/* RT722 SDCA Control - function number */
#define FUNC_NUM_JACK_CODEC 0x01
#define FUNC_NUM_MIC_ARRAY 0x02
#define FUNC_NUM_HID 0x03
#define FUNC_NUM_AMP 0x04
/* RT722 SDCA entity */
#define RT722_SDCA_ENT_HID01 0x01
#define RT722_SDCA_ENT_GE49 0x49
#define RT722_SDCA_ENT_USER_FU05 0x05
#define RT722_SDCA_ENT_USER_FU06 0x06
#define RT722_SDCA_ENT_USER_FU0F 0x0f
#define RT722_SDCA_ENT_USER_FU10 0x19
#define RT722_SDCA_ENT_USER_FU1E 0x1e
#define RT722_SDCA_ENT_FU15 0x15
#define RT722_SDCA_ENT_PDE23 0x23
#define RT722_SDCA_ENT_PDE40 0x40
#define RT722_SDCA_ENT_PDE11 0x11
#define RT722_SDCA_ENT_PDE12 0x12
#define RT722_SDCA_ENT_PDE2A 0x2a
#define RT722_SDCA_ENT_CS01 0x01
#define RT722_SDCA_ENT_CS11 0x11
#define RT722_SDCA_ENT_CS1F 0x1f
#define RT722_SDCA_ENT_CS1C 0x1c
#define RT722_SDCA_ENT_CS31 0x31
#define RT722_SDCA_ENT_OT23 0x42
#define RT722_SDCA_ENT_IT26 0x26
#define RT722_SDCA_ENT_IT09 0x09
#define RT722_SDCA_ENT_PLATFORM_FU15 0x15
#define RT722_SDCA_ENT_PLATFORM_FU44 0x44
#define RT722_SDCA_ENT_XU03 0x03
#define RT722_SDCA_ENT_XU0D 0x0d
/* RT722 SDCA control */
#define RT722_SDCA_CTL_SAMPLE_FREQ_INDEX 0x10
#define RT722_SDCA_CTL_FU_MUTE 0x01
#define RT722_SDCA_CTL_FU_VOLUME 0x02
#define RT722_SDCA_CTL_HIDTX_CURRENT_OWNER 0x10
#define RT722_SDCA_CTL_HIDTX_SET_OWNER_TO_DEVICE 0x11
#define RT722_SDCA_CTL_HIDTX_MESSAGE_OFFSET 0x12
#define RT722_SDCA_CTL_HIDTX_MESSAGE_LENGTH 0x13
#define RT722_SDCA_CTL_SELECTED_MODE 0x01
#define RT722_SDCA_CTL_DETECTED_MODE 0x02
#define RT722_SDCA_CTL_REQ_POWER_STATE 0x01
#define RT722_SDCA_CTL_VENDOR_DEF 0x30
#define RT722_SDCA_CTL_FU_CH_GAIN 0x0b
/* RT722 SDCA channel */
#define CH_L 0x01
#define CH_R 0x02
#define CH_01 0x01
#define CH_02 0x02
#define CH_03 0x03
#define CH_04 0x04
#define CH_08 0x08
/* sample frequency index */
#define RT722_SDCA_RATE_16000HZ 0x04
#define RT722_SDCA_RATE_32000HZ 0x07
#define RT722_SDCA_RATE_44100HZ 0x08
#define RT722_SDCA_RATE_48000HZ 0x09
#define RT722_SDCA_RATE_96000HZ 0x0b
#define RT722_SDCA_RATE_192000HZ 0x0d
enum {
RT722_AIF1, /* For headset mic and headphone */
RT722_AIF2, /* For speaker */
RT722_AIF3, /* For dmic */
RT722_AIFS,
};
enum rt722_sdca_jd_src {
RT722_JD_NULL,
RT722_JD1,
};
int rt722_sdca_io_init(struct device *dev, struct sdw_slave *slave);
int rt722_sdca_init(struct device *dev, struct regmap *regmap,
struct regmap *mbq_regmap, struct sdw_slave *slave);
int rt722_sdca_index_write(struct rt722_sdca_priv *rt722,
unsigned int nid, unsigned int reg, unsigned int value);
int rt722_sdca_index_read(struct rt722_sdca_priv *rt722,
unsigned int nid, unsigned int reg, unsigned int *value);
int rt722_sdca_jack_detect(struct rt722_sdca_priv *rt722, bool *hp, bool *mic);
#endif /* __RT722_H__ */