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pwm: mediatek: Prevent divide-by-zero in pwm_mediatek_config()

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With CONFIG_COMPILE_TEST && !CONFIG_HAVE_CLK, pwm_mediatek_config() has a
divide-by-zero in the following line:

	do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm]));

due to the fact that the !CONFIG_HAVE_CLK version of clk_get_rate()
returns zero.

This is presumably just a theoretical problem: COMPILE_TEST overrides
the dependency on RALINK which would select COMMON_CLK.  Regardless it's
a good idea to check for the error explicitly to avoid divide-by-zero.

Fixes the following warning:

  drivers/pwm/pwm-mediatek.o: warning: objtool: .text: unexpected end of section

Signed-off-by: Josh Poimboeuf <jpoimboe@kernel.org>
Link: https://lore.kernel.org/r/fb56444939325cc173e752ba199abd7aeae3bf12.1742852847.git.jpoimboe@kernel.org
[ukleinek: s/CONFIG_CLK/CONFIG_HAVE_CLK/]
Fixes: caf065f8fd ("pwm: Add MediaTek PWM support")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com>
Link: https://lore.kernel.org/r/9e78a0796acba3435553ed7db1c7965dcffa6215.1743501688.git.u.kleine-koenig@baylibre.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
This commit is contained in:
Josh Poimboeuf 2025-04-01 12:28:59 +02:00 • committed by Uwe Kleine-König
parent 6df320abbb
commit 7ca59947b5
1 changed files with 6 additions and 2 deletions
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8
drivers/pwm/pwm-mediatek.c
View file

@ -121,21 +121,25 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip);
u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH,
reg_thres = PWMTHRES; reg_thres = PWMTHRES;
unsigned long clk_rate;
u64 resolution; u64 resolution;
int ret; int ret;
ret = pwm_mediatek_clk_enable(chip, pwm); ret = pwm_mediatek_clk_enable(chip, pwm);
if (ret < 0) if (ret < 0)
return ret; return ret;
clk_rate = clk_get_rate(pc->clk_pwms[pwm->hwpwm]);
if (!clk_rate)
return -EINVAL;
/* Make sure we use the bus clock and not the 26MHz clock */ /* Make sure we use the bus clock and not the 26MHz clock */
if (pc->soc->has_ck_26m_sel) if (pc->soc->has_ck_26m_sel)
writel(0, pc->regs + PWM_CK_26M_SEL); writel(0, pc->regs + PWM_CK_26M_SEL);
/* Using resolution in picosecond gets accuracy higher */ /* Using resolution in picosecond gets accuracy higher */
resolution = (u64)NSEC_PER_SEC * 1000; resolution = (u64)NSEC_PER_SEC * 1000;
do_div(resolution, clk_get_rate(pc->clk_pwms[pwm->hwpwm])); do_div(resolution, clk_rate);
cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution);
while (cnt_period > 8191) { while (cnt_period > 8191) {