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drm/amdgpu/soc15: convert to IP version checking
Use IP versions rather than asic_type to differentiate IP version specific features. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher
parent
0b64a5a852
commit
75a07bcd1d
1 changed files with 88 additions and 71 deletions
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@ -156,31 +156,38 @@ static const struct amdgpu_video_codecs rn_video_codecs_decode =
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static int soc15_query_video_codecs(struct amdgpu_device *adev, bool encode,
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const struct amdgpu_video_codecs **codecs)
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{
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switch (adev->asic_type) {
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case CHIP_VEGA20:
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case CHIP_VEGA10:
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case CHIP_VEGA12:
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if (encode)
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*codecs = &vega_video_codecs_encode;
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else
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*codecs = &vega_video_codecs_decode;
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return 0;
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case CHIP_RAVEN:
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if (encode)
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*codecs = &vega_video_codecs_encode;
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else
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*codecs = &rv_video_codecs_decode;
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return 0;
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case CHIP_ARCTURUS:
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case CHIP_ALDEBARAN:
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case CHIP_RENOIR:
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if (encode)
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*codecs = &vega_video_codecs_encode;
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else
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*codecs = &rn_video_codecs_decode;
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return 0;
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default:
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return -EINVAL;
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if (adev->ip_versions[VCE_HWIP]) {
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switch (adev->ip_versions[VCE_HWIP]) {
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case IP_VERSION(4, 0, 0):
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case IP_VERSION(4, 1, 0):
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if (encode)
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*codecs = &vega_video_codecs_encode;
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else
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*codecs = &vega_video_codecs_decode;
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return 0;
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default:
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return -EINVAL;
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}
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} else {
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switch (adev->ip_versions[UVD_HWIP]) {
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case IP_VERSION(1, 0, 0):
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case IP_VERSION(1, 0, 1):
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if (encode)
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*codecs = &vega_video_codecs_encode;
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else
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*codecs = &rv_video_codecs_decode;
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return 0;
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case IP_VERSION(2, 5, 0):
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case IP_VERSION(2, 6, 0):
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case IP_VERSION(2, 2, 0):
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if (encode)
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*codecs = &vega_video_codecs_encode;
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else
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*codecs = &rn_video_codecs_decode;
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return 0;
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default:
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return -EINVAL;
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}
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}
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}
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@ -334,9 +341,11 @@ static u32 soc15_get_xclk(struct amdgpu_device *adev)
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{
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u32 reference_clock = adev->clock.spll.reference_freq;
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if (adev->asic_type == CHIP_RENOIR)
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if (adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 0) ||
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adev->ip_versions[MP1_HWIP] == IP_VERSION(12, 0, 1))
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return 10000;
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if (adev->asic_type == CHIP_RAVEN)
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if (adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 0) ||
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adev->ip_versions[MP1_HWIP] == IP_VERSION(10, 0, 1))
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return reference_clock / 4;
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return reference_clock;
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@ -567,28 +576,29 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
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dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
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amdgpu_reset_method);
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switch (adev->asic_type) {
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case CHIP_RAVEN:
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case CHIP_RENOIR:
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switch (adev->ip_versions[MP1_HWIP]) {
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case IP_VERSION(10, 0, 0):
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case IP_VERSION(10, 0, 1):
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case IP_VERSION(12, 0, 0):
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case IP_VERSION(12, 0, 1):
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return AMD_RESET_METHOD_MODE2;
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case CHIP_VEGA10:
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case CHIP_VEGA12:
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case CHIP_ARCTURUS:
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baco_reset = amdgpu_dpm_is_baco_supported(adev);
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break;
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case CHIP_VEGA20:
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if (adev->psp.sos.fw_version >= 0x80067)
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case IP_VERSION(9, 0, 0):
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case IP_VERSION(11, 0, 2):
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if (adev->asic_type == CHIP_VEGA20) {
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if (adev->psp.sos.fw_version >= 0x80067)
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baco_reset = amdgpu_dpm_is_baco_supported(adev);
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/*
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* 1. PMFW version > 0x284300: all cases use baco
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* 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
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*/
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if (ras && adev->ras_enabled &&
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adev->pm.fw_version <= 0x283400)
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baco_reset = false;
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} else {
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baco_reset = amdgpu_dpm_is_baco_supported(adev);
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/*
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* 1. PMFW version > 0x284300: all cases use baco
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* 2. PMFW version <= 0x284300: only sGPU w/o RAS use baco
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*/
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if (ras && adev->ras_enabled &&
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adev->pm.fw_version <= 0x283400)
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baco_reset = false;
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}
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break;
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case CHIP_ALDEBARAN:
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case IP_VERSION(13, 0, 2):
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/*
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* 1.connected to cpu: driver issue mode2 reset
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* 2.discret gpu: driver issue mode1 reset
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@ -631,15 +641,17 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
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static bool soc15_supports_baco(struct amdgpu_device *adev)
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{
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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case CHIP_VEGA12:
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case CHIP_ARCTURUS:
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return amdgpu_dpm_is_baco_supported(adev);
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case CHIP_VEGA20:
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if (adev->psp.sos.fw_version >= 0x80067)
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switch (adev->ip_versions[MP1_HWIP]) {
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case IP_VERSION(9, 0, 0):
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case IP_VERSION(11, 0, 2):
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if (adev->asic_type == CHIP_VEGA20) {
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if (adev->psp.sos.fw_version >= 0x80067)
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return amdgpu_dpm_is_baco_supported(adev);
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return false;
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} else {
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return amdgpu_dpm_is_baco_supported(adev);
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return false;
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}
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break;
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default:
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return false;
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}
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@ -1157,8 +1169,11 @@ static int soc15_common_early_init(void *handle)
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adev->rev_id = soc15_get_rev_id(adev);
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adev->external_rev_id = 0xFF;
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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/* TODO: split the GC and PG flags based on the relevant IP version for which
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* they are relevant.
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*/
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switch (adev->ip_versions[GC_HWIP]) {
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case IP_VERSION(9, 0, 1):
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adev->asic_funcs = &soc15_asic_funcs;
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adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
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AMD_CG_SUPPORT_GFX_MGLS |
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@ -1182,7 +1197,7 @@ static int soc15_common_early_init(void *handle)
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adev->pg_flags = 0;
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adev->external_rev_id = 0x1;
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break;
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case CHIP_VEGA12:
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case IP_VERSION(9, 2, 1):
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adev->asic_funcs = &soc15_asic_funcs;
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adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
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AMD_CG_SUPPORT_GFX_MGLS |
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@ -1205,7 +1220,7 @@ static int soc15_common_early_init(void *handle)
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adev->pg_flags = 0;
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adev->external_rev_id = adev->rev_id + 0x14;
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break;
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case CHIP_VEGA20:
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case IP_VERSION(9, 4, 0):
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adev->asic_funcs = &vega20_asic_funcs;
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adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
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AMD_CG_SUPPORT_GFX_MGLS |
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@ -1228,7 +1243,8 @@ static int soc15_common_early_init(void *handle)
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adev->pg_flags = 0;
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adev->external_rev_id = adev->rev_id + 0x28;
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break;
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case CHIP_RAVEN:
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case IP_VERSION(9, 1, 0):
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case IP_VERSION(9, 2, 2):
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adev->asic_funcs = &soc15_asic_funcs;
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if (adev->rev_id >= 0x8)
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@ -1301,7 +1317,7 @@ static int soc15_common_early_init(void *handle)
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adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN;
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}
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break;
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case CHIP_ARCTURUS:
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case IP_VERSION(9, 4, 1):
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adev->asic_funcs = &vega20_asic_funcs;
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adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
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AMD_CG_SUPPORT_GFX_MGLS |
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@ -1320,7 +1336,7 @@ static int soc15_common_early_init(void *handle)
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adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG;
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adev->external_rev_id = adev->rev_id + 0x32;
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break;
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case CHIP_RENOIR:
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case IP_VERSION(9, 3, 0):
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adev->asic_funcs = &soc15_asic_funcs;
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if (adev->apu_flags & AMD_APU_IS_RENOIR)
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@ -1351,7 +1367,7 @@ static int soc15_common_early_init(void *handle)
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AMD_PG_SUPPORT_JPEG |
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AMD_PG_SUPPORT_VCN_DPG;
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break;
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case CHIP_ALDEBARAN:
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case IP_VERSION(9, 4, 2):
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adev->asic_funcs = &vega20_asic_funcs;
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adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
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AMD_CG_SUPPORT_GFX_MGLS |
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@ -1566,10 +1582,10 @@ static int soc15_common_set_clockgating_state(void *handle,
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if (amdgpu_sriov_vf(adev))
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return 0;
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switch (adev->asic_type) {
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case CHIP_VEGA10:
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case CHIP_VEGA12:
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case CHIP_VEGA20:
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switch (adev->ip_versions[NBIO_HWIP]) {
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case IP_VERSION(6, 1, 0):
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case IP_VERSION(6, 2, 0):
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case IP_VERSION(7, 4, 0):
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adev->nbio.funcs->update_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE);
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adev->nbio.funcs->update_medium_grain_light_sleep(adev,
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@ -1585,8 +1601,9 @@ static int soc15_common_set_clockgating_state(void *handle,
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adev->df.funcs->update_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE);
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break;
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case CHIP_RAVEN:
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case CHIP_RENOIR:
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case IP_VERSION(7, 0, 0):
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case IP_VERSION(7, 0, 1):
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case IP_VERSION(2, 5, 0):
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adev->nbio.funcs->update_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE);
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adev->nbio.funcs->update_medium_grain_light_sleep(adev,
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@ -1598,8 +1615,8 @@ static int soc15_common_set_clockgating_state(void *handle,
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soc15_update_drm_light_sleep(adev,
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state == AMD_CG_STATE_GATE);
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break;
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case CHIP_ARCTURUS:
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case CHIP_ALDEBARAN:
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case IP_VERSION(7, 4, 1):
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case IP_VERSION(7, 4, 4):
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adev->hdp.funcs->update_clock_gating(adev,
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state == AMD_CG_STATE_GATE);
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break;
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@ -1621,7 +1638,7 @@ static void soc15_common_get_clockgating_state(void *handle, u32 *flags)
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adev->hdp.funcs->get_clock_gating_state(adev, flags);
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if (adev->asic_type != CHIP_ALDEBARAN) {
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if (adev->ip_versions[MP0_HWIP] != IP_VERSION(13, 0, 2)) {
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/* AMD_CG_SUPPORT_DRM_MGCG */
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data = RREG32(SOC15_REG_OFFSET(MP0, 0, mmMP0_MISC_CGTT_CTRL0));
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